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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -passes=loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -mtriple=riscv64 -mattr=+v -S %s | FileCheck %s3 4; Make sure we don't crash when transforming a VPWidenCastRecipe created without5; an underlying value to an EVL recipe. This occurs in this test via6; VPlanTransforms::truncateToMinimalBitwidths7 8define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr %src) {9; CHECK-LABEL: define void @truncate_to_minimal_bitwidths_widen_cast_recipe(10; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {11; CHECK-NEXT: [[ENTRY:.*:]]12; CHECK-NEXT: br label %[[VECTOR_PH:.*]]13; CHECK: [[VECTOR_PH]]:14; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]15; CHECK: [[VECTOR_BODY]]:16; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 9, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]17; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true)18; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i8.nxv8p0(<vscale x 8 x i8> zeroinitializer, <vscale x 8 x ptr> align 1 zeroinitializer, <vscale x 8 x i1> splat (i1 true), i32 [[TMP7]])19; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP7]] to i6420; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP9]]21; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[AVL_NEXT]], 022; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]23; CHECK: [[MIDDLE_BLOCK]]:24; CHECK-NEXT: br label %[[EXIT:.*]]25; CHECK: [[EXIT]]:26; CHECK-NEXT: ret void27;28entry:29 br label %loop30 31loop: ; preds = %loop, %entry32 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]33 %gep.src = getelementptr i8, ptr %src, i64 %iv34 %0 = load i8, ptr %gep.src, align 135 %conv = zext i8 %0 to i3236 %mul16 = mul i32 0, %conv37 %shr35 = lshr i32 %mul16, 138 %conv36 = trunc i32 %shr35 to i839 store i8 %conv36, ptr null, align 140 %iv.next = add i64 %iv, 141 %ec = icmp eq i64 %iv, 842 br i1 %ec, label %exit, label %loop43 44exit: ; preds = %loop45 ret void46}47 48; Test case for https://github.com/llvm/llvm-project/issues/162374.49define void @truncate_i16_to_i8_cse(ptr noalias %src, ptr noalias %dst) {50; CHECK-LABEL: define void @truncate_i16_to_i8_cse(51; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR0]] {52; CHECK-NEXT: [[ENTRY:.*]]:53; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()54; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 355; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 4294967296, [[TMP1]]56; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]57; CHECK: [[VECTOR_PH]]:58; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()59; CHECK-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 860; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 4294967296, [[TMP3]]61; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 4294967296, [[N_MOD_VF]]62; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[N_VEC]] to i3263; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]64; CHECK: [[VECTOR_BODY]]:65; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]66; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[SRC]], align 267; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[TMP5]], i64 068; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[BROADCAST_SPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer69; CHECK-NEXT: [[TMP6:%.*]] = trunc <vscale x 8 x i16> [[BROADCAST_SPLAT]] to <vscale x 8 x i8>70; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vscale.i32()71; CHECK-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 872; CHECK-NEXT: [[TMP9:%.*]] = sub i32 [[TMP8]], 173; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 8 x i8> [[TMP6]], i32 [[TMP9]]74; CHECK-NEXT: store i8 [[TMP10]], ptr null, align 175; CHECK-NEXT: store i8 [[TMP10]], ptr [[DST]], align 176; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]77; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]78; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]79; CHECK: [[MIDDLE_BLOCK]]:80; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 4294967296, [[N_VEC]]81; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]82; CHECK: [[SCALAR_PH]]:83; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]84; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]85; CHECK-NEXT: br label %[[LOOP:.*]]86; CHECK: [[LOOP]]:87; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]88; CHECK-NEXT: [[COUNT:%.*]] = phi i32 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[COUNT_NEXT:%.*]], %[[LOOP]] ]89; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr [[SRC]], align 290; CHECK-NEXT: [[VAL_ZEXT:%.*]] = zext i16 [[VAL]] to i6491; CHECK-NEXT: [[VAL_TRUNC_ZEXT:%.*]] = trunc i64 [[VAL_ZEXT]] to i892; CHECK-NEXT: store i8 [[VAL_TRUNC_ZEXT]], ptr null, align 193; CHECK-NEXT: [[VAL_TRUNC:%.*]] = trunc i16 [[VAL]] to i894; CHECK-NEXT: store i8 [[VAL_TRUNC]], ptr [[DST]], align 195; CHECK-NEXT: [[COUNT_NEXT]] = add i32 [[COUNT]], 196; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[COUNT_NEXT]], 097; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 198; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]99; CHECK: [[EXIT]]:100; CHECK-NEXT: ret void101;102entry:103 br label %loop104 105loop: ; preds = %loop, %entry106 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]107 %count = phi i32 [ 0, %entry ], [ %count.next, %loop ]108 %val = load i16, ptr %src, align 2109 %val.zext = zext i16 %val to i64110 %val.trunc.zext = trunc i64 %val.zext to i8111 store i8 %val.trunc.zext, ptr null, align 1112 %val.trunc = trunc i16 %val to i8113 store i8 %val.trunc, ptr %dst, align 1114 %count.next = add i32 %count, 1115 %exitcond = icmp eq i32 %count.next, 0116 %iv.next = add i64 %iv, 1117 br i1 %exitcond, label %exit, label %loop118 119exit: ; preds = %loop120 ret void121}122 123;.124; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}125; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}126; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}127; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}128; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META2]], [[META1]]}129;.130