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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt %s -S -mtriple riscv64 -passes=loop-vectorize --prefer-predicate-over-epilogue=predicate-dont-vectorize -force-tail-folding-style=data-with-evl -riscv-v-min-trip-count=0 -force-target-instruction-cost=1 -mattr=+v | FileCheck %s3 4; Check canonical-iv is removed in single-iteration loop5define void @foo(ptr %arg) #0 {6; CHECK-LABEL: define void @foo(7; CHECK-SAME: ptr [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {8; CHECK-NEXT: [[ENTRY:.*:]]9; CHECK-NEXT: br label %[[VECTOR_PH:.*]]10; CHECK: [[VECTOR_PH]]:11; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]12; CHECK: [[VECTOR_BODY]]:13; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> zeroinitializer, ptr align 8 [[ARG]], <vscale x 2 x i1> splat (i1 true), i32 3)14; CHECK-NEXT: br label %[[MIDDLE_BLOCK:.*]]15; CHECK: [[MIDDLE_BLOCK]]:16; CHECK-NEXT: br label %[[EXIT:.*]]17; CHECK: [[EXIT]]:18; CHECK-NEXT: ret void19;20entry:21 br label %loop22 23loop:24 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]25 %gep = getelementptr [3 x i64], ptr %arg, i64 0, i64 %iv26 store i64 0, ptr %gep, align 827 %iv.next = add i64 %iv, 128 %cond = icmp eq i64 %iv.next, 329 br i1 %cond, label %exit, label %loop30 31exit:32 ret void33}34 35define i32 @test_remove_iv(i32 %start) #0 {36; CHECK-LABEL: define i32 @test_remove_iv(37; CHECK-SAME: i32 [[START:%.*]]) #[[ATTR0]] {38; CHECK-NEXT: [[ENTRY:.*:]]39; CHECK-NEXT: br label %[[VECTOR_PH:.*]]40; CHECK: [[VECTOR_PH]]:41; CHECK-NEXT: [[TMP2:%.*]] = insertelement <vscale x 4 x i32> zeroinitializer, i32 [[START]], i32 042; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]43; CHECK: [[VECTOR_BODY]]:44; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[TMP2]], %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]45; CHECK-NEXT: [[AVL:%.*]] = phi i32 [ 6, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]46; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 4, i1 true)47; CHECK-NEXT: [[TMP4:%.*]] = xor <vscale x 4 x i32> [[VEC_PHI]], splat (i32 3)48; CHECK-NEXT: [[TMP5]] = call <vscale x 4 x i32> @llvm.vp.merge.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[TMP4]], <vscale x 4 x i32> [[VEC_PHI]], i32 [[TMP3]])49; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP3]]50; CHECK-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]51; CHECK: [[MIDDLE_BLOCK]]:52; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32> [[TMP5]])53; CHECK-NEXT: br label %[[EXIT:.*]]54; CHECK: [[EXIT]]:55; CHECK-NEXT: ret i32 [[TMP6]]56;57entry:58 br label %loop59 60loop:61 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]62 %red = phi i32 [ %start , %entry ], [ %red.next, %loop ]63 %red.next = xor i32 %red, 364 %iv.next = add i32 %iv, 165 %ec = icmp eq i32 %iv, 566 br i1 %ec, label %exit, label %loop67 68exit:69 ret i32 %red.next70}71 72attributes #0 = { vscale_range(2,2) }73 74;.75; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}76; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}77; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}78;.79