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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -mattr=+v -passes=loop-vectorize -S %s | FileCheck %s3 4target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"5target triple = "riscv64-unknown-unknown-elf"6 7define void @vf_will_not_generate_any_vector_insts(ptr %src, ptr %dst) {8; CHECK-LABEL: define void @vf_will_not_generate_any_vector_insts(9; CHECK-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]]) #[[ATTR0:[0-9]+]] {10; CHECK-NEXT: [[ENTRY:.*:]]11; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]12; CHECK: [[VECTOR_MEMCHECK]]:13; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 414; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SRC]], i64 415; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP1]]16; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SRC]], [[SCEVGEP]]17; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]18; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]19; CHECK: [[VECTOR_PH]]:20; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[SRC]], align 4, !alias.scope [[META0:![0-9]+]]21; CHECK-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[TMP0]], i64 022; CHECK-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT2]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer23; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x ptr> poison, ptr [[DST]], i64 024; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 4 x ptr> poison, <vscale x 4 x i32> zeroinitializer25; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]26; CHECK: [[VECTOR_BODY]]:27; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 100, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]28; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)29; CHECK-NEXT: call void @llvm.vp.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> [[BROADCAST_SPLAT3]], <vscale x 4 x ptr> align 4 [[BROADCAST_SPLAT]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP5]]), !alias.scope [[META3:![0-9]+]], !noalias [[META0]]30; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP5]] to i6431; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP7]]32; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[AVL_NEXT]], 033; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]34; CHECK: [[MIDDLE_BLOCK]]:35; CHECK-NEXT: br label %[[EXIT:.*]]36; CHECK: [[SCALAR_PH]]:37; CHECK-NEXT: br label %[[LOOP:.*]]38; CHECK: [[LOOP]]:39; CHECK-NEXT: [[TMP2:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[TMP3:%.*]], %[[LOOP]] ]40; CHECK-NEXT: [[DOTPRE:%.*]] = load i32, ptr [[SRC]], align 441; CHECK-NEXT: store i32 [[DOTPRE]], ptr [[DST]], align 442; CHECK-NEXT: [[TMP3]] = add nuw i64 [[TMP2]], 143; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[TMP3]], 10044; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]45; CHECK: [[EXIT]]:46; CHECK-NEXT: ret void47;48entry:49 br label %loop50 51loop:52 %0 = phi i64 [ 0, %entry ], [ %1, %loop ]53 %.pre = load i32, ptr %src, align 454 store i32 %.pre, ptr %dst, align 455 %1 = add nuw i64 %0, 156 %ec = icmp eq i64 %1, 10057 br i1 %ec, label %exit, label %loop58 59exit:60 ret void61}62;.63; CHECK: [[META0]] = !{[[META1:![0-9]+]]}64; CHECK: [[META1]] = distinct !{[[META1]], [[META2:![0-9]+]]}65; CHECK: [[META2]] = distinct !{[[META2]], !"LVerDomain"}66; CHECK: [[META3]] = !{[[META4:![0-9]+]]}67; CHECK: [[META4]] = distinct !{[[META4]], [[META2]]}68; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META6:![0-9]+]], [[META7:![0-9]+]]}69; CHECK: [[META6]] = !{!"llvm.loop.isvectorized", i32 1}70; CHECK: [[META7]] = !{!"llvm.loop.unroll.runtime.disable"}71; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META6]]}72;.73