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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=loop-vectorize -scalable-vectorization=on -mtriple riscv64-linux-gnu -mattr=+zve32f,+f -S 2>%t | FileCheck %s3 4target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"5target triple = "riscv64"6 7; We can't vectorize with Zvl32b due to RVVBitsPerBlock being 64. Since our8; vscale value is vlen/RVVBitsPerBlock this makes vscale 0.9define void @vector_add_i16(ptr noalias nocapture %a, i16 %v, i64 %n) {10; CHECK-LABEL: @vector_add_i16(11; CHECK-NEXT: entry:12; CHECK-NEXT: br label [[FOR_BODY:%.*]]13; CHECK: for.body:14; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]15; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[IV]]16; CHECK-NEXT: [[ELEM:%.*]] = load i16, ptr [[ARRAYIDX]], align 217; CHECK-NEXT: [[ADD:%.*]] = add i16 [[ELEM]], [[V:%.*]]18; CHECK-NEXT: store i16 [[ADD]], ptr [[ARRAYIDX]], align 219; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 120; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 102421; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY]]22; CHECK: for.end:23; CHECK-NEXT: ret void24;25 26entry:27 br label %for.body28 29for.body:30 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]31 %arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv32 %elem = load i16, ptr %arrayidx33 %add = add i16 %elem, %v34 store i16 %add, ptr %arrayidx35 %iv.next = add nuw nsw i64 %iv, 136 %exitcond.not = icmp eq i64 %iv.next, 102437 br i1 %exitcond.not, label %for.end, label %for.body38 39for.end:40 ret void41}42