324 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=loop-vectorize -S -mtriple=x86_64-- -o - %s | FileCheck %s3 4; Testcase that verify that we don't get a faulty bitcast that cast between5; different sizes.6 7%rec8 = type { i16 }8 9@a = global [1 x %rec8] zeroinitializer10@b = global [2 x ptr] zeroinitializer11 12 13define void @f1() {14; CHECK-LABEL: @f1(15; CHECK-NEXT: bb1:16; CHECK-NEXT: br label [[VECTOR_PH:%.*]]17; CHECK: vector.ph:18; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]19; CHECK: vector.body:20; CHECK-NEXT: [[TMP0:%.*]] = sext i16 0 to i6421; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [2 x ptr], ptr @b, i16 0, i64 [[TMP0]]22; CHECK-NEXT: store <2 x ptr> <ptr @a, ptr @a>, ptr [[TMP1]], align 823; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]]24; CHECK: middle.block:25; CHECK-NEXT: br label [[BB2:%.*]]26; CHECK: bb3:27; CHECK-NEXT: ret void28;29 30bb1:31 br label %bb232 33bb2:34 %c.1.0 = phi i16 [ 0, %bb1 ], [ %_tmp9, %bb2 ]35 %_tmp1 = zext i16 0 to i6436 %_tmp2 = getelementptr [1 x %rec8], ptr @a, i16 0, i64 %_tmp137 %_tmp6 = sext i16 %c.1.0 to i6438 %_tmp7 = getelementptr [2 x ptr], ptr @b, i16 0, i64 %_tmp639 store ptr %_tmp2, ptr %_tmp740 %_tmp9 = add nsw i16 %c.1.0, 141 %_tmp11 = icmp slt i16 %_tmp9, 242 br i1 %_tmp11, label %bb2, label %bb343 44bb3:45 ret void46}47 48; Test case for https://github.com/llvm/llvm-project/issues/131359.49define void @redundant_or_1(ptr %dst, i1 %c.0, i1 %c.1) {50; CHECK-LABEL: @redundant_or_1(51; CHECK-NEXT: entry:52; CHECK-NEXT: br label [[VECTOR_PH:%.*]]53; CHECK: vector.ph:54; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[C_0:%.*]], i64 055; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer56; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i1> poison, i1 [[C_1:%.*]], i64 057; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT1]], <4 x i1> poison, <4 x i32> zeroinitializer58; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i1> [[BROADCAST_SPLAT2]], splat (i1 true)59; CHECK-NEXT: [[TMP0:%.*]] = select <4 x i1> [[TMP1]], <4 x i1> [[BROADCAST_SPLAT]], <4 x i1> zeroinitializer60; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]61; CHECK: vector.body:62; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i1> [[TMP0]], <4 x i1> zeroinitializer63; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i1> [[TMP2]], i32 064; CHECK-NEXT: br i1 [[TMP6]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]65; CHECK: pred.store.if:66; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 067; CHECK-NEXT: store i32 0, ptr [[TMP8]], align 468; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]]69; CHECK: pred.store.continue:70; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP2]], i32 171; CHECK-NEXT: br i1 [[TMP9]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]]72; CHECK: pred.store.if3:73; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 174; CHECK-NEXT: store i32 0, ptr [[TMP11]], align 475; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]]76; CHECK: pred.store.continue4:77; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i1> [[TMP2]], i32 278; CHECK-NEXT: br i1 [[TMP12]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]79; CHECK: pred.store.if5:80; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 281; CHECK-NEXT: store i32 0, ptr [[TMP14]], align 482; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]]83; CHECK: pred.store.continue6:84; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i1> [[TMP2]], i32 385; CHECK-NEXT: br i1 [[TMP15]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]86; CHECK: pred.store.if7:87; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 388; CHECK-NEXT: store i32 0, ptr [[TMP17]], align 489; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]]90; CHECK: pred.store.continue8:91; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]]92; CHECK: middle.block:93; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]94; CHECK: exit:95; CHECK-NEXT: ret void96;97entry:98 br label %loop.header99 100loop.header:101 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]102 br i1 %c.0, label %loop.latch, label %then.1103 104then.1:105 %cmp = icmp eq i32 %iv, 2106 %or = or i1 %cmp, true107 %cond = select i1 %or, i1 %c.1, i1 false108 br i1 %cond, label %then.2, label %loop.latch109 110then.2:111 %gep = getelementptr inbounds i32, ptr %dst, i32 %iv112 store i32 0, ptr %gep, align 4113 br label %loop.latch114 115loop.latch:116 %iv.next = add nuw nsw i32 %iv, 1117 %ec = icmp eq i32 %iv.next, 3118 br i1 %ec, label %exit, label %loop.header119 120exit:121 ret void122}123 124define void @redundant_or_2(ptr %dst, i1 %c.0, i1 %c.1) {125; CHECK-LABEL: @redundant_or_2(126; CHECK-NEXT: entry:127; CHECK-NEXT: br label [[VECTOR_PH:%.*]]128; CHECK: vector.ph:129; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[C_1:%.*]], i64 0130; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer131; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i1> poison, i1 [[C_0:%.*]], i64 0132; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT1]], <4 x i1> poison, <4 x i32> zeroinitializer133; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i1> [[BROADCAST_SPLAT2]], splat (i1 true)134; CHECK-NEXT: [[TMP0:%.*]] = select <4 x i1> [[TMP1]], <4 x i1> [[BROADCAST_SPLAT]], <4 x i1> zeroinitializer135; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]136; CHECK: vector.body:137; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i1> [[TMP0]], <4 x i1> zeroinitializer138; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP3]], i32 0139; CHECK-NEXT: br i1 [[TMP5]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]140; CHECK: pred.store.if:141; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 0142; CHECK-NEXT: store i32 0, ptr [[TMP7]], align 4143; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]]144; CHECK: pred.store.continue:145; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP3]], i32 1146; CHECK-NEXT: br i1 [[TMP8]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]]147; CHECK: pred.store.if3:148; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 1149; CHECK-NEXT: store i32 0, ptr [[TMP10]], align 4150; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]]151; CHECK: pred.store.continue4:152; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP3]], i32 2153; CHECK-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]154; CHECK: pred.store.if5:155; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 2156; CHECK-NEXT: store i32 0, ptr [[TMP13]], align 4157; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]]158; CHECK: pred.store.continue6:159; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i1> [[TMP3]], i32 3160; CHECK-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]161; CHECK: pred.store.if7:162; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 3163; CHECK-NEXT: store i32 0, ptr [[TMP16]], align 4164; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]]165; CHECK: pred.store.continue8:166; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]]167; CHECK: middle.block:168; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]169; CHECK: exit:170; CHECK-NEXT: ret void171;172entry:173 br label %loop.header174 175loop.header:176 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]177 br i1 %c.0, label %loop.latch, label %then.1178 179then.1:180 %cmp = icmp eq i32 %iv, 2181 %or = or i1 true, %cmp182 %cond = select i1 %or, i1 %c.1, i1 false183 br i1 %cond, label %then.2, label %loop.latch184 185then.2:186 %gep = getelementptr inbounds i32, ptr %dst, i32 %iv187 store i32 0, ptr %gep, align 4188 br label %loop.latch189 190loop.latch:191 %iv.next = add nuw nsw i32 %iv, 1192 %ec = icmp eq i32 %iv.next, 3193 br i1 %ec, label %exit, label %loop.header194 195exit:196 ret void197}198 199define void @redundant_and_1(ptr %dst, i1 %c.0, i1 %c.1) {200; CHECK-LABEL: @redundant_and_1(201; CHECK-NEXT: entry:202; CHECK-NEXT: br label [[VECTOR_PH:%.*]]203; CHECK: vector.ph:204; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[C_0:%.*]], i64 0205; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer206; CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i1> [[BROADCAST_SPLAT]], splat (i1 true)207; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i1> poison, i1 [[C_1:%.*]], i64 0208; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT1]], <4 x i1> poison, <4 x i32> zeroinitializer209; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]210; CHECK: vector.body:211; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> <i1 false, i1 false, i1 true, i1 false>, <4 x i1> [[BROADCAST_SPLAT2]], <4 x i1> zeroinitializer212; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP0]], <4 x i1> [[TMP5]], <4 x i1> zeroinitializer213; CHECK-NEXT: [[TMP6:%.*]] = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i1> [[TMP2]], <4 x i1> zeroinitializer214; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i1> [[TMP6]], i32 0215; CHECK-NEXT: br i1 [[TMP7]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]216; CHECK: pred.store.if:217; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 0218; CHECK-NEXT: store i32 0, ptr [[TMP9]], align 4219; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]]220; CHECK: pred.store.continue:221; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP6]], i32 1222; CHECK-NEXT: br i1 [[TMP10]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]]223; CHECK: pred.store.if3:224; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 1225; CHECK-NEXT: store i32 0, ptr [[TMP12]], align 4226; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]]227; CHECK: pred.store.continue4:228; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i1> [[TMP6]], i32 2229; CHECK-NEXT: br i1 [[TMP13]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]230; CHECK: pred.store.if5:231; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 2232; CHECK-NEXT: store i32 0, ptr [[TMP15]], align 4233; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]]234; CHECK: pred.store.continue6:235; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i1> [[TMP6]], i32 3236; CHECK-NEXT: br i1 [[TMP16]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]237; CHECK: pred.store.if7:238; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 3239; CHECK-NEXT: store i32 0, ptr [[TMP18]], align 4240; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]]241; CHECK: pred.store.continue8:242; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]]243; CHECK: middle.block:244; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]245; CHECK: exit:246; CHECK-NEXT: ret void247;248entry:249 br label %loop.header250 251loop.header:252 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]253 br i1 %c.0, label %loop.latch, label %then.1254 255then.1:256 %cmp = icmp eq i32 %iv, 2257 %or = or i1 %cmp, false258 %cond = select i1 %or, i1 %c.1, i1 false259 br i1 %cond, label %then.2, label %loop.latch260 261then.2:262 %gep = getelementptr inbounds i32, ptr %dst, i32 %iv263 store i32 0, ptr %gep, align 4264 br label %loop.latch265 266loop.latch:267 %iv.next = add nuw nsw i32 %iv, 1268 %ec = icmp eq i32 %iv.next, 3269 br i1 %ec, label %exit, label %loop.header270 271exit:272 ret void273}274 275define void @redundant_and_2(ptr %dst, i1 %c.0, i1 %c.1) {276; CHECK-LABEL: @redundant_and_2(277; CHECK-NEXT: entry:278; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]279; CHECK: loop.header:280; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]281; CHECK-NEXT: br i1 [[C_0:%.*]], label [[LOOP_LATCH]], label [[THEN_1:%.*]]282; CHECK: then.1:283; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[IV]], 2284; CHECK-NEXT: [[OR:%.*]] = and i1 false, [[CMP]]285; CHECK-NEXT: [[COND:%.*]] = select i1 [[OR]], i1 [[C_1:%.*]], i1 false286; CHECK-NEXT: br i1 [[COND]], label [[THEN_2:%.*]], label [[LOOP_LATCH]]287; CHECK: then.2:288; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 [[IV]]289; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4290; CHECK-NEXT: br label [[LOOP_LATCH]]291; CHECK: loop.latch:292; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1293; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], 3294; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP_HEADER]]295; CHECK: exit:296; CHECK-NEXT: ret void297;298entry:299 br label %loop.header300 301loop.header:302 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]303 br i1 %c.0, label %loop.latch, label %then.1304 305then.1:306 %cmp = icmp eq i32 %iv, 2307 %or = and i1 false, %cmp308 %cond = select i1 %or, i1 %c.1, i1 false309 br i1 %cond, label %then.2, label %loop.latch310 311then.2:312 %gep = getelementptr inbounds i32, ptr %dst, i32 %iv313 store i32 0, ptr %gep, align 4314 br label %loop.latch315 316loop.latch:317 %iv.next = add nuw nsw i32 %iv, 1318 %ec = icmp eq i32 %iv.next, 3319 br i1 %ec, label %exit, label %loop.header320 321exit:322 ret void323}324