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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=loop-vectorize -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -S | FileCheck %s3 4target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"5target triple = "x86_64-apple-macosx10.8.0"6 7@c = common global [2048 x i32] zeroinitializer, align 168@b = common global [2048 x i32] zeroinitializer, align 169@d = common global [2048 x i32] zeroinitializer, align 1610@a = common global [2048 x i32] zeroinitializer, align 1611 12; The program below gathers and scatters data. We better not vectorize it.13define void @cost_model_1() nounwind uwtable noinline ssp {14; CHECK-LABEL: @cost_model_1(15; CHECK-NEXT: entry:16; CHECK-NEXT: br label [[FOR_BODY:%.*]]17; CHECK: for.body:18; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]19; CHECK-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDVARS_IV]], 120; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2048 x i32], ptr @c, i64 0, i64 [[TMP0]]21; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 822; CHECK-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP1]] to i6423; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 [[IDXPROM1]]24; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX2]], align 425; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2048 x i32], ptr @d, i64 0, i64 [[INDVARS_IV]]26; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX4]], align 427; CHECK-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i6428; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[IDXPROM5]]29; CHECK-NEXT: store i32 [[TMP2]], ptr [[ARRAYIDX6]], align 430; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 131; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i3232; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LFTR_WIDEIV]], 25633; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]]34; CHECK: for.end:35; CHECK-NEXT: ret void36;37entry:38 br label %for.body39 40for.body: ; preds = %for.body, %entry41 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]42 %0 = shl nsw i64 %indvars.iv, 143 %arrayidx = getelementptr inbounds [2048 x i32], ptr @c, i64 0, i64 %044 %1 = load i32, ptr %arrayidx, align 845 %idxprom1 = sext i32 %1 to i6446 %arrayidx2 = getelementptr inbounds [2048 x i32], ptr @b, i64 0, i64 %idxprom147 %2 = load i32, ptr %arrayidx2, align 448 %arrayidx4 = getelementptr inbounds [2048 x i32], ptr @d, i64 0, i64 %indvars.iv49 %3 = load i32, ptr %arrayidx4, align 450 %idxprom5 = sext i32 %3 to i6451 %arrayidx6 = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 %idxprom552 store i32 %2, ptr %arrayidx6, align 453 %indvars.iv.next = add i64 %indvars.iv, 154 %lftr.wideiv = trunc i64 %indvars.iv.next to i3255 %exitcond = icmp eq i32 %lftr.wideiv, 25656 br i1 %exitcond, label %for.end, label %for.body57 58for.end: ; preds = %for.body59 ret void60}61 62; This function uses a stride that is generally too big to benefit from vectorization without63; really good support for a gather load. But if we don't vectorize the pointer induction,64; then we don't need to extract the pointers out of vector of pointers,65; and the vectorization becomes profitable.66 67define float @PR27826(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %n) {68; CHECK-LABEL: @PR27826(69; CHECK-NEXT: entry:70; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[N:%.*]], 071; CHECK-NEXT: br i1 [[CMP]], label [[ITER_CHECK:%.*]], label [[FOR_END:%.*]]72; CHECK: iter.check:73; CHECK-NEXT: [[T0:%.*]] = sext i32 [[N]] to i6474; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[T0]], -175; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 576; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 177; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 478; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]79; CHECK: vector.main.loop.iter.check:80; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP2]], 1681; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]82; CHECK: vector.ph:83; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 1684; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]]85; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]86; CHECK: vector.body:87; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]88; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP119:%.*]], [[VECTOR_BODY]] ]89; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x float> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP120:%.*]], [[VECTOR_BODY]] ]90; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x float> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP121:%.*]], [[VECTOR_BODY]] ]91; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x float> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP122:%.*]], [[VECTOR_BODY]] ]92; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 3293; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 094; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 3295; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 6496; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 9697; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 12898; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 16099; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 192100; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 224101; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 256102; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 288103; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 320104; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 352105; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 384106; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[OFFSET_IDX]], 416107; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[OFFSET_IDX]], 448108; CHECK-NEXT: [[TMP18:%.*]] = add i64 [[OFFSET_IDX]], 480109; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[TMP3]]110; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP4]]111; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP5]]112; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP6]]113; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP7]]114; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP8]]115; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP9]]116; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP10]]117; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP11]]118; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP12]]119; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP13]]120; CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP14]]121; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP15]]122; CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP16]]123; CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP17]]124; CHECK-NEXT: [[TMP34:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP18]]125; CHECK-NEXT: [[TMP35:%.*]] = load float, ptr [[TMP19]], align 4126; CHECK-NEXT: [[TMP36:%.*]] = load float, ptr [[TMP20]], align 4127; CHECK-NEXT: [[TMP37:%.*]] = load float, ptr [[TMP21]], align 4128; CHECK-NEXT: [[TMP38:%.*]] = load float, ptr [[TMP22]], align 4129; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x float> poison, float [[TMP35]], i32 0130; CHECK-NEXT: [[TMP40:%.*]] = insertelement <4 x float> [[TMP39]], float [[TMP36]], i32 1131; CHECK-NEXT: [[TMP41:%.*]] = insertelement <4 x float> [[TMP40]], float [[TMP37]], i32 2132; CHECK-NEXT: [[TMP42:%.*]] = insertelement <4 x float> [[TMP41]], float [[TMP38]], i32 3133; CHECK-NEXT: [[TMP43:%.*]] = load float, ptr [[TMP23]], align 4134; CHECK-NEXT: [[TMP44:%.*]] = load float, ptr [[TMP24]], align 4135; CHECK-NEXT: [[TMP45:%.*]] = load float, ptr [[TMP25]], align 4136; CHECK-NEXT: [[TMP46:%.*]] = load float, ptr [[TMP26]], align 4137; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x float> poison, float [[TMP43]], i32 0138; CHECK-NEXT: [[TMP48:%.*]] = insertelement <4 x float> [[TMP47]], float [[TMP44]], i32 1139; CHECK-NEXT: [[TMP49:%.*]] = insertelement <4 x float> [[TMP48]], float [[TMP45]], i32 2140; CHECK-NEXT: [[TMP50:%.*]] = insertelement <4 x float> [[TMP49]], float [[TMP46]], i32 3141; CHECK-NEXT: [[TMP51:%.*]] = load float, ptr [[TMP27]], align 4142; CHECK-NEXT: [[TMP52:%.*]] = load float, ptr [[TMP28]], align 4143; CHECK-NEXT: [[TMP53:%.*]] = load float, ptr [[TMP29]], align 4144; CHECK-NEXT: [[TMP54:%.*]] = load float, ptr [[TMP30]], align 4145; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x float> poison, float [[TMP51]], i32 0146; CHECK-NEXT: [[TMP56:%.*]] = insertelement <4 x float> [[TMP55]], float [[TMP52]], i32 1147; CHECK-NEXT: [[TMP57:%.*]] = insertelement <4 x float> [[TMP56]], float [[TMP53]], i32 2148; CHECK-NEXT: [[TMP58:%.*]] = insertelement <4 x float> [[TMP57]], float [[TMP54]], i32 3149; CHECK-NEXT: [[TMP59:%.*]] = load float, ptr [[TMP31]], align 4150; CHECK-NEXT: [[TMP60:%.*]] = load float, ptr [[TMP32]], align 4151; CHECK-NEXT: [[TMP61:%.*]] = load float, ptr [[TMP33]], align 4152; CHECK-NEXT: [[TMP62:%.*]] = load float, ptr [[TMP34]], align 4153; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x float> poison, float [[TMP59]], i32 0154; CHECK-NEXT: [[TMP64:%.*]] = insertelement <4 x float> [[TMP63]], float [[TMP60]], i32 1155; CHECK-NEXT: [[TMP65:%.*]] = insertelement <4 x float> [[TMP64]], float [[TMP61]], i32 2156; CHECK-NEXT: [[TMP66:%.*]] = insertelement <4 x float> [[TMP65]], float [[TMP62]], i32 3157; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds float, ptr [[B:%.*]], i64 [[TMP3]]158; CHECK-NEXT: [[TMP68:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP4]]159; CHECK-NEXT: [[TMP69:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP5]]160; CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP6]]161; CHECK-NEXT: [[TMP71:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP7]]162; CHECK-NEXT: [[TMP72:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP8]]163; CHECK-NEXT: [[TMP73:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP9]]164; CHECK-NEXT: [[TMP74:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP10]]165; CHECK-NEXT: [[TMP75:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP11]]166; CHECK-NEXT: [[TMP76:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP12]]167; CHECK-NEXT: [[TMP77:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP13]]168; CHECK-NEXT: [[TMP78:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP14]]169; CHECK-NEXT: [[TMP79:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP15]]170; CHECK-NEXT: [[TMP80:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP16]]171; CHECK-NEXT: [[TMP81:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP17]]172; CHECK-NEXT: [[TMP82:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP18]]173; CHECK-NEXT: [[TMP83:%.*]] = load float, ptr [[TMP67]], align 4174; CHECK-NEXT: [[TMP84:%.*]] = load float, ptr [[TMP68]], align 4175; CHECK-NEXT: [[TMP85:%.*]] = load float, ptr [[TMP69]], align 4176; CHECK-NEXT: [[TMP86:%.*]] = load float, ptr [[TMP70]], align 4177; CHECK-NEXT: [[TMP87:%.*]] = insertelement <4 x float> poison, float [[TMP83]], i32 0178; CHECK-NEXT: [[TMP88:%.*]] = insertelement <4 x float> [[TMP87]], float [[TMP84]], i32 1179; CHECK-NEXT: [[TMP89:%.*]] = insertelement <4 x float> [[TMP88]], float [[TMP85]], i32 2180; CHECK-NEXT: [[TMP90:%.*]] = insertelement <4 x float> [[TMP89]], float [[TMP86]], i32 3181; CHECK-NEXT: [[TMP91:%.*]] = load float, ptr [[TMP71]], align 4182; CHECK-NEXT: [[TMP92:%.*]] = load float, ptr [[TMP72]], align 4183; CHECK-NEXT: [[TMP93:%.*]] = load float, ptr [[TMP73]], align 4184; CHECK-NEXT: [[TMP94:%.*]] = load float, ptr [[TMP74]], align 4185; CHECK-NEXT: [[TMP95:%.*]] = insertelement <4 x float> poison, float [[TMP91]], i32 0186; CHECK-NEXT: [[TMP96:%.*]] = insertelement <4 x float> [[TMP95]], float [[TMP92]], i32 1187; CHECK-NEXT: [[TMP97:%.*]] = insertelement <4 x float> [[TMP96]], float [[TMP93]], i32 2188; CHECK-NEXT: [[TMP98:%.*]] = insertelement <4 x float> [[TMP97]], float [[TMP94]], i32 3189; CHECK-NEXT: [[TMP99:%.*]] = load float, ptr [[TMP75]], align 4190; CHECK-NEXT: [[TMP100:%.*]] = load float, ptr [[TMP76]], align 4191; CHECK-NEXT: [[TMP101:%.*]] = load float, ptr [[TMP77]], align 4192; CHECK-NEXT: [[TMP102:%.*]] = load float, ptr [[TMP78]], align 4193; CHECK-NEXT: [[TMP103:%.*]] = insertelement <4 x float> poison, float [[TMP99]], i32 0194; CHECK-NEXT: [[TMP104:%.*]] = insertelement <4 x float> [[TMP103]], float [[TMP100]], i32 1195; CHECK-NEXT: [[TMP105:%.*]] = insertelement <4 x float> [[TMP104]], float [[TMP101]], i32 2196; CHECK-NEXT: [[TMP106:%.*]] = insertelement <4 x float> [[TMP105]], float [[TMP102]], i32 3197; CHECK-NEXT: [[TMP107:%.*]] = load float, ptr [[TMP79]], align 4198; CHECK-NEXT: [[TMP108:%.*]] = load float, ptr [[TMP80]], align 4199; CHECK-NEXT: [[TMP109:%.*]] = load float, ptr [[TMP81]], align 4200; CHECK-NEXT: [[TMP110:%.*]] = load float, ptr [[TMP82]], align 4201; CHECK-NEXT: [[TMP111:%.*]] = insertelement <4 x float> poison, float [[TMP107]], i32 0202; CHECK-NEXT: [[TMP112:%.*]] = insertelement <4 x float> [[TMP111]], float [[TMP108]], i32 1203; CHECK-NEXT: [[TMP113:%.*]] = insertelement <4 x float> [[TMP112]], float [[TMP109]], i32 2204; CHECK-NEXT: [[TMP114:%.*]] = insertelement <4 x float> [[TMP113]], float [[TMP110]], i32 3205; CHECK-NEXT: [[TMP115:%.*]] = fadd fast <4 x float> [[TMP42]], [[VEC_PHI]]206; CHECK-NEXT: [[TMP116:%.*]] = fadd fast <4 x float> [[TMP50]], [[VEC_PHI2]]207; CHECK-NEXT: [[TMP117:%.*]] = fadd fast <4 x float> [[TMP58]], [[VEC_PHI3]]208; CHECK-NEXT: [[TMP118:%.*]] = fadd fast <4 x float> [[TMP66]], [[VEC_PHI4]]209; CHECK-NEXT: [[TMP119]] = fadd fast <4 x float> [[TMP115]], [[TMP90]]210; CHECK-NEXT: [[TMP120]] = fadd fast <4 x float> [[TMP116]], [[TMP98]]211; CHECK-NEXT: [[TMP121]] = fadd fast <4 x float> [[TMP117]], [[TMP106]]212; CHECK-NEXT: [[TMP122]] = fadd fast <4 x float> [[TMP118]], [[TMP114]]213; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16214; CHECK-NEXT: [[TMP123:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]215; CHECK-NEXT: br i1 [[TMP123]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]216; CHECK: middle.block:217; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd fast <4 x float> [[TMP120]], [[TMP119]]218; CHECK-NEXT: [[BIN_RDX5:%.*]] = fadd fast <4 x float> [[TMP121]], [[BIN_RDX]]219; CHECK-NEXT: [[BIN_RDX6:%.*]] = fadd fast <4 x float> [[TMP122]], [[BIN_RDX5]]220; CHECK-NEXT: [[TMP124:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[BIN_RDX6]])221; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]]222; CHECK-NEXT: br i1 [[CMP_N]], label [[LOOPEXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]223; CHECK: vec.epilog.iter.check:224; CHECK-NEXT: [[IND_END9:%.*]] = mul i64 [[N_VEC]], 32225; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 4226; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]227; CHECK: vec.epilog.ph:228; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]229; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP124]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0.000000e+00, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]230; CHECK-NEXT: [[N_MOD_VF7:%.*]] = urem i64 [[TMP2]], 4231; CHECK-NEXT: [[N_VEC8:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF7]]232; CHECK-NEXT: [[IND_END:%.*]] = mul i64 [[N_VEC8]], 32233; CHECK-NEXT: [[TMP125:%.*]] = insertelement <4 x float> zeroinitializer, float [[BC_MERGE_RDX]], i32 0234; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]235; CHECK: vec.epilog.vector.body:236; CHECK-NEXT: [[INDEX10:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT13:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]237; CHECK-NEXT: [[VEC_PHI11:%.*]] = phi <4 x float> [ [[TMP125]], [[VEC_EPILOG_PH]] ], [ [[TMP155:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]238; CHECK-NEXT: [[OFFSET_IDX12:%.*]] = mul i64 [[INDEX10]], 32239; CHECK-NEXT: [[TMP126:%.*]] = add i64 [[OFFSET_IDX12]], 0240; CHECK-NEXT: [[TMP127:%.*]] = add i64 [[OFFSET_IDX12]], 32241; CHECK-NEXT: [[TMP128:%.*]] = add i64 [[OFFSET_IDX12]], 64242; CHECK-NEXT: [[TMP129:%.*]] = add i64 [[OFFSET_IDX12]], 96243; CHECK-NEXT: [[TMP130:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP126]]244; CHECK-NEXT: [[TMP131:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP127]]245; CHECK-NEXT: [[TMP132:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP128]]246; CHECK-NEXT: [[TMP133:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP129]]247; CHECK-NEXT: [[TMP134:%.*]] = load float, ptr [[TMP130]], align 4248; CHECK-NEXT: [[TMP135:%.*]] = load float, ptr [[TMP131]], align 4249; CHECK-NEXT: [[TMP136:%.*]] = load float, ptr [[TMP132]], align 4250; CHECK-NEXT: [[TMP137:%.*]] = load float, ptr [[TMP133]], align 4251; CHECK-NEXT: [[TMP138:%.*]] = insertelement <4 x float> poison, float [[TMP134]], i32 0252; CHECK-NEXT: [[TMP139:%.*]] = insertelement <4 x float> [[TMP138]], float [[TMP135]], i32 1253; CHECK-NEXT: [[TMP140:%.*]] = insertelement <4 x float> [[TMP139]], float [[TMP136]], i32 2254; CHECK-NEXT: [[TMP141:%.*]] = insertelement <4 x float> [[TMP140]], float [[TMP137]], i32 3255; CHECK-NEXT: [[TMP142:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP126]]256; CHECK-NEXT: [[TMP143:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP127]]257; CHECK-NEXT: [[TMP144:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP128]]258; CHECK-NEXT: [[TMP145:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP129]]259; CHECK-NEXT: [[TMP146:%.*]] = load float, ptr [[TMP142]], align 4260; CHECK-NEXT: [[TMP147:%.*]] = load float, ptr [[TMP143]], align 4261; CHECK-NEXT: [[TMP148:%.*]] = load float, ptr [[TMP144]], align 4262; CHECK-NEXT: [[TMP149:%.*]] = load float, ptr [[TMP145]], align 4263; CHECK-NEXT: [[TMP150:%.*]] = insertelement <4 x float> poison, float [[TMP146]], i32 0264; CHECK-NEXT: [[TMP151:%.*]] = insertelement <4 x float> [[TMP150]], float [[TMP147]], i32 1265; CHECK-NEXT: [[TMP152:%.*]] = insertelement <4 x float> [[TMP151]], float [[TMP148]], i32 2266; CHECK-NEXT: [[TMP153:%.*]] = insertelement <4 x float> [[TMP152]], float [[TMP149]], i32 3267; CHECK-NEXT: [[TMP154:%.*]] = fadd fast <4 x float> [[TMP141]], [[VEC_PHI11]]268; CHECK-NEXT: [[TMP155]] = fadd fast <4 x float> [[TMP154]], [[TMP153]]269; CHECK-NEXT: [[INDEX_NEXT13]] = add nuw i64 [[INDEX10]], 4270; CHECK-NEXT: [[TMP156:%.*]] = icmp eq i64 [[INDEX_NEXT13]], [[N_VEC8]]271; CHECK-NEXT: br i1 [[TMP156]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]272; CHECK: vec.epilog.middle.block:273; CHECK-NEXT: [[TMP157:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[TMP155]])274; CHECK-NEXT: [[CMP_N14:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC8]]275; CHECK-NEXT: br i1 [[CMP_N14]], label [[LOOPEXIT]], label [[VEC_EPILOG_SCALAR_PH]]276; CHECK: vec.epilog.scalar.ph:277; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END9]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK]] ]278; CHECK-NEXT: [[BC_MERGE_RDX15:%.*]] = phi float [ [[TMP157]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP124]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0.000000e+00, [[ITER_CHECK]] ]279; CHECK-NEXT: br label [[FOR:%.*]]280; CHECK: for:281; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR]] ]282; CHECK-NEXT: [[S_02:%.*]] = phi float [ [[BC_MERGE_RDX15]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[ADD4:%.*]], [[FOR]] ]283; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDVARS_IV]]284; CHECK-NEXT: [[T1:%.*]] = load float, ptr [[ARRAYIDX]], align 4285; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDVARS_IV]]286; CHECK-NEXT: [[T2:%.*]] = load float, ptr [[ARRAYIDX3]], align 4287; CHECK-NEXT: [[ADD:%.*]] = fadd fast float [[T1]], [[S_02]]288; CHECK-NEXT: [[ADD4]] = fadd fast float [[ADD]], [[T2]]289; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 32290; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT]], [[T0]]291; CHECK-NEXT: br i1 [[CMP1]], label [[FOR]], label [[LOOPEXIT]], !llvm.loop [[LOOP5:![0-9]+]]292; CHECK: loopexit:293; CHECK-NEXT: [[ADD4_LCSSA:%.*]] = phi float [ [[ADD4]], [[FOR]] ], [ [[TMP124]], [[MIDDLE_BLOCK]] ], [ [[TMP157]], [[VEC_EPILOG_MIDDLE_BLOCK]] ]294; CHECK-NEXT: br label [[FOR_END]]295; CHECK: for.end:296; CHECK-NEXT: [[S_0_LCSSA:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[ADD4_LCSSA]], [[LOOPEXIT]] ]297; CHECK-NEXT: ret float [[S_0_LCSSA]]298;299entry:300 %cmp = icmp sgt i32 %n, 0301 br i1 %cmp, label %preheader, label %for.end302 303preheader:304 %t0 = sext i32 %n to i64305 br label %for306 307for:308 %indvars.iv = phi i64 [ 0, %preheader ], [ %indvars.iv.next, %for ]309 %s.02 = phi float [ 0.0, %preheader ], [ %add4, %for ]310 %arrayidx = getelementptr inbounds float, ptr %a, i64 %indvars.iv311 %t1 = load float, ptr %arrayidx, align 4312 %arrayidx3 = getelementptr inbounds float, ptr %b, i64 %indvars.iv313 %t2 = load float, ptr %arrayidx3, align 4314 %add = fadd fast float %t1, %s.02315 %add4 = fadd fast float %add, %t2316 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 32317 %cmp1 = icmp slt i64 %indvars.iv.next, %t0318 br i1 %cmp1, label %for, label %loopexit319 320loopexit:321 %add4.lcssa = phi float [ %add4, %for ]322 br label %for.end323 324for.end:325 %s.0.lcssa = phi float [ 0.0, %entry ], [ %add4.lcssa, %loopexit ]326 ret float %s.0.lcssa327}328 329define void @multi_exit(ptr %dst, ptr %src.1, ptr %src.2, i64 %A, i64 %B) #0 {330; CHECK-LABEL: @multi_exit(331; CHECK-NEXT: entry:332; CHECK-NEXT: [[UMAX9:%.*]] = call i64 @llvm.umax.i64(i64 [[B:%.*]], i64 1)333; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[UMAX9]], -1334; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[TMP0]]335; CHECK-NEXT: [[UMIN10:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 [[A:%.*]])336; CHECK-NEXT: [[TMP2:%.*]] = add nuw i64 [[UMIN10]], 1337; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP2]], 24338; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]339; CHECK: vector.scevcheck:340; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[B]], i64 1)341; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[UMAX]], -1342; CHECK-NEXT: [[TMP4:%.*]] = freeze i64 [[TMP3]]343; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[A]])344; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[UMIN]] to i32345; CHECK-NEXT: [[TMP6:%.*]] = add i32 1, [[TMP5]]346; CHECK-NEXT: [[TMP7:%.*]] = icmp ult i32 [[TMP6]], 1347; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i64 [[UMIN]], 4294967295348; CHECK-NEXT: [[TMP9:%.*]] = or i1 [[TMP7]], [[TMP8]]349; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[UMIN]] to i32350; CHECK-NEXT: [[TMP11:%.*]] = icmp slt i32 [[TMP10]], 0351; CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i64 [[UMIN]], 4294967295352; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]]353; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP9]], [[TMP13]]354; CHECK-NEXT: br i1 [[TMP14]], label [[SCALAR_PH]], label [[VECTOR_MEMCHECK:%.*]]355; CHECK: vector.memcheck:356; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST:%.*]], i64 1357; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[SRC_2:%.*]], i64 8358; CHECK-NEXT: [[UMAX3:%.*]] = call i64 @llvm.umax.i64(i64 [[B]], i64 1)359; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[UMAX3]], -1360; CHECK-NEXT: [[TMP16:%.*]] = freeze i64 [[TMP15]]361; CHECK-NEXT: [[UMIN4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP16]], i64 [[A]])362; CHECK-NEXT: [[TMP17:%.*]] = shl i64 [[UMIN4]], 3363; CHECK-NEXT: [[TMP18:%.*]] = add i64 [[TMP17]], 8364; CHECK-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[SRC_3:%.*]], i64 [[TMP18]]365; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP2]]366; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SRC_2]], [[SCEVGEP]]367; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]368; CHECK-NEXT: [[BOUND06:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP5]]369; CHECK-NEXT: [[BOUND17:%.*]] = icmp ult ptr [[SRC_3]], [[SCEVGEP]]370; CHECK-NEXT: [[FOUND_CONFLICT8:%.*]] = and i1 [[BOUND06]], [[BOUND17]]371; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT8]]372; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]373; CHECK: vector.ph:374; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 4375; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i64 [[N_MOD_VF]], 0376; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i64 4, i64 [[N_MOD_VF]]377; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[TMP20]]378; CHECK-NEXT: [[TMP21:%.*]] = load i64, ptr [[SRC_2]], align 8, !alias.scope [[META6:![0-9]+]]379; CHECK-NEXT: [[TMP22:%.*]] = trunc i64 [[N_VEC]] to i32380; CHECK-NEXT: [[TMP31:%.*]] = icmp ne i64 [[TMP21]], 0381; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i1> poison, i1 [[TMP31]], i64 0382; CHECK-NEXT: [[TMP23:%.*]] = shufflevector <2 x i1> [[BROADCAST_SPLATINSERT]], <2 x i1> poison, <2 x i32> zeroinitializer383; CHECK-NEXT: br label [[LOOP:%.*]]384; CHECK: vector.body:385; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[LOOP]] ]386; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i64 [[INDEX]] to i32387; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i64, ptr [[SRC_3]], i32 [[OFFSET_IDX]]388; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i64, ptr [[TMP24]], i64 2389; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP25]], align 8, !alias.scope [[META9:![0-9]+]]390; CHECK-NEXT: [[TMP26:%.*]] = icmp eq <2 x i64> [[WIDE_LOAD]], zeroinitializer391; CHECK-NEXT: [[TMP27:%.*]] = and <2 x i1> [[TMP23]], [[TMP26]]392; CHECK-NEXT: [[TMP28:%.*]] = zext <2 x i1> [[TMP27]] to <2 x i8>393; CHECK-NEXT: [[TMP29:%.*]] = extractelement <2 x i8> [[TMP28]], i32 1394; CHECK-NEXT: store i8 [[TMP29]], ptr [[DST]], align 1, !alias.scope [[META11:![0-9]+]], !noalias [[META13:![0-9]+]]395; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4396; CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]397; CHECK-NEXT: br i1 [[TMP30]], label [[MIDDLE_BLOCK:%.*]], label [[LOOP]], !llvm.loop [[LOOP14:![0-9]+]]398; CHECK: middle.block:399; CHECK-NEXT: br label [[SCALAR_PH]]400; CHECK: scalar.ph:401; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[VECTOR_MEMCHECK]] ]402; CHECK-NEXT: [[BC_RESUME_VAL11:%.*]] = phi i32 [ [[TMP22]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[VECTOR_MEMCHECK]] ]403; CHECK-NEXT: br label [[LOOP1:%.*]]404; CHECK: loop:405; CHECK-NEXT: [[IV_1_WIDE:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT_WIDE:%.*]], [[LOOP_LATCH:%.*]] ]406; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ [[BC_RESUME_VAL11]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP_LATCH]] ]407; CHECK-NEXT: [[EC_1:%.*]] = icmp ult i64 [[IV_1_WIDE]], [[A]]408; CHECK-NEXT: br i1 [[EC_1]], label [[LOOP_LATCH]], label [[EXIT:%.*]]409; CHECK: loop.latch:410; CHECK-NEXT: [[SRC_1:%.*]] = getelementptr inbounds i64, ptr [[SRC_3]], i32 [[IV_1]]411; CHECK-NEXT: [[L_1:%.*]] = load i64, ptr [[SRC_1]], align 8412; CHECK-NEXT: [[L_2:%.*]] = load i64, ptr [[SRC_2]], align 8413; CHECK-NEXT: [[CMP55_US:%.*]] = icmp eq i64 [[L_1]], 0414; CHECK-NEXT: [[CMP_I_US:%.*]] = icmp ne i64 [[L_2]], 0415; CHECK-NEXT: [[AND:%.*]] = and i1 [[CMP_I_US]], [[CMP55_US]]416; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[AND]] to i8417; CHECK-NEXT: store i8 [[EXT]], ptr [[DST]], align 1418; CHECK-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1419; CHECK-NEXT: [[IV_1_NEXT_WIDE]] = zext i32 [[IV_1_NEXT]] to i64420; CHECK-NEXT: [[EC_2:%.*]] = icmp ult i64 [[IV_1_NEXT_WIDE]], [[B]]421; CHECK-NEXT: br i1 [[EC_2]], label [[LOOP1]], label [[EXIT]], !llvm.loop [[LOOP15:![0-9]+]]422; CHECK: exit:423; CHECK-NEXT: ret void424;425entry:426 br label %loop427 428loop:429 %iv.1.wide = phi i64 [ 0, %entry ], [ %iv.1.next.wide, %loop.latch ]430 %iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop.latch ]431 %ec.1 = icmp ult i64 %iv.1.wide, %A432 br i1 %ec.1, label %loop.latch, label %exit433 434loop.latch:435 %gep.src.1 = getelementptr inbounds i64, ptr %src.1, i32 %iv.1436 %l.1 = load i64, ptr %gep.src.1, align 8437 %l.2 = load i64, ptr %src.2, align 8438 %cmp55.us = icmp eq i64 %l.1, 0439 %cmp.i.us = icmp ne i64 %l.2, 0440 %and = and i1 %cmp.i.us, %cmp55.us441 %ext = zext i1 %and to i8442 store i8 %ext, ptr %dst, align 1443 %iv.1.next = add i32 %iv.1, 1444 %iv.1.next.wide = zext i32 %iv.1.next to i64445 %ec.2 = icmp ult i64 %iv.1.next.wide, %B446 br i1 %ec.2, label %loop, label %exit447 448exit:449 ret void450}451 452define i1 @any_of_cost(ptr %start, ptr %end) #0 {453; CHECK-LABEL: @any_of_cost(454; CHECK-NEXT: entry:455; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START:%.*]] to i64456; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END:%.*]] to i64457; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[END1]], [[START2]]458; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[TMP0]], 40459; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1460; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP2]], 4461; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]462; CHECK: vector.ph:463; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 4464; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[N_MOD_VF]], 0465; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i64 4, i64 [[N_MOD_VF]]466; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[TMP4]]467; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[N_VEC]], 40468; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]469; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]470; CHECK: vector.body:471; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]472; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i1> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP26:%.*]], [[VECTOR_BODY]] ]473; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <2 x i1> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP27:%.*]], [[VECTOR_BODY]] ]474; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 40475; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 0476; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 40477; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 80478; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 120479; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP6]]480; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP7]]481; CHECK-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP8]]482; CHECK-NEXT: [[NEXT_GEP6:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP9]]483; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 8484; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[NEXT_GEP4]], i64 8485; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[NEXT_GEP5]], i64 8486; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[NEXT_GEP6]], i64 8487; CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP10]], align 8488; CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP11]], align 8489; CHECK-NEXT: [[TMP16:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP14]], i32 0490; CHECK-NEXT: [[TMP17:%.*]] = insertelement <2 x ptr> [[TMP16]], ptr [[TMP15]], i32 1491; CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP12]], align 8492; CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP13]], align 8493; CHECK-NEXT: [[TMP20:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP18]], i32 0494; CHECK-NEXT: [[TMP21:%.*]] = insertelement <2 x ptr> [[TMP20]], ptr [[TMP19]], i32 1495; CHECK-NEXT: [[TMP24:%.*]] = icmp ne <2 x ptr> [[TMP17]], zeroinitializer496; CHECK-NEXT: [[TMP25:%.*]] = icmp ne <2 x ptr> [[TMP21]], zeroinitializer497; CHECK-NEXT: [[TMP26]] = or <2 x i1> [[VEC_PHI]], [[TMP24]]498; CHECK-NEXT: [[TMP27]] = or <2 x i1> [[VEC_PHI3]], [[TMP25]]499; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4500; CHECK-NEXT: [[TMP28:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]501; CHECK-NEXT: br i1 [[TMP28]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]502; CHECK: middle.block:503; CHECK-NEXT: [[BIN_RDX:%.*]] = or <2 x i1> [[TMP27]], [[TMP26]]504; CHECK-NEXT: [[TMP29:%.*]] = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> [[BIN_RDX]])505; CHECK-NEXT: [[TMP30:%.*]] = freeze i1 [[TMP29]]506; CHECK-NEXT: [[RDX_SELECT:%.*]] = select i1 [[TMP30]], i1 false, i1 false507; CHECK-NEXT: br label [[SCALAR_PH]]508; CHECK: scalar.ph:509; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i1 [ [[RDX_SELECT]], [[MIDDLE_BLOCK]] ], [ false, [[ENTRY:%.*]] ]510; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[START]], [[ENTRY]] ]511; CHECK-NEXT: br label [[LOOP:%.*]]512; CHECK: loop:513; CHECK-NEXT: [[ANY_OF:%.*]] = phi i1 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ANY_OF_NEXT:%.*]], [[LOOP]] ]514; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], [[LOOP]] ]515; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[PTR_IV]], i64 8516; CHECK-NEXT: [[L:%.*]] = load ptr, ptr [[GEP]], align 8517; CHECK-NEXT: [[CMP13_NOT_NOT:%.*]] = icmp eq ptr [[L]], null518; CHECK-NEXT: [[ANY_OF_NEXT]] = select i1 [[CMP13_NOT_NOT]], i1 [[ANY_OF]], i1 false519; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i8, ptr [[PTR_IV]], i64 40520; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq ptr [[PTR_IV]], [[END]]521; CHECK-NEXT: br i1 [[CMP_NOT]], label [[EXIT:%.*]], label [[LOOP]], !llvm.loop [[LOOP17:![0-9]+]]522; CHECK: exit:523; CHECK-NEXT: [[ANY_OF_NEXT_LCSSA:%.*]] = phi i1 [ [[ANY_OF_NEXT]], [[LOOP]] ]524; CHECK-NEXT: ret i1 [[ANY_OF_NEXT_LCSSA]]525;526entry:527 br label %loop528 529loop:530 %any.of = phi i1 [ false, %entry ], [ %any.of.next, %loop ]531 %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop ]532 %gep = getelementptr i8, ptr %ptr.iv, i64 8533 %l = load ptr, ptr %gep, align 8534 %cmp13.not.not = icmp eq ptr %l, null535 %any.of.next = select i1 %cmp13.not.not, i1 %any.of, i1 false536 %ptr.iv.next = getelementptr inbounds i8, ptr %ptr.iv, i64 40537 %cmp.not = icmp eq ptr %ptr.iv, %end538 br i1 %cmp.not, label %exit, label %loop539 540exit:541 ret i1 %any.of.next542}543 544define i64 @cost_assume(ptr %end, i64 %N) {545; CHECK-LABEL: @cost_assume(546; CHECK-NEXT: entry:547; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END:%.*]] to i64548; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -9549; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[TMP0]], 9550; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1551; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 8552; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]553; CHECK: vector.ph:554; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 8555; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]]556; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i64 [[N:%.*]], 0557; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP11]])558; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP11]])559; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]560; CHECK: vector.body:561; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]562; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP7:%.*]], [[VECTOR_BODY]] ]563; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP8:%.*]], [[VECTOR_BODY]] ]564; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ]565; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP10:%.*]], [[VECTOR_BODY]] ]566; CHECK-NEXT: [[TMP7]] = add <2 x i64> [[VEC_PHI]], splat (i64 1)567; CHECK-NEXT: [[TMP8]] = add <2 x i64> [[VEC_PHI2]], splat (i64 1)568; CHECK-NEXT: [[TMP9]] = add <2 x i64> [[VEC_PHI3]], splat (i64 1)569; CHECK-NEXT: [[TMP10]] = add <2 x i64> [[VEC_PHI4]], splat (i64 1)570; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8571; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]572; CHECK-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]573; CHECK: middle.block:574; CHECK-NEXT: [[BIN_RDX:%.*]] = add <2 x i64> [[TMP8]], [[TMP7]]575; CHECK-NEXT: [[BIN_RDX5:%.*]] = add <2 x i64> [[TMP9]], [[BIN_RDX]]576; CHECK-NEXT: [[BIN_RDX6:%.*]] = add <2 x i64> [[TMP10]], [[BIN_RDX5]]577; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[BIN_RDX6]])578; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]]579; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]580; CHECK: scalar.ph:581; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]582; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP14]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]583; CHECK-NEXT: br label [[LOOP:%.*]]584; CHECK: loop:585; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]586; CHECK-NEXT: [[TMP15:%.*]] = phi i64 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[TMP12:%.*]], [[LOOP]] ]587; CHECK-NEXT: [[TMP12]] = add i64 [[TMP15]], 1588; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1589; CHECK-NEXT: [[C:%.*]] = icmp ne i64 [[N]], 0590; CHECK-NEXT: tail call void @llvm.assume(i1 [[C]])591; CHECK-NEXT: [[GEP:%.*]] = getelementptr nusw [9 x i8], ptr null, i64 [[IV_NEXT]]592; CHECK-NEXT: [[EC:%.*]] = icmp eq ptr [[GEP]], [[END]]593; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP19:![0-9]+]]594; CHECK: exit:595; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP12]], [[LOOP]] ], [ [[TMP14]], [[MIDDLE_BLOCK]] ]596; CHECK-NEXT: ret i64 [[DOTLCSSA]]597;598entry:599 br label %loop600 601loop:602 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]603 %0 = phi i64 [ 0, %entry ], [ %1, %loop ]604 %1 = add i64 %0, 1605 %iv.next = add nsw i64 %iv, 1606 %c = icmp ne i64 %N, 0607 tail call void @llvm.assume(i1 %c)608 %gep = getelementptr nusw [ 9 x i8 ], ptr null, i64 %iv.next609 %ec = icmp eq ptr %gep, %end610 br i1 %ec, label %exit, label %loop611 612exit:613 ret i64 %1614}615 616; Test case for https://github.com/llvm/llvm-project/issues/96294 with a stored617; reduction which overwrites an earlier store.618define void @reduction_store(ptr noalias %src, ptr %dst, i1 %x) #2 {619; CHECK-LABEL: @reduction_store(620; CHECK-NEXT: entry:621; CHECK-NEXT: br label [[VECTOR_PH:%.*]]622; CHECK: vector.ph:623; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[X:%.*]], i64 0624; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer625; CHECK-NEXT: [[TMP0:%.*]] = zext <4 x i1> [[BROADCAST_SPLAT]] to <4 x i64>626; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i64> [[TMP0]], splat (i64 12)627; CHECK-NEXT: [[TMP2:%.*]] = trunc <4 x i64> [[TMP1]] to <4 x i32>628; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]629; CHECK: vector.body:630; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]631; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ <i32 0, i32 -1, i32 -1, i32 -1>, [[VECTOR_PH]] ], [ [[TMP11:%.*]], [[VECTOR_BODY]] ]632; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ splat (i32 -1), [[VECTOR_PH]] ], [ [[TMP12:%.*]], [[VECTOR_BODY]] ]633; CHECK-NEXT: [[TMP11]] = and <4 x i32> [[VEC_PHI]], [[TMP2]]634; CHECK-NEXT: [[TMP12]] = and <4 x i32> [[VEC_PHI1]], [[TMP2]]635; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8636; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[INDEX_NEXT]], 24637; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]638; CHECK: middle.block:639; CHECK-NEXT: [[BIN_RDX:%.*]] = and <4 x i32> [[TMP12]], [[TMP11]]640; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[BIN_RDX]])641; CHECK-NEXT: store i32 [[TMP10]], ptr [[DST:%.*]], align 4642; CHECK-NEXT: br label [[SCALAR_PH:%.*]]643; CHECK: scalar.ph:644; CHECK-NEXT: br label [[LOOP:%.*]]645; CHECK: loop:646; CHECK-NEXT: [[RED:%.*]] = phi i32 [ [[TMP10]], [[SCALAR_PH]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ]647; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 24, [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]648; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC:%.*]], i32 [[IV]]649; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4650; CHECK-NEXT: [[L_AND:%.*]] = and i32 [[L]], 3651; CHECK-NEXT: store i32 [[L_AND]], ptr [[DST]], align 4652; CHECK-NEXT: [[X_EXT:%.*]] = zext i1 [[X]] to i64653; CHECK-NEXT: [[LSHR:%.*]] = lshr i64 [[X_EXT]], 12654; CHECK-NEXT: [[T:%.*]] = trunc i64 [[LSHR]] to i32655; CHECK-NEXT: [[RED_NEXT]] = and i32 [[RED]], [[T]]656; CHECK-NEXT: store i32 [[RED_NEXT]], ptr [[DST]], align 4657; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1658; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV]], 29659; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP]], !llvm.loop [[LOOP21:![0-9]+]]660; CHECK: exit:661; CHECK-NEXT: ret void662;663entry:664 br label %loop665 666loop:667 %red = phi i32 [ 0, %entry ], [ %red.next, %loop ]668 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]669 %gep.src = getelementptr inbounds i32, ptr %src, i32 %iv670 %l = load i32, ptr %gep.src671 %l.and = and i32 %l, 3672 store i32 %l.and, ptr %dst, align 4673 %x.ext = zext i1 %x to i64674 %lshr = lshr i64 %x.ext, 12675 %t = trunc i64 %lshr to i32676 %red.next = and i32 %red, %t677 store i32 %red.next, ptr %dst, align 4678 %iv.next = add i32 %iv, 1679 %ec = icmp eq i32 %iv, 29680 br i1 %ec, label %exit, label %loop681 682exit:683 ret void684}685 686; Test case for https://github.com/llvm/llvm-project/issues/105722.687define i64 @live_in_known_1_via_scev() {688; CHECK-LABEL: @live_in_known_1_via_scev(689; CHECK-NEXT: entry:690; CHECK-NEXT: [[SEL:%.*]] = select i1 false, i32 3, i32 0691; CHECK-NEXT: br label [[PH:%.*]]692; CHECK: ph:693; CHECK-NEXT: [[P:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ]694; CHECK-NEXT: [[N:%.*]] = add nuw nsw i32 [[SEL]], 6695; CHECK-NEXT: [[P_EXT:%.*]] = zext nneg i32 [[P]] to i64696; CHECK-NEXT: br label [[VECTOR_PH:%.*]]697; CHECK: vector.ph:698; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]699; CHECK: vector.body:700; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]701; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ <i64 3, i64 1, i64 1, i64 1>, [[VECTOR_PH]] ], [ [[VEC_PHI]], [[VECTOR_BODY]] ]702; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4703; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[INDEX_NEXT]], 8704; CHECK-NEXT: br i1 [[TMP0]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]]705; CHECK: middle.block:706; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vector.reduce.mul.v4i64(<4 x i64> [[VEC_PHI]])707; CHECK-NEXT: br label [[LOOP:%.*]]708; CHECK: exit:709; CHECK-NEXT: ret i64 [[TMP3]]710;711entry:712 %sel = select i1 false, i32 3, i32 0713 br label %ph714 715ph:716 %p = phi i32 [ 1, %entry ]717 %N = add nuw nsw i32 %sel, 6718 %p.ext = zext nneg i32 %p to i64719 br label %loop720 721loop:722 %iv = phi i32 [ 0, %ph ], [ %iv.next, %loop ]723 %red = phi i64 [ 3, %ph ], [ %red.mul, %loop ]724 %red.mul = mul nsw i64 %red, %p.ext725 %iv.next = add nuw nsw i32 %iv, 1726 %ec = icmp eq i32 %iv.next, %N727 br i1 %ec, label %exit, label %loop728 729exit:730 %res = phi i64 [ %red.mul, %loop ]731 ret i64 %res732}733 734; Test case for https://github.com/llvm/llvm-project/issues/107501.735define i64 @cost_loop_invariant_recipes(i1 %x, i64 %y) {736; CHECK-LABEL: @cost_loop_invariant_recipes(737; CHECK-NEXT: entry:738; CHECK-NEXT: br label [[VECTOR_PH:%.*]]739; CHECK: vector.ph:740; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <2 x i64> poison, i64 [[Y:%.*]], i64 0741; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT1]], <2 x i64> poison, <2 x i32> zeroinitializer742; CHECK-NEXT: [[X:%.*]] = xor i1 [[X1:%.*]], true743; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i1> poison, i1 [[X]], i64 0744; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i1> [[BROADCAST_SPLATINSERT]], <2 x i1> poison, <2 x i32> zeroinitializer745; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i1> [[BROADCAST_SPLAT]] to <2 x i64>746; CHECK-NEXT: [[TMP2:%.*]] = shl <2 x i64> [[BROADCAST_SPLAT2]], [[TMP1]]747; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]748; CHECK: vector.body:749; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ splat (i64 1), [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ]750; CHECK-NEXT: [[TMP3]] = mul <2 x i64> [[TMP2]], [[VEC_PHI]]751; CHECK-NEXT: br i1 true, label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]]752; CHECK: middle.block:753; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> [[TMP3]])754; CHECK-NEXT: br label [[LOOP:%.*]]755; CHECK: exit:756; CHECK-NEXT: ret i64 [[TMP4]]757;758entry:759 br label %loop760 761loop:762 %iv = phi i64 [ 0, %entry ], [ %iv.next.i.i.i, %loop ]763 %red = phi i64 [ 1, %entry ], [ %red.mul, %loop ]764 %not.x = xor i1 %x, true765 %ext = zext i1 %not.x to i64766 %shl = shl i64 %y, %ext767 %red.mul = mul i64 %shl, %red768 %iv.next.i.i.i = add i64 %iv, 1769 %ec = icmp eq i64 %iv, 1770 br i1 %ec, label %exit, label %loop771 772exit:773 ret i64 %red.mul774}775 776; Test case for https://github.com/llvm/llvm-project/issues/113526.777define i32 @narrowed_reduction(ptr %a, i1 %cmp) #0 {778; CHECK-LABEL: @narrowed_reduction(779; CHECK-NEXT: entry:780; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP:%.*]] to i32781; CHECK-NEXT: br label [[VECTOR_PH1:%.*]]782; CHECK: vector.ph:783; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[CONV]], i64 0784; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i32> [[BROADCAST_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer785; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]786; CHECK: vector.body:787; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <16 x i32> [ zeroinitializer, [[VECTOR_PH1]] ], [ [[TMP7:%.*]], [[VECTOR_BODY]] ]788; CHECK-NEXT: [[TMP1:%.*]] = and <16 x i32> [[VEC_PHI1]], splat (i32 1)789; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i32> [[TMP1]], [[BROADCAST_SPLAT]]790; CHECK-NEXT: [[TMP5:%.*]] = trunc <16 x i32> [[TMP3]] to <16 x i1>791; CHECK-NEXT: [[TMP7]] = zext <16 x i1> [[TMP5]] to <16 x i32>792; CHECK-NEXT: br i1 true, label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP24:![0-9]+]]793; CHECK: middle.block:794; CHECK-NEXT: [[TMP20:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP5]])795; CHECK-NEXT: [[TMP21:%.*]] = zext i1 [[TMP20]] to i32796; CHECK-NEXT: br label [[LOOP1:%.*]]797; CHECK: exit:798; CHECK-NEXT: ret i32 [[TMP21]]799;800entry:801 %conv = zext i1 %cmp to i32802 br label %loop803 804loop:805 %iv = phi i32 [ 1, %entry ], [ %inc, %loop ]806 %or13 = phi i32 [ 0, %entry ], [ %or, %loop ]807 %and = and i32 %or13, 1808 %or = or i32 %and, %conv809 %inc = add i32 %iv, 1810 %ec = icmp eq i32 %iv, 16811 br i1 %ec, label %exit, label %loop812 813exit:814 ret i32 %or815}816 817; Check if the vplan-based cost model select same VF to the legacy cost model.818; Reduced from: https://github.com/llvm/llvm-project/issues/115744#issuecomment-2670479463819define i32 @g(i64 %n) {820; CHECK-LABEL: @g(821; CHECK-NEXT: iter.check:822; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[N:%.*]] to i32823; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 1824; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 4825; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]826; CHECK: vector.scevcheck:827; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt i64 [[N]], 4294967295828; CHECK-NEXT: br i1 [[TMP2]], label [[VEC_EPILOG_SCALAR_PH]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]829; CHECK: vector.main.loop.iter.check:830; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i32 [[TMP1]], 16831; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]832; CHECK: vector.ph:833; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 16834; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]]835; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[N]], i64 0836; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer837; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]838; CHECK: vector.body:839; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]840; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]841; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP15:%.*]], [[VECTOR_BODY]] ]842; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP16:%.*]], [[VECTOR_BODY]] ]843; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP17:%.*]], [[VECTOR_BODY]] ]844; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP18:%.*]], [[VECTOR_BODY]] ]845; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4)846; CHECK-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i32> [[STEP_ADD]], splat (i32 4)847; CHECK-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i32> [[STEP_ADD_2]], splat (i32 4)848; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i32> [[VEC_IND]] to <4 x i64>849; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i32> [[STEP_ADD]] to <4 x i64>850; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i32> [[STEP_ADD_2]] to <4 x i64>851; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i32> [[STEP_ADD_3]] to <4 x i64>852; CHECK-NEXT: [[TMP7:%.*]] = icmp eq <4 x i64> [[BROADCAST_SPLAT]], [[TMP3]]853; CHECK-NEXT: [[TMP8:%.*]] = icmp eq <4 x i64> [[BROADCAST_SPLAT]], [[TMP4]]854; CHECK-NEXT: [[TMP9:%.*]] = icmp eq <4 x i64> [[BROADCAST_SPLAT]], [[TMP5]]855; CHECK-NEXT: [[TMP10:%.*]] = icmp eq <4 x i64> [[BROADCAST_SPLAT]], [[TMP6]]856; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[TMP7]], <4 x i32> zeroinitializer, <4 x i32> splat (i32 2)857; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[TMP8]], <4 x i32> zeroinitializer, <4 x i32> splat (i32 2)858; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP9]], <4 x i32> zeroinitializer, <4 x i32> splat (i32 2)859; CHECK-NEXT: [[TMP14:%.*]] = select <4 x i1> [[TMP10]], <4 x i32> zeroinitializer, <4 x i32> splat (i32 2)860; CHECK-NEXT: [[TMP15]] = or <4 x i32> [[TMP11]], [[VEC_PHI]]861; CHECK-NEXT: [[TMP16]] = or <4 x i32> [[TMP12]], [[VEC_PHI2]]862; CHECK-NEXT: [[TMP17]] = or <4 x i32> [[TMP13]], [[VEC_PHI3]]863; CHECK-NEXT: [[TMP18]] = or <4 x i32> [[TMP14]], [[VEC_PHI4]]864; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16865; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD_3]], splat (i32 4)866; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]867; CHECK-NEXT: br i1 [[TMP19]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP25:![0-9]+]]868; CHECK: middle.block:869; CHECK-NEXT: [[BIN_RDX:%.*]] = or <4 x i32> [[TMP16]], [[TMP15]]870; CHECK-NEXT: [[BIN_RDX5:%.*]] = or <4 x i32> [[TMP17]], [[BIN_RDX]]871; CHECK-NEXT: [[BIN_RDX6:%.*]] = or <4 x i32> [[TMP18]], [[BIN_RDX5]]872; CHECK-NEXT: [[TMP20:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[BIN_RDX6]])873; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]]874; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]875; CHECK: vec.epilog.iter.check:876; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i32 [[N_MOD_VF]], 4877; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF3]]878; CHECK: vec.epilog.ph:879; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]880; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP20]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]881; CHECK-NEXT: [[N_MOD_VF7:%.*]] = urem i32 [[TMP1]], 4882; CHECK-NEXT: [[N_VEC8:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF7]]883; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i32> zeroinitializer, i32 [[BC_MERGE_RDX]], i32 0884; CHECK-NEXT: [[BROADCAST_SPLATINSERT9:%.*]] = insertelement <4 x i64> poison, i64 [[N]], i64 0885; CHECK-NEXT: [[BROADCAST_SPLAT14:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT9]], <4 x i64> poison, <4 x i32> zeroinitializer886; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[BC_RESUME_VAL]], i64 0887; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer888; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[DOTSPLAT]], <i32 0, i32 1, i32 2, i32 3>889; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]890; CHECK: vec.epilog.vector.body:891; CHECK-NEXT: [[INDEX9:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT15:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]892; CHECK-NEXT: [[VEC_IND10:%.*]] = phi <4 x i32> [ [[INDUCTION]], [[VEC_EPILOG_PH]] ], [ [[VEC_IND_NEXT11:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]893; CHECK-NEXT: [[VEC_PHI12:%.*]] = phi <4 x i32> [ [[TMP21]], [[VEC_EPILOG_PH]] ], [ [[TMP25:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]894; CHECK-NEXT: [[TMP22:%.*]] = zext <4 x i32> [[VEC_IND10]] to <4 x i64>895; CHECK-NEXT: [[TMP23:%.*]] = icmp eq <4 x i64> [[BROADCAST_SPLAT14]], [[TMP22]]896; CHECK-NEXT: [[TMP24:%.*]] = select <4 x i1> [[TMP23]], <4 x i32> zeroinitializer, <4 x i32> splat (i32 2)897; CHECK-NEXT: [[TMP25]] = or <4 x i32> [[TMP24]], [[VEC_PHI12]]898; CHECK-NEXT: [[INDEX_NEXT15]] = add nuw i32 [[INDEX9]], 4899; CHECK-NEXT: [[VEC_IND_NEXT11]] = add <4 x i32> [[VEC_IND10]], splat (i32 4)900; CHECK-NEXT: [[TMP26:%.*]] = icmp eq i32 [[INDEX_NEXT15]], [[N_VEC8]]901; CHECK-NEXT: br i1 [[TMP26]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP26:![0-9]+]]902; CHECK: vec.epilog.middle.block:903; CHECK-NEXT: [[TMP27:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP25]])904; CHECK-NEXT: [[CMP_N16:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC8]]905; CHECK-NEXT: br i1 [[CMP_N16]], label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]]906; CHECK: vec.epilog.scalar.ph:907; CHECK-NEXT: [[BC_RESUME_VAL17:%.*]] = phi i32 [ [[N_VEC8]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ITER_CHECK:%.*]] ]908; CHECK-NEXT: [[BC_MERGE_RDX18:%.*]] = phi i32 [ [[TMP27]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP20]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ITER_CHECK]] ]909; CHECK-NEXT: br label [[LOOP:%.*]]910; CHECK: loop:911; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL17]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]912; CHECK-NEXT: [[SELECT:%.*]] = phi i32 [ [[BC_MERGE_RDX18]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[SELECT_NEXT:%.*]], [[LOOP]] ]913; CHECK-NEXT: [[IV_WIDEN:%.*]] = zext i32 [[IV]] to i64914; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[N]], [[IV_WIDEN]]915; CHECK-NEXT: [[SELECT_I:%.*]] = select i1 [[EXITCOND]], i32 0, i32 2916; CHECK-NEXT: [[SELECT_NEXT]] = or i32 [[SELECT_I]], [[SELECT]]917; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1918; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP27:![0-9]+]]919; CHECK: exit:920; CHECK-NEXT: [[SELECT_NEXT_LCSSA:%.*]] = phi i32 [ [[SELECT_NEXT]], [[LOOP]] ], [ [[TMP20]], [[MIDDLE_BLOCK]] ], [ [[TMP27]], [[VEC_EPILOG_MIDDLE_BLOCK]] ]921; CHECK-NEXT: ret i32 [[SELECT_NEXT_LCSSA]]922;923entry:924 br label %loop925 926loop:927 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]928 %select = phi i32 [ 0, %entry ], [ %select.next, %loop ]929 %iv.widen = zext i32 %iv to i64930 %exitcond = icmp eq i64 %n, %iv.widen931 %select.i = select i1 %exitcond, i32 0, i32 2932 %select.next = or i32 %select.i, %select933 %iv.next = add i32 %iv, 1934 br i1 %exitcond, label %exit, label %loop935 936exit:937 ret i32 %select.next938}939 940declare void @llvm.assume(i1 noundef) #0941 942attributes #0 = { "target-cpu"="penryn" }943attributes #1 = { "target-features"="+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl" }944attributes #2 = { "target-cpu"="znver3" }945