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1; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize,vplan -disable-output 2>&1 < %s | FileCheck %s2; REQUIRES: asserts3 4target triple = "x86_64"5 6; Test that shows how many registers the loop vectorizer thinks an illegal <VF x i1> will consume.7 8; CHECK-LABEL: LV: Checking a loop in 'or_reduction_avx' from <stdin>9; CHECK: LV(REG): VF = 6410; CHECK-NEXT: LV(REG): Found max usage: 2 item11; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers12; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 136 registers13 14define i1 @or_reduction_avx(i32 %arg, ptr %ptr) "target-features"="+avx" {15entry:16  br label %loop17exit:18  ret i1 %reduction_next19loop:20  %induction = phi i32 [ 0, %entry ], [ %induction_next, %loop ]21  %reduction = phi i1 [ 0, %entry ], [ %reduction_next, %loop ]22  %gep = getelementptr inbounds i32, ptr %ptr, i32 %induction23  %loaded = load i32, ptr %gep24  %i1 = icmp eq i32 %loaded, %induction25  %reduction_next = or i1 %i1, %reduction26  %induction_next = add nuw i32 %induction, 127  %cond = icmp eq i32 %induction_next, %arg28  br i1 %cond, label %exit, label %loop, !llvm.loop !6429}30 31!64 = distinct !{!64, !65}32!65 = !{!"llvm.loop.vectorize.width", i32 64}33