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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -force-vector-width=4 -S %s | FileCheck %s3 4target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"5target triple = "x86_64-unknown-linux-gnu"6 7; Test for https://github.com/llvm/llvm-project/issues/111606.8define ptr @test_interleave_ptradd_with_replicated_op(ptr %m) #0 {9; CHECK-LABEL: define ptr @test_interleave_ptradd_with_replicated_op(10; CHECK-SAME: ptr [[M:%.*]]) #[[ATTR0:[0-9]+]] {11; CHECK-NEXT: [[ENTRY:.*:]]12; CHECK-NEXT: br label %[[VECTOR_PH:.*]]13; CHECK: [[VECTOR_PH]]:14; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[M]], i64 76815; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]16; CHECK: [[VECTOR_BODY]]:17; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]18; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 819; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 020; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 821; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 1622; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 2423; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 3224; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 4025; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 4826; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 5627; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 6428; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 7229; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 8030; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 8831; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 9632; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 10433; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 11234; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 12035; CHECK-NEXT: [[NEXT_GEP12:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP0]]36; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP1]]37; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP2]]38; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP3]]39; CHECK-NEXT: [[NEXT_GEP13:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP4]]40; CHECK-NEXT: [[NEXT_GEP6:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP5]]41; CHECK-NEXT: [[NEXT_GEP7:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP6]]42; CHECK-NEXT: [[NEXT_GEP8:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP7]]43; CHECK-NEXT: [[NEXT_GEP14:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP8]]44; CHECK-NEXT: [[NEXT_GEP10:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP9]]45; CHECK-NEXT: [[NEXT_GEP11:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP10]]46; CHECK-NEXT: [[NEXT_GEP17:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP11]]47; CHECK-NEXT: [[NEXT_GEP15:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP12]]48; CHECK-NEXT: [[NEXT_GEP18:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP13]]49; CHECK-NEXT: [[NEXT_GEP19:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP14]]50; CHECK-NEXT: [[NEXT_GEP16:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP15]]51; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[NEXT_GEP12]], i64 452; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[NEXT_GEP13]], i64 453; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[NEXT_GEP14]], i64 454; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[NEXT_GEP15]], i64 455; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP27]], i32 -456; CHECK-NEXT: [[TMP33:%.*]] = getelementptr i8, ptr [[TMP28]], i32 -457; CHECK-NEXT: [[TMP34:%.*]] = getelementptr i8, ptr [[TMP29]], i32 -458; CHECK-NEXT: [[TMP35:%.*]] = getelementptr i8, ptr [[TMP30]], i32 -459; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <8 x i32>, ptr [[TMP32]], align 460; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>61; CHECK-NEXT: [[STRIDED_VEC17:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>62; CHECK-NEXT: [[WIDE_VEC18:%.*]] = load <8 x i32>, ptr [[TMP33]], align 463; CHECK-NEXT: [[STRIDED_VEC19:%.*]] = shufflevector <8 x i32> [[WIDE_VEC18]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>64; CHECK-NEXT: [[STRIDED_VEC20:%.*]] = shufflevector <8 x i32> [[WIDE_VEC18]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>65; CHECK-NEXT: [[WIDE_VEC21:%.*]] = load <8 x i32>, ptr [[TMP34]], align 466; CHECK-NEXT: [[STRIDED_VEC22:%.*]] = shufflevector <8 x i32> [[WIDE_VEC21]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>67; CHECK-NEXT: [[STRIDED_VEC23:%.*]] = shufflevector <8 x i32> [[WIDE_VEC21]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>68; CHECK-NEXT: [[WIDE_VEC24:%.*]] = load <8 x i32>, ptr [[TMP35]], align 469; CHECK-NEXT: [[STRIDED_VEC25:%.*]] = shufflevector <8 x i32> [[WIDE_VEC24]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>70; CHECK-NEXT: [[STRIDED_VEC26:%.*]] = shufflevector <8 x i32> [[WIDE_VEC24]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>71; CHECK-NEXT: [[TMP36:%.*]] = add <4 x i32> [[STRIDED_VEC17]], [[STRIDED_VEC]]72; CHECK-NEXT: [[TMP40:%.*]] = extractelement <4 x i32> [[TMP36]], i32 073; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x i32> [[TMP36]], i32 174; CHECK-NEXT: [[TMP42:%.*]] = extractelement <4 x i32> [[TMP36]], i32 275; CHECK-NEXT: [[TMP43:%.*]] = extractelement <4 x i32> [[TMP36]], i32 376; CHECK-NEXT: [[TMP37:%.*]] = add <4 x i32> [[STRIDED_VEC20]], [[STRIDED_VEC19]]77; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i32> [[TMP37]], i32 078; CHECK-NEXT: [[TMP45:%.*]] = extractelement <4 x i32> [[TMP37]], i32 179; CHECK-NEXT: [[TMP46:%.*]] = extractelement <4 x i32> [[TMP37]], i32 280; CHECK-NEXT: [[TMP47:%.*]] = extractelement <4 x i32> [[TMP37]], i32 381; CHECK-NEXT: [[TMP38:%.*]] = add <4 x i32> [[STRIDED_VEC23]], [[STRIDED_VEC22]]82; CHECK-NEXT: [[TMP48:%.*]] = extractelement <4 x i32> [[TMP38]], i32 083; CHECK-NEXT: [[TMP49:%.*]] = extractelement <4 x i32> [[TMP38]], i32 184; CHECK-NEXT: [[TMP50:%.*]] = extractelement <4 x i32> [[TMP38]], i32 285; CHECK-NEXT: [[TMP51:%.*]] = extractelement <4 x i32> [[TMP38]], i32 386; CHECK-NEXT: [[TMP39:%.*]] = add <4 x i32> [[STRIDED_VEC26]], [[STRIDED_VEC25]]87; CHECK-NEXT: [[TMP52:%.*]] = extractelement <4 x i32> [[TMP39]], i32 088; CHECK-NEXT: [[TMP53:%.*]] = extractelement <4 x i32> [[TMP39]], i32 189; CHECK-NEXT: [[TMP54:%.*]] = extractelement <4 x i32> [[TMP39]], i32 290; CHECK-NEXT: [[TMP55:%.*]] = extractelement <4 x i32> [[TMP39]], i32 391; CHECK-NEXT: store i32 [[TMP40]], ptr [[NEXT_GEP12]], align 492; CHECK-NEXT: store i32 [[TMP41]], ptr [[NEXT_GEP2]], align 493; CHECK-NEXT: store i32 [[TMP42]], ptr [[NEXT_GEP3]], align 494; CHECK-NEXT: store i32 [[TMP43]], ptr [[NEXT_GEP4]], align 495; CHECK-NEXT: store i32 [[TMP44]], ptr [[NEXT_GEP13]], align 496; CHECK-NEXT: store i32 [[TMP45]], ptr [[NEXT_GEP6]], align 497; CHECK-NEXT: store i32 [[TMP46]], ptr [[NEXT_GEP7]], align 498; CHECK-NEXT: store i32 [[TMP47]], ptr [[NEXT_GEP8]], align 499; CHECK-NEXT: store i32 [[TMP48]], ptr [[NEXT_GEP14]], align 4100; CHECK-NEXT: store i32 [[TMP49]], ptr [[NEXT_GEP10]], align 4101; CHECK-NEXT: store i32 [[TMP50]], ptr [[NEXT_GEP11]], align 4102; CHECK-NEXT: store i32 [[TMP51]], ptr [[NEXT_GEP17]], align 4103; CHECK-NEXT: store i32 [[TMP52]], ptr [[NEXT_GEP15]], align 4104; CHECK-NEXT: store i32 [[TMP53]], ptr [[NEXT_GEP18]], align 4105; CHECK-NEXT: store i32 [[TMP54]], ptr [[NEXT_GEP19]], align 4106; CHECK-NEXT: store i32 [[TMP55]], ptr [[NEXT_GEP16]], align 4107; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16108; CHECK-NEXT: [[TMP56:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96109; CHECK-NEXT: br i1 [[TMP56]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]110; CHECK: [[MIDDLE_BLOCK]]:111; CHECK-NEXT: br label %[[SCALAR_PH:.*]]112; CHECK: [[SCALAR_PH]]:113; CHECK-NEXT: br label %[[LOOP:.*]]114; CHECK: [[LOOP]]:115; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[IND_END]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ]116; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 97, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]117; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 8118; CHECK-NEXT: [[P_4:%.*]] = getelementptr i8, ptr [[PTR_IV]], i64 4119; CHECK-NEXT: [[L_1:%.*]] = load i32, ptr [[P_4]], align 4120; CHECK-NEXT: [[P_0:%.*]] = getelementptr i8, ptr [[PTR_IV]], i64 0121; CHECK-NEXT: [[L_2:%.*]] = load i32, ptr [[P_0]], align 4122; CHECK-NEXT: [[ADD:%.*]] = add i32 [[L_1]], [[L_2]]123; CHECK-NEXT: store i32 [[ADD]], ptr [[PTR_IV]], align 4124; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1125; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[IV]], 100126; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]127; CHECK: [[EXIT]]:128; CHECK-NEXT: [[P_4_LCSSA:%.*]] = phi ptr [ [[P_4]], %[[LOOP]] ]129; CHECK-NEXT: ret ptr [[P_4_LCSSA]]130;131entry:132 br label %loop133 134loop: ; preds = %loop, %entry135 %ptr.iv = phi ptr [ %m, %entry ], [ %ptr.iv.next, %loop ]136 %iv = phi i32 [ 1, %entry ], [ %iv.next, %loop ]137 %ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 8138 %p.4 = getelementptr i8, ptr %ptr.iv, i64 4139 %l.1 = load i32, ptr %p.4, align 4140 %p.0 = getelementptr i8, ptr %ptr.iv, i64 0141 %l.2 = load i32, ptr %p.0, align 4142 %add = add i32 %l.1, %l.2143 store i32 %add, ptr %ptr.iv, align 4144 %iv.next = add i32 %iv, 1145 %tobool.not = icmp eq i32 %iv, 100146 br i1 %tobool.not, label %exit, label %loop147 148exit: ; preds = %loop149 ret ptr %p.4150}151 152attributes #0 = { "target-cpu"="znver2" }153;.154; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}155; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}156; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}157; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}158;.159