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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s3 4target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"5target triple = "x86_64-apple-macos"6 7; Both %l3 and the earlier store to %gep.iv.2 access the same location. %l18; cannot be added safely to the same interleave group as %l2 and %l3, because9; that would mean %l2 and %l3 would need to be hoisted across the store.10define void @pr63602_1(ptr %arr) {11; CHECK-LABEL: define void @pr63602_112; CHECK-SAME: (ptr [[ARR:%.*]]) {13; CHECK-NEXT: entry:14; CHECK-NEXT: br label [[VECTOR_PH:%.*]]15; CHECK: vector.ph:16; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]17; CHECK: vector.body:18; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]19; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[INDEX]], 320; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[TMP0]]21; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[INDEX]], 322; CHECK-NEXT: [[OFFSET_IDX1:%.*]] = add i64 4, [[TMP1]]23; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX1]], 024; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX1]], 325; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX1]], 626; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX1]], 927; CHECK-NEXT: [[TMP6:%.*]] = add nuw nsw i64 [[OFFSET_IDX]], 428; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP6]]29; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <12 x i32>, ptr [[TMP7]], align 430; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <12 x i32> [[WIDE_VEC]], <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>31; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[STRIDED_VEC]], i32 032; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[STRIDED_VEC]], i32 133; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i32> [[STRIDED_VEC]], i32 234; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i32> [[STRIDED_VEC]], i32 335; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP2]]36; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP3]]37; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP4]]38; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP5]]39; CHECK-NEXT: store i32 [[TMP8]], ptr [[TMP12]], align 440; CHECK-NEXT: store i32 [[TMP9]], ptr [[TMP13]], align 441; CHECK-NEXT: store i32 [[TMP10]], ptr [[TMP14]], align 442; CHECK-NEXT: store i32 [[TMP11]], ptr [[TMP15]], align 443; CHECK-NEXT: [[TMP16:%.*]] = add nuw nsw i64 [[OFFSET_IDX]], 244; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP16]]45; CHECK-NEXT: [[WIDE_VEC2:%.*]] = load <12 x i32>, ptr [[TMP17]], align 446; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <12 x i32> [[WIDE_VEC2]], <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>47; CHECK-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <12 x i32> [[WIDE_VEC2]], <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>48; CHECK-NEXT: [[TMP18:%.*]] = add <4 x i32> [[STRIDED_VEC4]], [[STRIDED_VEC3]]49; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i32> [[TMP18]], i32 050; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i32> [[TMP18]], i32 151; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i32> [[TMP18]], i32 252; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x i32> [[TMP18]], i32 353; CHECK-NEXT: store i32 [[TMP19]], ptr [[TMP12]], align 454; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP13]], align 455; CHECK-NEXT: store i32 [[TMP21]], ptr [[TMP14]], align 456; CHECK-NEXT: store i32 [[TMP22]], ptr [[TMP15]], align 457; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 458; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1659; CHECK-NEXT: br i1 [[TMP23]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]60; CHECK: middle.block:61; CHECK-NEXT: br label [[SCALAR_PH:%.*]]62; CHECK: scalar.ph:63; CHECK-NEXT: br label [[LOOP:%.*]]64; CHECK: loop:65; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ 49, [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ]66; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ 52, [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ]67; CHECK-NEXT: [[IV_1_NEXT]] = add nuw nsw i64 [[IV_1]], 368; CHECK-NEXT: [[IV_1_PLUS_4:%.*]] = add nuw nsw i64 [[IV_1]], 469; CHECK-NEXT: [[GEP_IV_1_PLUS_4:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[IV_1_PLUS_4]]70; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_IV_1_PLUS_4]], align 471; CHECK-NEXT: [[GEP_IV_2:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[IV_2]]72; CHECK-NEXT: store i32 [[L1]], ptr [[GEP_IV_2]], align 473; CHECK-NEXT: [[IV_1_PLUS_2:%.*]] = add nuw nsw i64 [[IV_1]], 274; CHECK-NEXT: [[GEP_IV_1_PLUS_2:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[IV_1_PLUS_2]]75; CHECK-NEXT: [[L2:%.*]] = load i32, ptr [[GEP_IV_1_PLUS_2]], align 476; CHECK-NEXT: [[L3:%.*]] = load i32, ptr [[GEP_IV_2]], align 477; CHECK-NEXT: [[ADD:%.*]] = add i32 [[L3]], [[L2]]78; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP_IV_2]], align 479; CHECK-NEXT: [[IV_2_NEXT]] = add nuw nsw i64 [[IV_2]], 380; CHECK-NEXT: [[ICMP:%.*]] = icmp ugt i64 [[IV_2]], 5081; CHECK-NEXT: br i1 [[ICMP]], label [[EXIT:%.*]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]82; CHECK: exit:83; CHECK-NEXT: ret void84;85entry:86 br label %loop87 88loop:89 %iv.1 = phi i64 [ 1, %entry ], [ %iv.1.next, %loop ]90 %iv.2 = phi i64 [ 4, %entry ], [ %iv.2.next, %loop ]91 %iv.1.next = add nuw nsw i64 %iv.1, 392 %iv.1.plus.4 = add nuw nsw i64 %iv.1, 493 %gep.iv.1.plus.4 = getelementptr inbounds i32, ptr %arr, i64 %iv.1.plus.494 %l1 = load i32, ptr %gep.iv.1.plus.495 %gep.iv.2 = getelementptr inbounds i32, ptr %arr, i64 %iv.296 store i32 %l1, ptr %gep.iv.297 %iv.1.plus.2 = add nuw nsw i64 %iv.1, 298 %gep.iv.1.plus.2= getelementptr inbounds i32, ptr %arr, i64 %iv.1.plus.299 %l2 = load i32, ptr %gep.iv.1.plus.2100 %l3 = load i32, ptr %gep.iv.2101 %add = add i32 %l3 , %l2102 store i32 %add, ptr %gep.iv.2103 %iv.2.next = add nuw nsw i64 %iv.2, 3104 %icmp = icmp ugt i64 %iv.2, 50105 br i1 %icmp, label %exit, label %loop106 107exit:108 ret void109}110 111; %l3 and the preceeding store access the same memory location. So, we cannot112; have the loads %l1, %l2 and %l3 in the same interleave group since it would113; mean hoisting the load %l2 and %l3 across the store.114 115; Unlike the above case, since we go through the last load in program order and116; compare against the obstructing stores (%l2 versus the store) there is no117; dependency. However, the other load in %l2's interleave group (%l3) does118; obstruct with the store.119define void @pr63602_2(ptr %arr) {120; CHECK-LABEL: define void @pr63602_2121; CHECK-SAME: (ptr [[ARR:%.*]]) {122; CHECK-NEXT: entry:123; CHECK-NEXT: br label [[VECTOR_PH:%.*]]124; CHECK: vector.ph:125; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]126; CHECK: vector.body:127; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]128; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[INDEX]], 3129; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[TMP0]]130; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 0131; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 3132; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 6133; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 9134; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[INDEX]], 3135; CHECK-NEXT: [[OFFSET_IDX1:%.*]] = add i64 4, [[TMP5]]136; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX1]], 0137; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX1]], 3138; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX1]], 6139; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX1]], 9140; CHECK-NEXT: [[TMP10:%.*]] = add nuw nsw i64 [[TMP1]], 4141; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP10]]142; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <12 x i32>, ptr [[TMP11]], align 4143; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <12 x i32> [[WIDE_VEC]], <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>144; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[STRIDED_VEC]], i32 0145; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i32> [[STRIDED_VEC]], i32 1146; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i32> [[STRIDED_VEC]], i32 2147; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[STRIDED_VEC]], i32 3148; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP6]]149; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP7]]150; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP8]]151; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP9]]152; CHECK-NEXT: store i32 [[TMP12]], ptr [[TMP16]], align 4153; CHECK-NEXT: store i32 [[TMP13]], ptr [[TMP17]], align 4154; CHECK-NEXT: store i32 [[TMP14]], ptr [[TMP18]], align 4155; CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP19]], align 4156; CHECK-NEXT: [[TMP20:%.*]] = add nuw nsw i64 [[TMP1]], 2157; CHECK-NEXT: [[TMP21:%.*]] = add nuw nsw i64 [[TMP2]], 2158; CHECK-NEXT: [[TMP22:%.*]] = add nuw nsw i64 [[TMP3]], 2159; CHECK-NEXT: [[TMP23:%.*]] = add nuw nsw i64 [[TMP4]], 2160; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP20]]161; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP21]]162; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP22]]163; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP23]]164; CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP16]], align 4165; CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP17]], align 4166; CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP18]], align 4167; CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP19]], align 4168; CHECK-NEXT: [[TMP32:%.*]] = insertelement <4 x i32> poison, i32 [[TMP28]], i32 0169; CHECK-NEXT: [[TMP33:%.*]] = insertelement <4 x i32> [[TMP32]], i32 [[TMP29]], i32 1170; CHECK-NEXT: [[TMP34:%.*]] = insertelement <4 x i32> [[TMP33]], i32 [[TMP30]], i32 2171; CHECK-NEXT: [[TMP35:%.*]] = insertelement <4 x i32> [[TMP34]], i32 [[TMP31]], i32 3172; CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP24]], align 4173; CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP25]], align 4174; CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP26]], align 4175; CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP27]], align 4176; CHECK-NEXT: [[TMP40:%.*]] = insertelement <4 x i32> poison, i32 [[TMP36]], i32 0177; CHECK-NEXT: [[TMP41:%.*]] = insertelement <4 x i32> [[TMP40]], i32 [[TMP37]], i32 1178; CHECK-NEXT: [[TMP42:%.*]] = insertelement <4 x i32> [[TMP41]], i32 [[TMP38]], i32 2179; CHECK-NEXT: [[TMP43:%.*]] = insertelement <4 x i32> [[TMP42]], i32 [[TMP39]], i32 3180; CHECK-NEXT: [[TMP44:%.*]] = add <4 x i32> [[TMP35]], [[TMP43]]181; CHECK-NEXT: [[TMP45:%.*]] = extractelement <4 x i32> [[TMP44]], i32 0182; CHECK-NEXT: [[TMP46:%.*]] = extractelement <4 x i32> [[TMP44]], i32 1183; CHECK-NEXT: [[TMP47:%.*]] = extractelement <4 x i32> [[TMP44]], i32 2184; CHECK-NEXT: [[TMP48:%.*]] = extractelement <4 x i32> [[TMP44]], i32 3185; CHECK-NEXT: store i32 [[TMP45]], ptr [[TMP16]], align 4186; CHECK-NEXT: store i32 [[TMP46]], ptr [[TMP17]], align 4187; CHECK-NEXT: store i32 [[TMP47]], ptr [[TMP18]], align 4188; CHECK-NEXT: store i32 [[TMP48]], ptr [[TMP19]], align 4189; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4190; CHECK-NEXT: [[TMP49:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16191; CHECK-NEXT: br i1 [[TMP49]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]192; CHECK: middle.block:193; CHECK-NEXT: br label [[SCALAR_PH:%.*]]194; CHECK: scalar.ph:195; CHECK-NEXT: br label [[LOOP:%.*]]196; CHECK: loop:197; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ 49, [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ]198; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ 52, [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ]199; CHECK-NEXT: [[IV_1_NEXT]] = add nuw nsw i64 [[IV_1]], 3200; CHECK-NEXT: [[IV_1_PLUS_4:%.*]] = add nuw nsw i64 [[IV_1]], 4201; CHECK-NEXT: [[GEP_IV_1_PLUS_4:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[IV_1_PLUS_4]]202; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_IV_1_PLUS_4]], align 4203; CHECK-NEXT: [[GEP_IV_2:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[IV_2]]204; CHECK-NEXT: store i32 [[L1]], ptr [[GEP_IV_2]], align 4205; CHECK-NEXT: [[IV_1_PLUS_2:%.*]] = add nuw nsw i64 [[IV_1]], 2206; CHECK-NEXT: [[GEP_IV_1_PLUS_2:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[IV_1_PLUS_2]]207; CHECK-NEXT: [[L3:%.*]] = load i32, ptr [[GEP_IV_2]], align 4208; CHECK-NEXT: [[L2:%.*]] = load i32, ptr [[GEP_IV_1_PLUS_2]], align 4209; CHECK-NEXT: [[ADD:%.*]] = add i32 [[L3]], [[L2]]210; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP_IV_2]], align 4211; CHECK-NEXT: [[IV_2_NEXT]] = add nuw nsw i64 [[IV_2]], 3212; CHECK-NEXT: [[ICMP:%.*]] = icmp ugt i64 [[IV_2]], 50213; CHECK-NEXT: br i1 [[ICMP]], label [[EXIT:%.*]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]214; CHECK: exit:215; CHECK-NEXT: ret void216;217entry:218 br label %loop219 220loop:221 %iv.1 = phi i64 [ 1, %entry ], [ %iv.1.next, %loop ]222 %iv.2 = phi i64 [ 4, %entry ], [ %iv.2.next, %loop ]223 %iv.1.next = add nuw nsw i64 %iv.1, 3224 %iv.1.plus.4 = add nuw nsw i64 %iv.1, 4225 %gep.iv.1.plus.4 = getelementptr inbounds i32, ptr %arr, i64 %iv.1.plus.4226 %l1 = load i32, ptr %gep.iv.1.plus.4227 %gep.iv.2 = getelementptr inbounds i32, ptr %arr, i64 %iv.2228 store i32 %l1, ptr %gep.iv.2229 %iv.1.plus.2 = add nuw nsw i64 %iv.1, 2230 %gep.iv.1.plus.2= getelementptr inbounds i32, ptr %arr, i64 %iv.1.plus.2231 %l3 = load i32, ptr %gep.iv.2232 %l2 = load i32, ptr %gep.iv.1.plus.2233 %add = add i32 %l3 , %l2234 store i32 %add, ptr %gep.iv.2235 %iv.2.next = add nuw nsw i64 %iv.2, 3236 %icmp = icmp ugt i64 %iv.2, 50237 br i1 %icmp, label %exit, label %loop238 239exit:240 ret void241}242