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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 32; RUN: opt -passes=loop-vectorize -mcpu=skx -enable-masked-interleaved-mem-accesses=1 -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s3target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"4target triple = "x86_64-apple-macos"5 6; %l2 load and the preceeding store has a dependency. We should not sink7; that store into the last store (by creating an interleaved store group). This8; means the loaded %l2 will have incorrect value.9define void @avoid_sinking_store_across_load(ptr %arr) {10; CHECK-LABEL: define void @avoid_sinking_store_across_load(11; CHECK-SAME: ptr [[ARR:%.*]]) #[[ATTR0:[0-9]+]] {12; CHECK-NEXT: entry:13; CHECK-NEXT: br label [[VECTOR_PH:%.*]]14; CHECK: vector.ph:15; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]16; CHECK: vector.body:17; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]18; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 1, i64 4, i64 7, i64 10>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]19; CHECK-NEXT: [[VEC_IND2:%.*]] = phi <4 x i64> [ <i64 4, i64 7, i64 10, i64 13>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT3:%.*]], [[VECTOR_BODY]] ]20; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[INDEX]], 321; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[TMP0]]22; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[OFFSET_IDX]], 423; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP2]]24; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <12 x i32>, ptr [[TMP3]], align 425; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <12 x i32> [[WIDE_VEC]], <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>26; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[ARR]], <4 x i64> [[VEC_IND2]]27; CHECK-NEXT: [[TMP5:%.*]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 2)28; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[ARR]], <4 x i64> [[TMP5]]29; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x ptr> [[TMP6]], i32 030; CHECK-NEXT: [[TMP7:%.*]] = mul <4 x i32> [[STRIDED_VEC]], splat (i32 25)31; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> [[TMP7]], <4 x ptr> align 4 [[TMP6]], <4 x i1> splat (i1 true))32; CHECK-NEXT: [[WIDE_VEC4:%.*]] = load <12 x i32>, ptr [[TMP8]], align 433; CHECK-NEXT: [[STRIDED_VEC5:%.*]] = shufflevector <12 x i32> [[WIDE_VEC4]], <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>34; CHECK-NEXT: [[STRIDED_VEC6:%.*]] = shufflevector <12 x i32> [[WIDE_VEC4]], <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>35; CHECK-NEXT: [[TMP9:%.*]] = add <4 x i32> [[STRIDED_VEC6]], [[STRIDED_VEC5]]36; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> [[TMP9]], <4 x ptr> align 4 [[TMP4]], <4 x i1> splat (i1 true))37; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 438; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 12)39; CHECK-NEXT: [[VEC_IND_NEXT3]] = add nuw nsw <4 x i64> [[VEC_IND2]], splat (i64 12)40; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1641; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]42; CHECK: middle.block:43; CHECK-NEXT: br label [[SCALAR_PH:%.*]]44; CHECK: scalar.ph:45; CHECK-NEXT: br label [[LOOP:%.*]]46; CHECK: loop:47; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ 49, [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ]48; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ 52, [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ]49; CHECK-NEXT: [[IV_1_NEXT]] = add nuw nsw i64 [[IV_1]], 350; CHECK-NEXT: [[IV_1_PLUS_4:%.*]] = add nuw nsw i64 [[IV_1]], 451; CHECK-NEXT: [[GEP_IV_1_PLUS_4:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[IV_1_PLUS_4]]52; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_IV_1_PLUS_4]], align 453; CHECK-NEXT: [[GEP_IV_2:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[IV_2]]54; CHECK-NEXT: [[IV_1_PLUS_2:%.*]] = add nuw nsw i64 [[IV_1]], 255; CHECK-NEXT: [[GEP_IV_1_PLUS_2:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[IV_1_PLUS_2]]56; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[L1]], 2557; CHECK-NEXT: store i32 [[MUL]], ptr [[GEP_IV_1_PLUS_2]], align 458; CHECK-NEXT: [[L2:%.*]] = load i32, ptr [[GEP_IV_1_PLUS_2]], align 459; CHECK-NEXT: [[L3:%.*]] = load i32, ptr [[GEP_IV_2]], align 460; CHECK-NEXT: [[ADD:%.*]] = add i32 [[L3]], [[L2]]61; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP_IV_2]], align 462; CHECK-NEXT: [[IV_2_NEXT]] = add nuw nsw i64 [[IV_2]], 363; CHECK-NEXT: [[ICMP:%.*]] = icmp ugt i64 [[IV_2]], 5064; CHECK-NEXT: br i1 [[ICMP]], label [[EXIT:%.*]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]65; CHECK: exit:66; CHECK-NEXT: ret void67;68entry:69 br label %loop70 71loop:72 %iv.1 = phi i64 [ 1, %entry ], [ %iv.1.next, %loop ]73 %iv.2 = phi i64 [ 4, %entry ], [ %iv.2.next, %loop ]74 %iv.1.next = add nuw nsw i64 %iv.1, 375 %iv.1.plus.4 = add nuw nsw i64 %iv.1, 476 %gep.iv.1.plus.4 = getelementptr inbounds i32, ptr %arr, i64 %iv.1.plus.477 %l1 = load i32, ptr %gep.iv.1.plus.478 %gep.iv.2 = getelementptr inbounds i32, ptr %arr, i64 %iv.279 %iv.1.plus.2 = add nuw nsw i64 %iv.1, 280 %gep.iv.1.plus.2= getelementptr inbounds i32, ptr %arr, i64 %iv.1.plus.281 %mul = mul i32 %l1, 2582 store i32 %mul, ptr %gep.iv.1.plus.283 %l2 = load i32, ptr %gep.iv.1.plus.284 %l3 = load i32, ptr %gep.iv.285 %add = add i32 %l3 , %l286 store i32 %add, ptr %gep.iv.287 %iv.2.next = add nuw nsw i64 %iv.2, 388 %icmp = icmp ugt i64 %iv.2, 5089 br i1 %icmp, label %exit, label %loop90 91exit:92 ret void93}94