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1; RUN: opt < %s -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=2 -debug-only=vectorutils -disable-output -enable-interleaved-mem-accesses=true 2>&1 | FileCheck %s2; REQUIRES: asserts3target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"4target triple = "x86_64-unknown-linux-gnu"5 6; PR402917; The loop does the following operation 3 times:8; 1. Load x from memory;9; 2. Store (x + 1) to this memory;10; 3. if (x < 1), store 0 to this memory.11 12; When scalar version stores 0 in all locations, the vector version should do13; the same thing. However, with interleaving it does not honour the WAW dependency between14; store 0 and store (x + 1) to the same memory.15; For now, we identify such unsafe dependency and disable adding the16; store into the interleaved group.17; In this test case, because we disable adding store into ptr %storeaddr12 and18; storeaddr22, we create interleaved groups with gaps and19; disable that interleaved group. So, we are only left with valid interleaved20; groups.21 22 23 24 25; CHECK: LV: Analyzing interleaved accesses...26; CHECK: LV: Creating an interleave group with: store i32 %tmp34, ptr %storeaddr32, align 427; CHECK-NEXT: LV: Inserted: store i32 %tmp24, ptr %storeaddr22, align 428; CHECK-NEXT: into the interleave group with store i32 %tmp34, ptr %storeaddr32, align 429; CHECK-NEXT: LV: Inserted: store i32 %tmp14, ptr %storeaddr12, align 430; CHECK-NEXT: into the interleave group with store i32 %tmp34, ptr %storeaddr32, align 431; CHECK: LV: Invalidated store group due to dependence between store i32 %tmp24, ptr %storeaddr22, align 4 and store i32 0, ptr %storeaddr22, align 432; CHECK-NEXT: LV: Creating an interleave group with: store i32 %tmp24, ptr %storeaddr22, align 433; CHECK-NEXT: LV: Inserted: store i32 %tmp14, ptr %storeaddr12, align 434; CHECK-NEXT: into the interleave group with store i32 %tmp24, ptr %storeaddr22, align 435; CHECK-NEXT: LV: Invalidated store group due to dependence between store i32 %tmp14, ptr %storeaddr12, align 4 and store i32 0, ptr %storeaddr12, align 436 37 38define void @test(ptr nonnull align 8 dereferenceable_or_null(24) %arg) {39bb:40 %tmp = getelementptr inbounds i8, ptr %arg, i64 1641 %tmp2 = load ptr, ptr %tmp, align 842 %tmp3 = getelementptr inbounds i8, ptr %arg, i64 843 %tmp5 = load ptr, ptr %tmp3, align 844 %tmp6 = getelementptr inbounds i8, ptr %tmp5, i64 1245 %tmp8 = getelementptr inbounds i8, ptr %tmp2, i64 1246 br label %header47 48header: ; preds = %latch, %bb49 %tmp10 = phi i64 [ %tmp41, %latch ], [ 3, %bb ]50 %tmp11 = add nsw i64 %tmp10, -151 %storeaddr12 = getelementptr inbounds i32, ptr %tmp6, i64 %tmp1152 %tmp13 = load i32, ptr %storeaddr12, align 453 %tmp14 = add i32 %tmp13, 154 store i32 %tmp14, ptr %storeaddr12, align 455 %tmp15 = icmp slt i32 %tmp13, 156 %tmp16 = xor i1 %tmp15, true57 %tmp17 = zext i1 %tmp16 to i858 %tmp18 = getelementptr inbounds i8, ptr %tmp8, i64 %tmp1059 store i8 %tmp17, ptr %tmp18, align 160 br i1 %tmp15, label %bb19, label %bb2061 62bb19: ; preds = %header63 store i32 0, ptr %storeaddr12, align 464 br label %bb2065 66bb20: ; preds = %bb19, %header67 %tmp21 = add nuw nsw i64 %tmp10, 168 %storeaddr22 = getelementptr inbounds i32, ptr %tmp6, i64 %tmp1069 %tmp23 = load i32, ptr %storeaddr22, align 470 %tmp24 = add i32 %tmp23, 171 store i32 %tmp24, ptr %storeaddr22, align 472 %tmp25 = icmp slt i32 %tmp23, 173 %tmp26 = xor i1 %tmp25, true74 %tmp27 = zext i1 %tmp26 to i875 %tmp28 = getelementptr inbounds i8, ptr %tmp8, i64 %tmp2176 store i8 %tmp27, ptr %tmp28, align 177 br i1 %tmp25, label %bb29, label %bb3078 79bb29: ; preds = %bb2080 store i32 0, ptr %storeaddr22, align 481 br label %bb3082 83bb30: ; preds = %bb29, %bb2084 %tmp31 = add nuw nsw i64 %tmp10, 285 %storeaddr32 = getelementptr inbounds i32, ptr %tmp6, i64 %tmp2186 %tmp33 = load i32, ptr %storeaddr32, align 487 %tmp34 = add i32 %tmp33, 188 store i32 %tmp34, ptr %storeaddr32, align 489 %tmp35 = icmp slt i32 %tmp33, 190 %tmp36 = xor i1 %tmp35, true91 %tmp37 = zext i1 %tmp36 to i892 %tmp38 = getelementptr inbounds i8, ptr %tmp8, i64 %tmp3193 store i8 %tmp37, ptr %tmp38, align 194 br i1 %tmp35, label %bb39, label %latch95 96bb39: ; preds = %bb3097 store i32 0, ptr %storeaddr32, align 498 br label %latch99 100latch: ; preds = %bb39, %bb30101 %tmp41 = add nuw nsw i64 %tmp10, 3102 %tmp42 = icmp ugt i64 %tmp31, 67103 br i1 %tmp42, label %exit, label %header104 105exit: ; preds = %latch106 ret void107}108