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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -mcpu=skylake-avx512 -S %s | FileCheck %s3 4target triple = "x86_64-unknown-linux-gnu"5 6define i64 @test_pr98660(ptr %dst, i64 %N) {7; CHECK-LABEL: define i64 @test_pr98660(8; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {9; CHECK-NEXT: [[ENTRY:.*]]:10; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 111; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 3212; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]13; CHECK: [[VECTOR_PH]]:14; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 3215; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]16; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]17; CHECK: [[VECTOR_BODY]]:18; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]19; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 120; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP5]]21; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP9]], i64 822; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1623; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP9]], i64 2424; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, ptr [[TMP9]], align 425; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x i32>, ptr [[TMP14]], align 426; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x i32>, ptr [[TMP15]], align 427; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i32>, ptr [[TMP16]], align 428; CHECK-NEXT: [[TMP17:%.*]] = icmp eq <8 x i32> [[WIDE_LOAD]], zeroinitializer29; CHECK-NEXT: [[TMP18:%.*]] = icmp eq <8 x i32> [[WIDE_LOAD1]], zeroinitializer30; CHECK-NEXT: [[TMP19:%.*]] = icmp eq <8 x i32> [[WIDE_LOAD2]], zeroinitializer31; CHECK-NEXT: [[TMP20:%.*]] = icmp eq <8 x i32> [[WIDE_LOAD3]], zeroinitializer32; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr align 4 [[TMP9]], <8 x i1> [[TMP17]])33; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr align 4 [[TMP14]], <8 x i1> [[TMP18]])34; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr align 4 [[TMP15]], <8 x i1> [[TMP19]])35; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr align 4 [[TMP16]], <8 x i1> [[TMP20]])36; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 3237; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]38; CHECK-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]39; CHECK: [[MIDDLE_BLOCK]]:40; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]41; CHECK-NEXT: [[IND_ESCAPE:%.*]] = sub i64 [[N_VEC]], 142; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]43; CHECK: [[SCALAR_PH]]:44; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]45; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]46; CHECK: [[LOOP_HEADER]]:47; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]48; CHECK-NEXT: [[OR:%.*]] = or disjoint i64 [[IV]], 149; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[OR]]50; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP]], align 451; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 052; CHECK-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_LATCH]]53; CHECK: [[THEN]]:54; CHECK-NEXT: store i32 0, ptr [[GEP]], align 455; CHECK-NEXT: br label %[[LOOP_LATCH]]56; CHECK: [[LOOP_LATCH]]:57; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 158; CHECK-NEXT: [[EC:%.*]] = icmp ult i64 [[IV]], [[N]]59; CHECK-NEXT: br i1 [[EC]], label %[[LOOP_HEADER]], label %[[EXIT]], !llvm.loop [[LOOP3:![0-9]+]]60; CHECK: [[EXIT]]:61; CHECK-NEXT: [[RET:%.*]] = phi i64 [ [[IV]], %[[LOOP_LATCH]] ], [ [[IND_ESCAPE]], %[[MIDDLE_BLOCK]] ]62; CHECK-NEXT: ret i64 [[RET]]63;64entry:65 br label %loop.header66 67loop.header:68 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]69 %or = or disjoint i64 %iv, 170 %gep = getelementptr i32, ptr %dst, i64 %or71 %l = load i32, ptr %gep72 %c = icmp eq i32 %l, 073 br i1 %c, label %then, label %loop.latch74 75then:76 store i32 0, ptr %gep, align 477 br label %loop.latch78 79loop.latch:80 %iv.next = add i64 %iv, 181 %ec = icmp ult i64 %iv, %N82 br i1 %ec, label %loop.header, label %exit83 84exit:85 %ret = phi i64 [ %iv, %loop.latch ]86 ret i64 %ret87}88;.89; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}90; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}91; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}92; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}93;.94