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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=loop-vectorize -mcpu=skylake-avx512 -S %s | FileCheck %s3 4target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"5target triple = "x86_64-unknown-linux-gnu"6 7; Make sure selected VF for the epilog loop doesn't exceed remaining TC.8define void @test_tc_17_no_epilogue_vectorization(ptr noalias %src, ptr noalias %dst) {9; CHECK-LABEL: @test_tc_17_no_epilogue_vectorization(10; CHECK-NEXT: entry:11; CHECK-NEXT: br label [[VECTOR_PH:%.*]]12; CHECK: vector.ph:13; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]14; CHECK: vector.body:15; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[TMP1:%.*]], align 6416; CHECK-NEXT: store <16 x i8> [[WIDE_LOAD]], ptr [[TMP3:%.*]], align 6417; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]]18; CHECK: middle.block:19; CHECK-NEXT: br label [[SCALAR_PH:%.*]]20; CHECK: scalar.ph:21; CHECK-NEXT: br label [[LOOP:%.*]]22; CHECK: loop:23; CHECK-NEXT: [[I:%.*]] = phi i64 [ 16, [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[LOOP]] ]24; CHECK-NEXT: [[LDADDR:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 [[I]]25; CHECK-NEXT: [[VAL:%.*]] = load i8, ptr [[LDADDR]], align 6426; CHECK-NEXT: [[STADDR:%.*]] = getelementptr inbounds i8, ptr [[TMP3]], i64 [[I]]27; CHECK-NEXT: store i8 [[VAL]], ptr [[STADDR]], align 6428; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 129; CHECK-NEXT: [[IS_NEXT:%.*]] = icmp ult i64 [[I_NEXT]], 1730; CHECK-NEXT: br i1 [[IS_NEXT]], label [[LOOP]], label [[EXIT:%.*]], !llvm.loop [[LOOP0:![0-9]+]]31; CHECK: exit:32; CHECK-NEXT: ret void33;34entry:35 br label %loop36 37loop:38 %i = phi i64 [ 0, %entry ], [ %i.next, %loop ]39 %ldaddr = getelementptr inbounds i8, ptr %src, i64 %i40 %val = load i8, ptr %ldaddr, align 6441 %staddr = getelementptr inbounds i8, ptr %dst, i64 %i42 store i8 %val, ptr %staddr, align 6443 %i.next = add i64 %i, 144 %is.next = icmp ult i64 %i.next, 1745 br i1 %is.next, label %loop, label %exit46 47exit:48 ret void49}50 51define void @test_tc_18(ptr noalias %src, ptr noalias %dst) {52; CHECK-LABEL: @test_tc_18(53; CHECK-NEXT: iter.check:54; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]55; CHECK: vector.main.loop.iter.check:56; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]57; CHECK: vector.ph:58; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]59; CHECK: vector.body:60; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]61; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[INDEX]]62; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[TMP1]], align 6463; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[DST:%.*]], i64 [[INDEX]]64; CHECK-NEXT: store <16 x i8> [[WIDE_LOAD]], ptr [[TMP3]], align 6465; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1666; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1667; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]68; CHECK: middle.block:69; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]70; CHECK: vec.epilog.iter.check:71; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF4:![0-9]+]]72; CHECK: vec.epilog.ph:73; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ 16, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]74; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]75; CHECK: vec.epilog.vector.body:76; CHECK-NEXT: [[INDEX1:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT3:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]77; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX1]]78; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <2 x i8>, ptr [[TMP7]], align 6479; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[INDEX1]]80; CHECK-NEXT: store <2 x i8> [[WIDE_LOAD2]], ptr [[TMP9]], align 6481; CHECK-NEXT: [[INDEX_NEXT3]] = add nuw i64 [[INDEX1]], 282; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT3]], 1883; CHECK-NEXT: br i1 [[TMP11]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]84; CHECK: vec.epilog.middle.block:85; CHECK-NEXT: br i1 true, label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]]86; CHECK: vec.epilog.scalar.ph:87; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 18, [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 16, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ]88; CHECK-NEXT: br label [[LOOP:%.*]]89; CHECK: loop:90; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[LOOP]] ]91; CHECK-NEXT: [[LDADDR:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[I]]92; CHECK-NEXT: [[VAL:%.*]] = load i8, ptr [[LDADDR]], align 6493; CHECK-NEXT: [[STADDR:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[I]]94; CHECK-NEXT: store i8 [[VAL]], ptr [[STADDR]], align 6495; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 196; CHECK-NEXT: [[IS_NEXT:%.*]] = icmp ult i64 [[I_NEXT]], 1897; CHECK-NEXT: br i1 [[IS_NEXT]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP6:![0-9]+]]98; CHECK: exit:99; CHECK-NEXT: ret void100;101entry:102 br label %loop103 104loop:105 %i = phi i64 [ 0, %entry ], [ %i.next, %loop ]106 %ldaddr = getelementptr inbounds i8, ptr %src, i64 %i107 %val = load i8, ptr %ldaddr, align 64108 %staddr = getelementptr inbounds i8, ptr %dst, i64 %i109 store i8 %val, ptr %staddr, align 64110 %i.next = add i64 %i, 1111 %is.next = icmp ult i64 %i.next, 18112 br i1 %is.next, label %loop, label %exit113 114exit:115 ret void116}117 118define void @test_tc_19(ptr noalias %src, ptr noalias %dst) {119; CHECK-LABEL: @test_tc_19(120; CHECK-NEXT: iter.check:121; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]122; CHECK: vector.main.loop.iter.check:123; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]124; CHECK: vector.ph:125; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]126; CHECK: vector.body:127; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]128; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[INDEX]]129; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[TMP1]], align 64130; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[DST:%.*]], i64 [[INDEX]]131; CHECK-NEXT: store <16 x i8> [[WIDE_LOAD]], ptr [[TMP3]], align 64132; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16133; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16134; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]135; CHECK: middle.block:136; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]137; CHECK: vec.epilog.iter.check:138; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF4]]139; CHECK: vec.epilog.ph:140; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ 16, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]141; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]142; CHECK: vec.epilog.vector.body:143; CHECK-NEXT: [[INDEX1:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT3:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]144; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX1]]145; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <2 x i8>, ptr [[TMP7]], align 64146; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[INDEX1]]147; CHECK-NEXT: store <2 x i8> [[WIDE_LOAD2]], ptr [[TMP9]], align 64148; CHECK-NEXT: [[INDEX_NEXT3]] = add nuw i64 [[INDEX1]], 2149; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT3]], 18150; CHECK-NEXT: br i1 [[TMP11]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]151; CHECK: vec.epilog.middle.block:152; CHECK-NEXT: br i1 false, label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]]153; CHECK: vec.epilog.scalar.ph:154; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 18, [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 16, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ]155; CHECK-NEXT: br label [[LOOP:%.*]]156; CHECK: loop:157; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[LOOP]] ]158; CHECK-NEXT: [[LDADDR:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[I]]159; CHECK-NEXT: [[VAL:%.*]] = load i8, ptr [[LDADDR]], align 64160; CHECK-NEXT: [[STADDR:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[I]]161; CHECK-NEXT: store i8 [[VAL]], ptr [[STADDR]], align 64162; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1163; CHECK-NEXT: [[IS_NEXT:%.*]] = icmp ult i64 [[I_NEXT]], 19164; CHECK-NEXT: br i1 [[IS_NEXT]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP9:![0-9]+]]165; CHECK: exit:166; CHECK-NEXT: ret void167;168entry:169 br label %loop170 171loop:172 %i = phi i64 [ 0, %entry ], [ %i.next, %loop ]173 %ldaddr = getelementptr inbounds i8, ptr %src, i64 %i174 %val = load i8, ptr %ldaddr, align 64175 %staddr = getelementptr inbounds i8, ptr %dst, i64 %i176 store i8 %val, ptr %staddr, align 64177 %i.next = add i64 %i, 1178 %is.next = icmp ult i64 %i.next, 19179 br i1 %is.next, label %loop, label %exit180 181exit:182 ret void183}184 185define void @test_tc_20(ptr noalias %src, ptr noalias %dst) {186; CHECK-LABEL: @test_tc_20(187; CHECK-NEXT: iter.check:188; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]189; CHECK: vector.main.loop.iter.check:190; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]191; CHECK: vector.ph:192; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]193; CHECK: vector.body:194; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]195; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[INDEX]]196; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 4197; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 8198; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 12199; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 64200; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i8>, ptr [[TMP3]], align 64201; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i8>, ptr [[TMP4]], align 64202; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i8>, ptr [[TMP5]], align 64203; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[DST:%.*]], i64 [[INDEX]]204; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 4205; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 8206; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 12207; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD]], ptr [[TMP6]], align 64208; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD1]], ptr [[TMP8]], align 64209; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD2]], ptr [[TMP9]], align 64210; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD3]], ptr [[TMP10]], align 64211; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16212; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16213; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]214; CHECK: middle.block:215; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]216; CHECK: vec.epilog.iter.check:217; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF11:![0-9]+]]218; CHECK: vec.epilog.ph:219; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ 16, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]220; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]221; CHECK: vec.epilog.vector.body:222; CHECK-NEXT: [[INDEX4:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT6:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]223; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX4]]224; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i8>, ptr [[TMP13]], align 64225; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[INDEX4]]226; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD5]], ptr [[TMP15]], align 64227; CHECK-NEXT: [[INDEX_NEXT6]] = add nuw i64 [[INDEX4]], 4228; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT6]], 20229; CHECK-NEXT: br i1 [[TMP17]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]230; CHECK: vec.epilog.middle.block:231; CHECK-NEXT: br i1 true, label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]]232; CHECK: vec.epilog.scalar.ph:233; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 20, [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 16, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ]234; CHECK-NEXT: br label [[LOOP:%.*]]235; CHECK: loop:236; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[LOOP]] ]237; CHECK-NEXT: [[LDADDR:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[I]]238; CHECK-NEXT: [[VAL:%.*]] = load i8, ptr [[LDADDR]], align 64239; CHECK-NEXT: [[STADDR:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[I]]240; CHECK-NEXT: store i8 [[VAL]], ptr [[STADDR]], align 64241; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1242; CHECK-NEXT: [[IS_NEXT:%.*]] = icmp ult i64 [[I_NEXT]], 20243; CHECK-NEXT: br i1 [[IS_NEXT]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP13:![0-9]+]]244; CHECK: exit:245; CHECK-NEXT: ret void246;247entry:248 br label %loop249 250loop:251 %i = phi i64 [ 0, %entry ], [ %i.next, %loop ]252 %ldaddr = getelementptr inbounds i8, ptr %src, i64 %i253 %val = load i8, ptr %ldaddr, align 64254 %staddr = getelementptr inbounds i8, ptr %dst, i64 %i255 store i8 %val, ptr %staddr, align 64256 %i.next = add i64 %i, 1257 %is.next = icmp ult i64 %i.next, 20258 br i1 %is.next, label %loop, label %exit259 260exit:261 ret void262}263 264define void @limit_main_loop_vf_to_avoid_dead_main_vector_loop(ptr noalias %src, ptr noalias %dst) {265; CHECK-LABEL: @limit_main_loop_vf_to_avoid_dead_main_vector_loop(266; CHECK-NEXT: entry:267; CHECK-NEXT: br label [[VECTOR_PH:%.*]]268; CHECK: vector.ph:269; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]270; CHECK: vector.body:271; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]272; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [3 x i8], ptr [[SRC:%.*]], i64 [[INDEX]], i64 0273; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <24 x i8>, ptr [[TMP1]], align 1274; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <24 x i8> [[WIDE_VEC]], <24 x i8> poison, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>275; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[DST:%.*]], i64 [[INDEX]]276; CHECK-NEXT: store <8 x i8> [[STRIDED_VEC]], ptr [[TMP3]], align 1277; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8278; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 24279; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]280; CHECK: middle.block:281; CHECK-NEXT: br label [[SCALAR_PH:%.*]]282; CHECK: scalar.ph:283; CHECK-NEXT: br label [[LOOP:%.*]]284; CHECK: loop:285; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 24, [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]286; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds [3 x i8], ptr [[SRC]], i64 [[IV]], i64 0287; CHECK-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 1288; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[IV]]289; CHECK-NEXT: store i8 [[L]], ptr [[GEP_DST]], align 1290; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1291; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 32292; CHECK-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[LOOP]], !llvm.loop [[LOOP15:![0-9]+]]293; CHECK: exit:294; CHECK-NEXT: ret void295;296entry:297 br label %loop298 299loop:300 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]301 %gep.src = getelementptr inbounds [3 x i8], ptr %src, i64 %iv, i64 0302 %l = load i8, ptr %gep.src, align 1303 %gep.dst = getelementptr inbounds i8, ptr %dst, i64 %iv304 store i8 %l, ptr %gep.dst, align 1305 %iv.next = add nuw nsw i64 %iv, 1306 %cmp = icmp eq i64 %iv.next, 32307 br i1 %cmp, label %exit, label %loop308 309exit:310 ret void311}312