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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -p loop-vectorize -mtriple=x86_64-apple-macosx -S %s | FileCheck %s3 4target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"5 6define i32 @test_scalar_predicated_cost(i64 %x, i64 %y, ptr %A) #0 {7; CHECK-LABEL: define i32 @test_scalar_predicated_cost(8; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]], ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {9; CHECK-NEXT: iter.check:10; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]11; CHECK: vector.main.loop.iter.check:12; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH1:%.*]]13; CHECK: vector.ph:14; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[Y]], i64 015; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i64> [[BROADCAST_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer16; CHECK-NEXT: [[BROADCAST_SPLATINSERT4:%.*]] = insertelement <8 x i64> poison, i64 [[X]], i64 017; CHECK-NEXT: [[BROADCAST_SPLAT5:%.*]] = shufflevector <8 x i64> [[BROADCAST_SPLATINSERT4]], <8 x i64> poison, <8 x i32> zeroinitializer18; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]19; CHECK: vector.body:20; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]21; CHECK-NEXT: [[VEC_IND:%.*]] = phi <8 x i64> [ <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>, [[VECTOR_PH1]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]22; CHECK-NEXT: [[STEP_ADD:%.*]] = add <8 x i64> [[VEC_IND]], splat (i64 8)23; CHECK-NEXT: [[STEP_ADD1:%.*]] = add <8 x i64> [[STEP_ADD]], splat (i64 8)24; CHECK-NEXT: [[STEP_ADD2:%.*]] = add <8 x i64> [[STEP_ADD1]], splat (i64 8)25; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt <8 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]26; CHECK-NEXT: [[TMP9:%.*]] = icmp ugt <8 x i64> [[STEP_ADD]], [[BROADCAST_SPLAT]]27; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt <8 x i64> [[STEP_ADD1]], [[BROADCAST_SPLAT]]28; CHECK-NEXT: [[TMP11:%.*]] = icmp ugt <8 x i64> [[STEP_ADD2]], [[BROADCAST_SPLAT]]29; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i64> [[BROADCAST_SPLAT5]], [[VEC_IND]]30; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i64> [[BROADCAST_SPLAT5]], [[STEP_ADD]]31; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i64> [[BROADCAST_SPLAT5]], [[STEP_ADD1]]32; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i64> [[BROADCAST_SPLAT5]], [[STEP_ADD2]]33; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[A]], i64 [[INDEX]]34; CHECK-NEXT: [[TMP20:%.*]] = trunc <8 x i64> [[TMP12]] to <8 x i32>35; CHECK-NEXT: [[TMP21:%.*]] = trunc <8 x i64> [[TMP13]] to <8 x i32>36; CHECK-NEXT: [[TMP22:%.*]] = trunc <8 x i64> [[TMP14]] to <8 x i32>37; CHECK-NEXT: [[TMP23:%.*]] = trunc <8 x i64> [[TMP15]] to <8 x i32>38; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP16]], i64 839; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP16]], i64 1640; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[TMP16]], i64 2441; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> [[TMP20]], ptr align 4 [[TMP16]], <8 x i1> [[TMP8]])42; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> [[TMP21]], ptr align 4 [[TMP25]], <8 x i1> [[TMP9]])43; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> [[TMP22]], ptr align 4 [[TMP26]], <8 x i1> [[TMP10]])44; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> [[TMP23]], ptr align 4 [[TMP27]], <8 x i1> [[TMP11]])45; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 3246; CHECK-NEXT: [[VEC_IND_NEXT]] = add <8 x i64> [[STEP_ADD2]], splat (i64 8)47; CHECK-NEXT: [[TMP28:%.*]] = icmp eq i64 [[INDEX_NEXT]], 9648; CHECK-NEXT: br i1 [[TMP28]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]49; CHECK: middle.block:50; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]51; CHECK: vec.epilog.iter.check:52; CHECK-NEXT: br i1 false, label [[SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]53; CHECK: vec.epilog.ph:54; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ 96, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_PH]] ]55; CHECK-NEXT: [[BROADCAST_SPLATINSERT7:%.*]] = insertelement <4 x i64> poison, i64 [[Y]], i64 056; CHECK-NEXT: [[BROADCAST_SPLAT8:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT7]], <4 x i64> poison, <4 x i32> zeroinitializer57; CHECK-NEXT: [[BROADCAST_SPLATINSERT9:%.*]] = insertelement <4 x i64> poison, i64 [[X]], i64 058; CHECK-NEXT: [[BROADCAST_SPLAT10:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT9]], <4 x i64> poison, <4 x i32> zeroinitializer59; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[VEC_EPILOG_RESUME_VAL]], i64 060; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i64> [[DOTSPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer61; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i64> [[DOTSPLAT]], <i64 0, i64 1, i64 2, i64 3>62; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]63; CHECK: vec.epilog.vector.body:64; CHECK-NEXT: [[INDEX4:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT11:%.*]], [[LOOP_HEADER]] ]65; CHECK-NEXT: [[VEC_IND5:%.*]] = phi <4 x i64> [ [[INDUCTION]], [[VEC_EPILOG_PH]] ], [ [[VEC_IND_NEXT6:%.*]], [[LOOP_HEADER]] ]66; CHECK-NEXT: [[TMP33:%.*]] = icmp ugt <4 x i64> [[VEC_IND5]], [[BROADCAST_SPLAT8]]67; CHECK-NEXT: [[TMP34:%.*]] = or <4 x i64> [[BROADCAST_SPLAT10]], [[VEC_IND5]]68; CHECK-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr [[A]], i64 [[INDEX4]]69; CHECK-NEXT: [[TMP36:%.*]] = trunc <4 x i64> [[TMP34]] to <4 x i32>70; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[TMP36]], ptr align 4 [[TMP35]], <4 x i1> [[TMP33]])71; CHECK-NEXT: [[INDEX_NEXT11]] = add nuw i64 [[INDEX4]], 472; CHECK-NEXT: [[VEC_IND_NEXT6]] = add <4 x i64> [[VEC_IND5]], splat (i64 4)73; CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[INDEX_NEXT11]], 10074; CHECK-NEXT: br i1 [[TMP30]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[LOOP_HEADER]], !llvm.loop [[LOOP4:![0-9]+]]75; CHECK: vec.epilog.middle.block:76; CHECK-NEXT: br i1 false, label [[EXIT]], label [[SCALAR_PH]]77; CHECK: vec.epilog.scalar.ph:78; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 100, [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 96, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ]79; CHECK-NEXT: br label [[LOOP_HEADER1:%.*]]80; CHECK: loop.header:81; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]82; CHECK-NEXT: [[CMP9_NOT:%.*]] = icmp ule i64 [[IV]], [[Y]]83; CHECK-NEXT: br i1 [[CMP9_NOT]], label [[LOOP_LATCH]], label [[IF_THEN:%.*]]84; CHECK: if.then:85; CHECK-NEXT: [[OR:%.*]] = or i64 [[X]], [[IV]]86; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[A]], i64 [[IV]]87; CHECK-NEXT: [[T:%.*]] = trunc i64 [[OR]] to i3288; CHECK-NEXT: store i32 [[T]], ptr [[GEP]], align 489; CHECK-NEXT: br label [[LOOP_LATCH]]90; CHECK: loop.latch:91; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 192; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 10093; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER1]], !llvm.loop [[LOOP5:![0-9]+]]94; CHECK: exit:95; CHECK-NEXT: ret i32 096;97entry:98 br label %loop.header99 100loop.header:101 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]102 %cmp9.not = icmp ule i64 %iv, %y103 br i1 %cmp9.not, label %loop.latch, label %if.then104 105if.then:106 %or = or i64 %x, %iv107 %gep = getelementptr i32, ptr %A, i64 %iv108 %t = trunc i64 %or to i32109 store i32 %t, ptr %gep, align 4110 br label %loop.latch111 112loop.latch:113 %iv.next = add i64 %iv, 1114 %ec = icmp eq i64 %iv, 100115 br i1 %ec, label %exit, label %loop.header116 117exit:118 ret i32 0119}120 121define void @test_scalar_cost_single_store_loop_invariant_cond(ptr %dst, i1 %c) #0 {122; CHECK-LABEL: define void @test_scalar_cost_single_store_loop_invariant_cond(123; CHECK-SAME: ptr [[DST:%.*]], i1 [[C:%.*]]) #[[ATTR0]] {124; CHECK-NEXT: entry:125; CHECK-NEXT: br label [[VECTOR_PH:%.*]]126; CHECK: vector.ph:127; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[DST]], i64 96128; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i1> poison, i1 [[C]], i64 0129; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i1> [[BROADCAST_SPLATINSERT]], <8 x i1> poison, <8 x i32> zeroinitializer130; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]131; CHECK: vector.body:132; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]133; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4134; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[OFFSET_IDX]]135; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr align 4 [[NEXT_GEP]], <8 x i1> [[BROADCAST_SPLAT]])136; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8137; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 24138; CHECK-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]139; CHECK: middle.block:140; CHECK-NEXT: br label [[SCALAR_PH:%.*]]141; CHECK: scalar.ph:142; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]143; CHECK: loop.header:144; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[IND_END]], [[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]145; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 96, [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH]] ]146; CHECK-NEXT: br i1 [[C]], label [[IF_THEN:%.*]], label [[LOOP_LATCH]]147; CHECK: if.then:148; CHECK-NEXT: store i32 0, ptr [[PTR_IV]], align 4149; CHECK-NEXT: br label [[LOOP_LATCH]]150; CHECK: loop.latch:151; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 4152; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[DST]], i64 [[IV_NEXT]]153; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[IV]], 116154; CHECK-NEXT: br i1 [[CMP_NOT]], label [[EXIT:%.*]], label [[LOOP_HEADER]], !llvm.loop [[LOOP7:![0-9]+]]155; CHECK: exit:156; CHECK-NEXT: ret void157;158entry:159 br label %loop.header160 161loop.header:162 %ptr.iv = phi ptr [ %dst, %entry ], [ %ptr.iv.next, %loop.latch ]163 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]164 br i1 %c, label %if.then, label %loop.latch165 166if.then:167 store i32 0, ptr %ptr.iv, align 4168 br label %loop.latch169 170loop.latch:171 %iv.next = add i64 %iv, 4172 %ptr.iv.next = getelementptr i8, ptr %dst, i64 %iv.next173 %cmp.not = icmp eq i64 %iv, 116174 br i1 %cmp.not, label %exit, label %loop.header175 176exit:177 ret void178}179 180define void @test_scalar_cost_single_store_loop_varying_cond(ptr %dst, ptr noalias %src) #0 {181; CHECK-LABEL: define void @test_scalar_cost_single_store_loop_varying_cond(182; CHECK-SAME: ptr [[DST:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {183; CHECK-NEXT: entry:184; CHECK-NEXT: br label [[VECTOR_PH:%.*]]185; CHECK: vector.ph:186; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[DST]], i64 96187; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]188; CHECK: vector.body:189; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]190; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4191; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[OFFSET_IDX]]192; CHECK-NEXT: [[OFFSET_IDX3:%.*]] = mul i64 [[INDEX]], 4193; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX3]], 16194; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[OFFSET_IDX3]]195; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP3]]196; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <16 x i32>, ptr [[TMP4]], align 4197; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <16 x i32> [[WIDE_VEC]], <16 x i32> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>198; CHECK-NEXT: [[WIDE_VEC4:%.*]] = load <16 x i32>, ptr [[TMP5]], align 4199; CHECK-NEXT: [[STRIDED_VEC5:%.*]] = shufflevector <16 x i32> [[WIDE_VEC4]], <16 x i32> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>200; CHECK-NEXT: [[TMP8:%.*]] = icmp eq <4 x i32> [[STRIDED_VEC]], splat (i32 123)201; CHECK-NEXT: [[TMP9:%.*]] = icmp eq <4 x i32> [[STRIDED_VEC5]], splat (i32 123)202; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i64 4203; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> zeroinitializer, ptr align 4 [[NEXT_GEP]], <4 x i1> [[TMP8]])204; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> zeroinitializer, ptr align 4 [[TMP11]], <4 x i1> [[TMP9]])205; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8206; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 24207; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]208; CHECK: middle.block:209; CHECK-NEXT: br label [[SCALAR_PH:%.*]]210; CHECK: scalar.ph:211; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]212; CHECK: loop.header:213; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[IND_END]], [[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]214; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 96, [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH]] ]215; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]]216; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4217; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 123218; CHECK-NEXT: br i1 [[C]], label [[IF_THEN:%.*]], label [[LOOP_LATCH]]219; CHECK: if.then:220; CHECK-NEXT: store i32 0, ptr [[PTR_IV]], align 4221; CHECK-NEXT: br label [[LOOP_LATCH]]222; CHECK: loop.latch:223; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 4224; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[DST]], i64 [[IV_NEXT]]225; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[IV]], 116226; CHECK-NEXT: br i1 [[CMP_NOT]], label [[EXIT:%.*]], label [[LOOP_HEADER]], !llvm.loop [[LOOP9:![0-9]+]]227; CHECK: exit:228; CHECK-NEXT: ret void229;230entry:231 br label %loop.header232 233loop.header:234 %ptr.iv = phi ptr [ %dst, %entry ], [ %ptr.iv.next, %loop.latch ]235 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]236 %gep.src = getelementptr inbounds i32, ptr %src, i64 %iv237 %l = load i32, ptr %gep.src238 %c = icmp eq i32 %l, 123239 br i1 %c, label %if.then, label %loop.latch240 241if.then:242 store i32 0, ptr %ptr.iv, align 4243 br label %loop.latch244 245loop.latch:246 %iv.next = add i64 %iv, 4247 %ptr.iv.next = getelementptr i8, ptr %dst, i64 %iv.next248 %cmp.not = icmp eq i64 %iv, 116249 br i1 %cmp.not, label %exit, label %loop.header250 251exit:252 ret void253}254 255attributes #0 = { "min-legal-vector-width"="0" "target-cpu"="skylake-avx512" }256;.257; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}258; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}259; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}260; CHECK: [[PROF3]] = !{!"branch_weights", i32 4, i32 28}261; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}262; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}263; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}264; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}265; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}266; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]}267;.268