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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -mtriple=x86_64-apple-macosx -mcpu=penryn -S %s | FileCheck %s3 4define i64 @test_value_in_exit_compare_chain_used_outside(ptr %src, i64 %x, i64 range(i64 1, 32) %N) {5; CHECK-LABEL: define i64 @test_value_in_exit_compare_chain_used_outside(6; CHECK-SAME: ptr [[SRC:%.*]], i64 [[X:%.*]], i64 range(i64 1, 32) [[N:%.*]]) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: [[ENTRY:.*]]:8; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[N]], -19; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[TMP0]]10; CHECK-NEXT: [[UMIN2:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 [[X]])11; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[UMIN2]], 112; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP2]], 813; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]14; CHECK: [[VECTOR_SCEVCHECK]]:15; CHECK-NEXT: [[TMP3:%.*]] = add nsw i64 [[N]], -116; CHECK-NEXT: [[TMP4:%.*]] = freeze i64 [[TMP3]]17; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[X]])18; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[UMIN]] to i119; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[UMIN]], 120; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]21; CHECK-NEXT: br i1 [[TMP7]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]22; CHECK: [[VECTOR_PH]]:23; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 824; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[N_MOD_VF]], 025; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i64 8, i64 [[N_MOD_VF]]26; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[TMP9]]27; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]28; CHECK: [[VECTOR_BODY]]:29; CHECK-NEXT: [[TMP10:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]30; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <8 x i8> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP29:%.*]], %[[VECTOR_BODY]] ]31; CHECK-NEXT: [[TMP18:%.*]] = and i64 [[TMP10]], 132; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP18]]33; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[TMP26]], i64 034; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP12]], i64 -735; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP28]], align 136; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <8 x i8> [[WIDE_LOAD]], <8 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>37; CHECK-NEXT: [[TMP29]] = xor <8 x i8> [[REVERSE]], [[VEC_PHI]]38; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP10]], 839; CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]40; CHECK-NEXT: br i1 [[TMP30]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]41; CHECK: [[MIDDLE_BLOCK]]:42; CHECK-NEXT: [[TMP31:%.*]] = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> [[TMP29]])43; CHECK-NEXT: br label %[[SCALAR_PH]]44; CHECK: [[SCALAR_PH]]:45; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]46; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i8 [ [[TMP31]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]47; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]48; CHECK: [[LOOP_HEADER]]:49; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]50; CHECK-NEXT: [[XOR_RED:%.*]] = phi i8 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[XOR_RED_NEXT:%.*]], %[[LOOP_LATCH]] ]51; CHECK-NEXT: [[IV_AND:%.*]] = and i64 [[IV]], 152; CHECK-NEXT: [[X_INC:%.*]] = add i64 [[IV_AND]], [[X]]53; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IV_AND]]54; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[X_INC]], 055; CHECK-NEXT: br i1 [[CMP]], label %[[EXIT_1:.*]], label %[[LOOP_LATCH]]56; CHECK: [[LOOP_LATCH]]:57; CHECK-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 158; CHECK-NEXT: [[XOR_RED_NEXT]] = xor i8 [[L]], [[XOR_RED]]59; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 160; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]61; CHECK-NEXT: br i1 [[EC]], label %[[EXIT_2:.*]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]62; CHECK: [[EXIT_1]]:63; CHECK-NEXT: [[X_INC_LCSSA:%.*]] = phi i64 [ [[X_INC]], %[[LOOP_HEADER]] ]64; CHECK-NEXT: ret i64 [[X_INC_LCSSA]]65; CHECK: [[EXIT_2]]:66; CHECK-NEXT: [[XOR_RED_NEXT_LCSSA:%.*]] = phi i8 [ [[XOR_RED_NEXT]], %[[LOOP_LATCH]] ]67; CHECK-NEXT: [[R:%.*]] = zext i8 [[XOR_RED_NEXT_LCSSA]] to i6468; CHECK-NEXT: ret i64 [[R]]69;70entry:71 br label %loop.header72 73loop.header:74 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]75 %xor.red = phi i8 [ 0, %entry ], [ %xor.red.next, %loop.latch ]76 %iv.and = and i64 %iv, 177 %x.inc = add i64 %iv.and, %x78 %gep.src = getelementptr i8, ptr %src, i64 %iv.and79 %cmp = icmp eq i64 %x.inc, 080 br i1 %cmp, label %exit.1, label %loop.latch81 82loop.latch:83 %l = load i8, ptr %gep.src, align 184 %xor.red.next = xor i8 %l, %xor.red85 %iv.next = add i64 %iv, 186 %ec = icmp eq i64 %iv.next, %N87 br i1 %ec, label %exit.2, label %loop.header88 89exit.1:90 ret i64 %x.inc91 92exit.2:93 %r = zext i8 %xor.red.next to i6494 ret i64 %r95}96;.97; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}98; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}99; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}100; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}101;.102