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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -passes=loop-vectorize -S %s | FileCheck %s3 4target triple = "x86_64"5 6define i8 @pr141968(i1 %cond, i8 %v) {7; CHECK-LABEL: define i8 @pr141968(8; CHECK-SAME: i1 [[COND:%.*]], i8 [[V:%.*]]) {9; CHECK-NEXT: [[ENTRY:.*:]]10; CHECK-NEXT: [[ZEXT_TRUE:%.*]] = zext i1 true to i1611; CHECK-NEXT: [[SEXT:%.*]] = sext i8 [[V]] to i1612; CHECK-NEXT: br label %[[VECTOR_PH:.*]]13; CHECK: [[VECTOR_PH]]:14; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i1> poison, i1 [[COND]], i64 015; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i1> [[BROADCAST_SPLATINSERT]], <16 x i1> poison, <16 x i32> zeroinitializer16; CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i1> [[BROADCAST_SPLAT]], splat (i1 true)17; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]18; CHECK: [[VECTOR_BODY]]:19; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_SDIV_CONTINUE30:.*]] ]20; CHECK-NEXT: [[TMP1:%.*]] = extractelement <16 x i1> [[TMP0]], i32 021; CHECK-NEXT: br i1 [[TMP1]], label %[[PRED_SDIV_IF:.*]], label %[[PRED_SDIV_CONTINUE:.*]]22; CHECK: [[PRED_SDIV_IF]]:23; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE]]24; CHECK: [[PRED_SDIV_CONTINUE]]:25; CHECK-NEXT: [[TMP2:%.*]] = extractelement <16 x i1> [[TMP0]], i32 126; CHECK-NEXT: br i1 [[TMP2]], label %[[PRED_SDIV_IF1:.*]], label %[[PRED_SDIV_CONTINUE2:.*]]27; CHECK: [[PRED_SDIV_IF1]]:28; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE2]]29; CHECK: [[PRED_SDIV_CONTINUE2]]:30; CHECK-NEXT: [[TMP3:%.*]] = extractelement <16 x i1> [[TMP0]], i32 231; CHECK-NEXT: br i1 [[TMP3]], label %[[PRED_SDIV_IF3:.*]], label %[[PRED_SDIV_CONTINUE4:.*]]32; CHECK: [[PRED_SDIV_IF3]]:33; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE4]]34; CHECK: [[PRED_SDIV_CONTINUE4]]:35; CHECK-NEXT: [[TMP4:%.*]] = extractelement <16 x i1> [[TMP0]], i32 336; CHECK-NEXT: br i1 [[TMP4]], label %[[PRED_SDIV_IF5:.*]], label %[[PRED_SDIV_CONTINUE6:.*]]37; CHECK: [[PRED_SDIV_IF5]]:38; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE6]]39; CHECK: [[PRED_SDIV_CONTINUE6]]:40; CHECK-NEXT: [[TMP5:%.*]] = extractelement <16 x i1> [[TMP0]], i32 441; CHECK-NEXT: br i1 [[TMP5]], label %[[PRED_SDIV_IF7:.*]], label %[[PRED_SDIV_CONTINUE8:.*]]42; CHECK: [[PRED_SDIV_IF7]]:43; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE8]]44; CHECK: [[PRED_SDIV_CONTINUE8]]:45; CHECK-NEXT: [[TMP6:%.*]] = extractelement <16 x i1> [[TMP0]], i32 546; CHECK-NEXT: br i1 [[TMP6]], label %[[PRED_SDIV_IF9:.*]], label %[[PRED_SDIV_CONTINUE10:.*]]47; CHECK: [[PRED_SDIV_IF9]]:48; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE10]]49; CHECK: [[PRED_SDIV_CONTINUE10]]:50; CHECK-NEXT: [[TMP7:%.*]] = extractelement <16 x i1> [[TMP0]], i32 651; CHECK-NEXT: br i1 [[TMP7]], label %[[PRED_SDIV_IF11:.*]], label %[[PRED_SDIV_CONTINUE12:.*]]52; CHECK: [[PRED_SDIV_IF11]]:53; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE12]]54; CHECK: [[PRED_SDIV_CONTINUE12]]:55; CHECK-NEXT: [[TMP8:%.*]] = extractelement <16 x i1> [[TMP0]], i32 756; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_SDIV_IF13:.*]], label %[[PRED_SDIV_CONTINUE14:.*]]57; CHECK: [[PRED_SDIV_IF13]]:58; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE14]]59; CHECK: [[PRED_SDIV_CONTINUE14]]:60; CHECK-NEXT: [[TMP9:%.*]] = extractelement <16 x i1> [[TMP0]], i32 861; CHECK-NEXT: br i1 [[TMP9]], label %[[PRED_SDIV_IF15:.*]], label %[[PRED_SDIV_CONTINUE16:.*]]62; CHECK: [[PRED_SDIV_IF15]]:63; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE16]]64; CHECK: [[PRED_SDIV_CONTINUE16]]:65; CHECK-NEXT: [[TMP10:%.*]] = extractelement <16 x i1> [[TMP0]], i32 966; CHECK-NEXT: br i1 [[TMP10]], label %[[PRED_SDIV_IF17:.*]], label %[[PRED_SDIV_CONTINUE18:.*]]67; CHECK: [[PRED_SDIV_IF17]]:68; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE18]]69; CHECK: [[PRED_SDIV_CONTINUE18]]:70; CHECK-NEXT: [[TMP11:%.*]] = extractelement <16 x i1> [[TMP0]], i32 1071; CHECK-NEXT: br i1 [[TMP11]], label %[[PRED_SDIV_IF19:.*]], label %[[PRED_SDIV_CONTINUE20:.*]]72; CHECK: [[PRED_SDIV_IF19]]:73; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE20]]74; CHECK: [[PRED_SDIV_CONTINUE20]]:75; CHECK-NEXT: [[TMP12:%.*]] = extractelement <16 x i1> [[TMP0]], i32 1176; CHECK-NEXT: br i1 [[TMP12]], label %[[PRED_SDIV_IF21:.*]], label %[[PRED_SDIV_CONTINUE22:.*]]77; CHECK: [[PRED_SDIV_IF21]]:78; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE22]]79; CHECK: [[PRED_SDIV_CONTINUE22]]:80; CHECK-NEXT: [[TMP13:%.*]] = extractelement <16 x i1> [[TMP0]], i32 1281; CHECK-NEXT: br i1 [[TMP13]], label %[[PRED_SDIV_IF23:.*]], label %[[PRED_SDIV_CONTINUE24:.*]]82; CHECK: [[PRED_SDIV_IF23]]:83; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE24]]84; CHECK: [[PRED_SDIV_CONTINUE24]]:85; CHECK-NEXT: [[TMP14:%.*]] = extractelement <16 x i1> [[TMP0]], i32 1386; CHECK-NEXT: br i1 [[TMP14]], label %[[PRED_SDIV_IF25:.*]], label %[[PRED_SDIV_CONTINUE26:.*]]87; CHECK: [[PRED_SDIV_IF25]]:88; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE26]]89; CHECK: [[PRED_SDIV_CONTINUE26]]:90; CHECK-NEXT: [[TMP15:%.*]] = extractelement <16 x i1> [[TMP0]], i32 1491; CHECK-NEXT: br i1 [[TMP15]], label %[[PRED_SDIV_IF27:.*]], label %[[PRED_SDIV_CONTINUE28:.*]]92; CHECK: [[PRED_SDIV_IF27]]:93; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE28]]94; CHECK: [[PRED_SDIV_CONTINUE28]]:95; CHECK-NEXT: [[TMP16:%.*]] = extractelement <16 x i1> [[TMP0]], i32 1596; CHECK-NEXT: br i1 [[TMP16]], label %[[PRED_SDIV_IF29:.*]], label %[[PRED_SDIV_CONTINUE30]]97; CHECK: [[PRED_SDIV_IF29]]:98; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE30]]99; CHECK: [[PRED_SDIV_CONTINUE30]]:100; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[COND]], i8 0, i8 [[V]]101; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16102; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT]], 256103; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]104; CHECK: [[MIDDLE_BLOCK]]:105; CHECK-NEXT: br label %[[EXIT:.*]]106; CHECK: [[EXIT]]:107; CHECK-NEXT: ret i8 [[PREDPHI]]108;109entry:110 %zext.true = zext i1 true to i16111 %sext = sext i8 %v to i16112 br label %loop.header113 114loop.header: ; preds = %loop.latch, %entry115 %iv = phi i8 [ %iv.next, %loop.latch ], [ 0, %entry ]116 br i1 %cond, label %loop.latch, label %cond.false117 118cond.false: ; preds = %loop.header119 %sdiv = sdiv i16 %sext, %zext.true120 %sdiv.trunc = trunc i16 %sdiv to i8121 br label %loop.latch122 123loop.latch: ; preds = %cond.false, %loop.header124 %ret = phi i8 [ %sdiv.trunc, %cond.false ], [ 0, %loop.header ]125 %iv.next = add i8 %iv, 1126 %exitcond = icmp eq i8 %iv.next, 0127 br i1 %exitcond, label %exit, label %loop.header128 129exit: ; preds = %loop.latch130 ret i8 %ret131}132