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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=loop-vectorize -mtriple=x86_64-unknown-linux-gnu -S < %s | FileCheck %s3 4; The test checks that there is no assert caused by issue described in PR354325 6target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"7target triple = "x86_64-unknown-linux-gnu"8 9@a = common local_unnamed_addr global [192 x [192 x i32]] zeroinitializer, align 1610 11define i32 @main(ptr %ptr) {12; CHECK-LABEL: @main(13; CHECK-NEXT: entry:14; CHECK-NEXT: [[I:%.*]] = alloca i32, align 415; CHECK-NEXT: [[S:%.*]] = alloca i16, align 216; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr nonnull [[I]])17; CHECK-NEXT: store i32 0, ptr [[I]], align 418; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr nonnull [[S]])19; CHECK-NEXT: [[CALL:%.*]] = call i32 (ptr, ...) @goo(ptr nonnull [[I]])20; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 421; CHECK-NEXT: [[STOREMERGE6:%.*]] = trunc i32 [[TMP0]] to i1622; CHECK-NEXT: store i16 [[STOREMERGE6]], ptr [[S]], align 223; CHECK-NEXT: [[CONV17:%.*]] = and i32 [[TMP0]], 6547224; CHECK-NEXT: [[CMP8:%.*]] = icmp eq i32 [[CONV17]], 025; CHECK-NEXT: br i1 [[CMP8]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END12:%.*]]26; CHECK: for.body.lr.ph:27; CHECK-NEXT: br label [[FOR_BODY:%.*]]28; CHECK: for.body:29; CHECK-NEXT: [[STOREMERGE_IN9:%.*]] = phi i32 [ [[TMP0]], [[FOR_BODY_LR_PH]] ], [ [[ADD:%.*]], [[FOR_INC9:%.*]] ]30; CHECK-NEXT: [[CONV52:%.*]] = and i32 [[STOREMERGE_IN9]], 25531; CHECK-NEXT: [[CMP63:%.*]] = icmp ult i32 [[TMP0]], [[CONV52]]32; CHECK-NEXT: br i1 [[CMP63]], label [[FOR_BODY8_LR_PH:%.*]], label [[FOR_INC9]]33; CHECK: for.body8.lr.ph:34; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[STOREMERGE_IN9]] to i835; CHECK-NEXT: [[DOTPROMOTED:%.*]] = load i32, ptr @a, align 1636; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[CONV3]], -137; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i3238; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], 139; CHECK-NEXT: [[UMIN1:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP0]], i32 [[TMP2]])40; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP3]], [[UMIN1]]41; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP4]], 2442; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]43; CHECK: vector.scevcheck:44; CHECK-NEXT: [[TMP5:%.*]] = add i8 [[CONV3]], -145; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i3246; CHECK-NEXT: [[UMIN:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP0]], i32 [[TMP6]])47; CHECK-NEXT: [[TMP7:%.*]] = sub i32 [[TMP6]], [[UMIN]]48; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i849; CHECK-NEXT: [[TMP9:%.*]] = sub i8 [[TMP5]], [[TMP8]]50; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i8 [[TMP9]], [[TMP5]]51; CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i32 [[TMP7]], 25552; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP10]], [[TMP12]]53; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[DOTPROMOTED]], 154; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP14]], [[TMP7]]55; CHECK-NEXT: [[TMP16:%.*]] = icmp slt i32 [[TMP15]], [[TMP14]]56; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP13]], [[TMP16]]57; CHECK-NEXT: br i1 [[TMP17]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]58; CHECK: vector.ph:59; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP4]], 860; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP4]], [[N_MOD_VF]]61; CHECK-NEXT: [[IND_END:%.*]] = add i32 [[DOTPROMOTED]], [[N_VEC]]62; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i32 [[N_VEC]] to i863; CHECK-NEXT: [[IND_END2:%.*]] = sub i8 [[CONV3]], [[DOTCAST]]64; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]65; CHECK: vector.body:66; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]67; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i32 [[DOTPROMOTED]], [[INDEX]]68; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[OFFSET_IDX]], 169; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[PTR:%.*]], i32 [[TMP20]]70; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i32, ptr [[TMP22]], i64 471; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP22]], align 472; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP25]], align 473; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 874; CHECK-NEXT: [[TMP26:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]75; CHECK-NEXT: br i1 [[TMP26]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]76; CHECK: middle.block:77; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP4]], [[N_VEC]]78; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_COND4_FOR_INC9_CRIT_EDGE:%.*]], label [[SCALAR_PH]]79; CHECK: scalar.ph:80; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[DOTPROMOTED]], [[FOR_BODY8_LR_PH]] ], [ [[DOTPROMOTED]], [[VECTOR_SCEVCHECK]] ]81; CHECK-NEXT: [[BC_RESUME_VAL3:%.*]] = phi i8 [ [[IND_END2]], [[MIDDLE_BLOCK]] ], [ [[CONV3]], [[FOR_BODY8_LR_PH]] ], [ [[CONV3]], [[VECTOR_SCEVCHECK]] ]82; CHECK-NEXT: br label [[FOR_BODY8:%.*]]83; CHECK: for.body8:84; CHECK-NEXT: [[INC5:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC:%.*]], [[FOR_BODY8]] ]85; CHECK-NEXT: [[C_04:%.*]] = phi i8 [ [[BC_RESUME_VAL3]], [[SCALAR_PH]] ], [ [[DEC:%.*]], [[FOR_BODY8]] ]86; CHECK-NEXT: [[INC]] = add i32 [[INC5]], 187; CHECK-NEXT: [[DEC]] = add i8 [[C_04]], -188; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i32 [[INC]]89; CHECK-NEXT: store i32 0, ptr [[GEP]], align 490; CHECK-NEXT: [[CONV5:%.*]] = zext i8 [[DEC]] to i3291; CHECK-NEXT: [[CMP6:%.*]] = icmp ult i32 [[TMP0]], [[CONV5]]92; CHECK-NEXT: br i1 [[CMP6]], label [[FOR_BODY8]], label [[FOR_COND4_FOR_INC9_CRIT_EDGE]], !llvm.loop [[LOOP3:![0-9]+]]93; CHECK: for.cond4.for.inc9_crit_edge:94; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[FOR_BODY8]] ], [ [[IND_END]], [[MIDDLE_BLOCK]] ]95; CHECK-NEXT: store i32 [[INC_LCSSA]], ptr @a, align 1696; CHECK-NEXT: br label [[FOR_INC9]]97; CHECK: for.inc9:98; CHECK-NEXT: [[CONV10:%.*]] = and i32 [[STOREMERGE_IN9]], 6553599; CHECK-NEXT: [[ADD]] = add nuw nsw i32 [[CONV10]], 1100; CHECK-NEXT: [[CONV1:%.*]] = and i32 [[ADD]], 65472101; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[CONV1]], 0102; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_FOR_END12_CRIT_EDGE:%.*]]103; CHECK: for.cond.for.end12_crit_edge:104; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_INC9]] ]105; CHECK-NEXT: [[STOREMERGE:%.*]] = trunc i32 [[ADD_LCSSA]] to i16106; CHECK-NEXT: store i16 [[STOREMERGE]], ptr [[S]], align 2107; CHECK-NEXT: br label [[FOR_END12]]108; CHECK: for.end12:109; CHECK-NEXT: [[CALL13:%.*]] = call i32 (ptr, ...) @foo(ptr nonnull [[S]])110; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr nonnull [[S]])111; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr nonnull [[I]])112; CHECK-NEXT: ret i32 0113;114entry:115 %i = alloca i32, align 4116 %s = alloca i16, align 2117 call void @llvm.lifetime.start.p0(ptr nonnull %i) #3118 store i32 0, ptr %i, align 4119 call void @llvm.lifetime.start.p0(ptr nonnull %s) #3120 %call = call i32 (ptr, ...) @goo(ptr nonnull %i) #3121 %0 = load i32, ptr %i, align 4122 %storemerge6 = trunc i32 %0 to i16123 store i16 %storemerge6, ptr %s, align 2124 %conv17 = and i32 %0, 65472125 %cmp8 = icmp eq i32 %conv17, 0126 br i1 %cmp8, label %for.body.lr.ph, label %for.end12127 128for.body.lr.ph: ; preds = %entry129 br label %for.body130 131for.body: ; preds = %for.body.lr.ph, %for.inc9132 %storemerge.in9 = phi i32 [ %0, %for.body.lr.ph ], [ %add, %for.inc9 ]133 %conv52 = and i32 %storemerge.in9, 255134 %cmp63 = icmp ult i32 %0, %conv52135 br i1 %cmp63, label %for.body8.lr.ph, label %for.inc9136 137for.body8.lr.ph: ; preds = %for.body138 %conv3 = trunc i32 %storemerge.in9 to i8139 %.promoted = load i32, ptr @a, align 16140 br label %for.body8141 142for.body8: ; preds = %for.body8.lr.ph, %for.body8143 %inc5 = phi i32 [ %.promoted, %for.body8.lr.ph ], [ %inc, %for.body8 ]144 %c.04 = phi i8 [ %conv3, %for.body8.lr.ph ], [ %dec, %for.body8 ]145 %inc = add i32 %inc5, 1146 %dec = add i8 %c.04, -1147 %gep = getelementptr inbounds i32, ptr %ptr, i32 %inc148 store i32 0, ptr %gep149 %conv5 = zext i8 %dec to i32150 %cmp6 = icmp ult i32 %0, %conv5151 br i1 %cmp6, label %for.body8, label %for.cond4.for.inc9_crit_edge152 153for.cond4.for.inc9_crit_edge: ; preds = %for.body8154 %inc.lcssa = phi i32 [ %inc, %for.body8 ]155 store i32 %inc.lcssa, ptr @a, align 16156 br label %for.inc9157 158for.inc9: ; preds = %for.cond4.for.inc9_crit_edge, %for.body159 %conv10 = and i32 %storemerge.in9, 65535160 %add = add nuw nsw i32 %conv10, 1161 %conv1 = and i32 %add, 65472162 %cmp = icmp eq i32 %conv1, 0163 br i1 %cmp, label %for.body, label %for.cond.for.end12_crit_edge164 165for.cond.for.end12_crit_edge: ; preds = %for.inc9166 %add.lcssa = phi i32 [ %add, %for.inc9 ]167 %storemerge = trunc i32 %add.lcssa to i16168 store i16 %storemerge, ptr %s, align 2169 br label %for.end12170 171for.end12: ; preds = %for.cond.for.end12_crit_edge, %entry172 %call13 = call i32 (ptr, ...) @foo(ptr nonnull %s) #3173 call void @llvm.lifetime.end.p0(ptr nonnull %s) #3174 call void @llvm.lifetime.end.p0(ptr nonnull %i) #3175 ret i32 0176}177 178; Function Attrs: argmemonly nounwind179declare void @llvm.lifetime.start.p0(ptr nocapture) #1180 181declare i32 @goo(...) local_unnamed_addr #2182 183declare i32 @foo(...) local_unnamed_addr #2184 185; Function Attrs: argmemonly nounwind186declare void @llvm.lifetime.end.p0(ptr nocapture) #1187