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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 < %s | FileCheck %s3 4target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1"5 6define void @foo(ptr %ptr, ptr %ptr.2) {7; CHECK-LABEL: @foo(8; CHECK-NEXT: entry:9; CHECK-NEXT: br label [[VECTOR_MEMCHECK:%.*]]10; CHECK: vector.memcheck:11; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[PTR_2:%.*]], i64 412; CHECK-NEXT: [[UGLYGEP1:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 64013; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[PTR_2]], [[UGLYGEP1]]14; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[PTR]], [[UGLYGEP]]15; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]16; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]17; CHECK: vector.ph:18; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]19; CHECK: vector.body:20; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]21; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 2, i64 3, i64 4, i64 5>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]22; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 2, [[INDEX]]23; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[OFFSET_IDX]] to i3224; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 025; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP0]], 126; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP0]], 227; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP0]], 328; CHECK-NEXT: store i32 [[TMP4]], ptr [[PTR_2]], align 4, !alias.scope [[META0:![0-9]+]], !noalias [[META3:![0-9]+]]29; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[PTR]], i64 [[INDEX]]30; CHECK-NEXT: store <4 x i64> [[VEC_IND]], ptr [[TMP6]], align 8, !alias.scope [[META3]]31; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 432; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)33; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 8034; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]35; CHECK: middle.block:36; CHECK-NEXT: br label [[EXIT:%.*]]37; CHECK: scalar.ph:38; CHECK-NEXT: br label [[LOOP:%.*]]39; CHECK: loop:40; CHECK-NEXT: [[CAN_IV:%.*]] = phi i64 [ 0, [[SCALAR_PH]] ], [ [[CAN_IV_NEXT:%.*]], [[LOOP]] ]41; CHECK-NEXT: [[TMP9:%.*]] = phi i64 [ 2, [[SCALAR_PH]] ], [ [[TMP12:%.*]], [[LOOP]] ]42; CHECK-NEXT: [[TMP10:%.*]] = and i64 [[TMP9]], 429496729543; CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP9]] to i3244; CHECK-NEXT: store i32 [[TMP11]], ptr [[PTR_2]], align 445; CHECK-NEXT: [[GEP_PTR:%.*]] = getelementptr inbounds i64, ptr [[PTR]], i64 [[CAN_IV]]46; CHECK-NEXT: store i64 [[TMP9]], ptr [[GEP_PTR]], align 847; CHECK-NEXT: [[TMP12]] = add nuw nsw i64 [[TMP10]], 148; CHECK-NEXT: [[TMP13:%.*]] = icmp sgt i32 [[TMP11]], 8049; CHECK-NEXT: [[CAN_IV_NEXT]] = add nuw nsw i64 [[CAN_IV]], 150; CHECK-NEXT: br i1 [[TMP13]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]51; CHECK: exit:52; CHECK-NEXT: ret void53;54entry:55 br label %loop56 57loop:58 %can.iv = phi i64 [ 0, %entry ], [ %can.iv.next, %loop ]59 %0 = phi i64 [ 2, %entry ], [ %3, %loop ]60 %1 = and i64 %0, 429496729561 %2 = trunc i64 %0 to i3262 store i32 %2, ptr %ptr.263 %gep.ptr = getelementptr inbounds i64, ptr %ptr, i64 %can.iv64 store i64 %0, ptr %gep.ptr65 %3 = add nuw nsw i64 %1, 166 %4 = icmp sgt i32 %2, 8067 %can.iv.next = add nuw nsw i64 %can.iv, 168 br i1 %4, label %exit, label %loop69 70exit:71 ret void72}73