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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -mtriple=x86_64-apple-macosx -mcpu=skylake-avx512 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=COST %s3; RUN: opt -p loop-vectorize -mtriple=x86_64-apple-macosx -mcpu=skylake-avx512 -force-vector-width=4 -force-vector-interleave=2 -S %s | FileCheck --check-prefixes=FORCED %s4 5define void @switch_default_to_latch_common_dest(ptr %start, ptr %end) {6; COST-LABEL: define void @switch_default_to_latch_common_dest(7; COST-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0:[0-9]+]] {8; COST-NEXT: [[ENTRY:.*]]:9; COST-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i6410; COST-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i6411; COST-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -812; COST-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]13; COST-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 314; COST-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 115; COST-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 416; COST-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]17; COST: [[VECTOR_PH]]:18; COST-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 419; COST-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]20; COST-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 821; COST-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]22; COST-NEXT: br label %[[VECTOR_BODY:.*]]23; COST: [[VECTOR_BODY]]:24; COST-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]25; COST-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 826; COST-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]]27; COST-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[NEXT_GEP]], align 128; COST-NEXT: [[TMP7:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 -12)29; COST-NEXT: [[TMP8:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 13)30; COST-NEXT: [[TMP10:%.*]] = or <4 x i1> [[TMP7]], [[TMP8]]31; COST-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP10]])32; COST-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 433; COST-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]34; COST-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]35; COST: [[MIDDLE_BLOCK]]:36; COST-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]37; COST-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]38; COST: [[SCALAR_PH]]:39; COST-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]40; COST-NEXT: br label %[[LOOP_HEADER:.*]]41; COST: [[LOOP_HEADER]]:42; COST-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]43; COST-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 144; COST-NEXT: switch i64 [[L]], label %[[LOOP_LATCH]] [45; COST-NEXT: i64 -12, label %[[IF_THEN:.*]]46; COST-NEXT: i64 13, label %[[IF_THEN]]47; COST-NEXT: ]48; COST: [[IF_THEN]]:49; COST-NEXT: store i64 42, ptr [[PTR_IV]], align 150; COST-NEXT: br label %[[LOOP_LATCH]]51; COST: [[LOOP_LATCH]]:52; COST-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 153; COST-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]54; COST-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]55; COST: [[EXIT]]:56; COST-NEXT: ret void57;58; FORCED-LABEL: define void @switch_default_to_latch_common_dest(59; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0:[0-9]+]] {60; FORCED-NEXT: [[ENTRY:.*]]:61; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i6462; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i6463; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -864; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]65; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 366; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 167; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 868; FORCED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]69; FORCED: [[VECTOR_PH]]:70; FORCED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 871; FORCED-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]72; FORCED-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 873; FORCED-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]74; FORCED-NEXT: br label %[[VECTOR_BODY:.*]]75; FORCED: [[VECTOR_BODY]]:76; FORCED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]77; FORCED-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 878; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]]79; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i64 480; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[NEXT_GEP]], align 181; FORCED-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP8]], align 182; FORCED-NEXT: [[TMP9:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 -12)83; FORCED-NEXT: [[TMP10:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 -12)84; FORCED-NEXT: [[TMP11:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 13)85; FORCED-NEXT: [[TMP12:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 13)86; FORCED-NEXT: [[TMP15:%.*]] = or <4 x i1> [[TMP9]], [[TMP11]]87; FORCED-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP10]], [[TMP12]]88; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP15]])89; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[TMP8]], <4 x i1> [[TMP16]])90; FORCED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 891; FORCED-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]92; FORCED-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]93; FORCED: [[MIDDLE_BLOCK]]:94; FORCED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]95; FORCED-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]96; FORCED: [[SCALAR_PH]]:97; FORCED-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]98; FORCED-NEXT: br label %[[LOOP_HEADER:.*]]99; FORCED: [[LOOP_HEADER]]:100; FORCED-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]101; FORCED-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 1102; FORCED-NEXT: switch i64 [[L]], label %[[LOOP_LATCH]] [103; FORCED-NEXT: i64 -12, label %[[IF_THEN:.*]]104; FORCED-NEXT: i64 13, label %[[IF_THEN]]105; FORCED-NEXT: ]106; FORCED: [[IF_THEN]]:107; FORCED-NEXT: store i64 42, ptr [[PTR_IV]], align 1108; FORCED-NEXT: br label %[[LOOP_LATCH]]109; FORCED: [[LOOP_LATCH]]:110; FORCED-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 1111; FORCED-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]112; FORCED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]113; FORCED: [[EXIT]]:114; FORCED-NEXT: ret void115;116entry:117 br label %loop.header118 119loop.header:120 %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]121 %l = load i64, ptr %ptr.iv, align 1122 switch i64 %l, label %loop.latch [123 i64 -12, label %if.then124 i64 13, label %if.then125 ]126 127if.then:128 store i64 42, ptr %ptr.iv, align 1129 br label %loop.latch130 131loop.latch:132 %ptr.iv.next = getelementptr inbounds i64, ptr %ptr.iv, i64 1133 %ec = icmp eq ptr %ptr.iv.next, %end134 br i1 %ec, label %exit, label %loop.header135 136exit:137 ret void138}139 140define void @switch_default_to_latch_common_dest_using_branches(ptr %start, ptr %end) {141; COST-LABEL: define void @switch_default_to_latch_common_dest_using_branches(142; COST-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {143; COST-NEXT: [[ENTRY:.*]]:144; COST-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64145; COST-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64146; COST-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8147; COST-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]148; COST-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3149; COST-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1150; COST-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4151; COST-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]152; COST: [[VECTOR_PH]]:153; COST-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 4154; COST-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]155; COST-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 8156; COST-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]157; COST-NEXT: br label %[[VECTOR_BODY:.*]]158; COST: [[VECTOR_BODY]]:159; COST-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]160; COST-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8161; COST-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]]162; COST-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[NEXT_GEP]], align 1163; COST-NEXT: [[TMP7:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 -12)164; COST-NEXT: [[TMP8:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 13)165; COST-NEXT: [[TMP9:%.*]] = xor <4 x i1> [[TMP7]], splat (i1 true)166; COST-NEXT: [[TMP10:%.*]] = select <4 x i1> [[TMP9]], <4 x i1> [[TMP8]], <4 x i1> zeroinitializer167; COST-NEXT: [[TMP11:%.*]] = or <4 x i1> [[TMP10]], [[TMP7]]168; COST-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP11]])169; COST-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4170; COST-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]171; COST-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]172; COST: [[MIDDLE_BLOCK]]:173; COST-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]174; COST-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]175; COST: [[SCALAR_PH]]:176; COST-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]177; COST-NEXT: br label %[[LOOP_HEADER:.*]]178; COST: [[LOOP_HEADER]]:179; COST-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]180; COST-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 1181; COST-NEXT: [[EQ_1:%.*]] = icmp eq i64 [[L]], -12182; COST-NEXT: [[EQ_2:%.*]] = icmp eq i64 [[L]], 13183; COST-NEXT: br i1 [[EQ_1]], label %[[IF_THEN:.*]], label %[[ELSE:.*]]184; COST: [[IF_THEN]]:185; COST-NEXT: store i64 42, ptr [[PTR_IV]], align 1186; COST-NEXT: br label %[[LOOP_LATCH]]187; COST: [[ELSE]]:188; COST-NEXT: br i1 [[EQ_2]], label %[[IF_THEN]], label %[[LOOP_LATCH]]189; COST: [[LOOP_LATCH]]:190; COST-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 1191; COST-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]192; COST-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP5:![0-9]+]]193; COST: [[EXIT]]:194; COST-NEXT: ret void195;196; FORCED-LABEL: define void @switch_default_to_latch_common_dest_using_branches(197; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {198; FORCED-NEXT: [[ENTRY:.*]]:199; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64200; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64201; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8202; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]203; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3204; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1205; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8206; FORCED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]207; FORCED: [[VECTOR_PH]]:208; FORCED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 8209; FORCED-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]210; FORCED-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 8211; FORCED-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]212; FORCED-NEXT: br label %[[VECTOR_BODY:.*]]213; FORCED: [[VECTOR_BODY]]:214; FORCED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]215; FORCED-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8216; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]]217; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i64 4218; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[NEXT_GEP]], align 1219; FORCED-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP8]], align 1220; FORCED-NEXT: [[TMP9:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 -12)221; FORCED-NEXT: [[TMP10:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 -12)222; FORCED-NEXT: [[TMP11:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 13)223; FORCED-NEXT: [[TMP12:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 13)224; FORCED-NEXT: [[TMP13:%.*]] = xor <4 x i1> [[TMP9]], splat (i1 true)225; FORCED-NEXT: [[TMP14:%.*]] = xor <4 x i1> [[TMP10]], splat (i1 true)226; FORCED-NEXT: [[TMP15:%.*]] = select <4 x i1> [[TMP13]], <4 x i1> [[TMP11]], <4 x i1> zeroinitializer227; FORCED-NEXT: [[TMP16:%.*]] = select <4 x i1> [[TMP14]], <4 x i1> [[TMP12]], <4 x i1> zeroinitializer228; FORCED-NEXT: [[TMP17:%.*]] = or <4 x i1> [[TMP15]], [[TMP9]]229; FORCED-NEXT: [[TMP18:%.*]] = or <4 x i1> [[TMP16]], [[TMP10]]230; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP17]])231; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[TMP8]], <4 x i1> [[TMP18]])232; FORCED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8233; FORCED-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]234; FORCED-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]235; FORCED: [[MIDDLE_BLOCK]]:236; FORCED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]237; FORCED-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]238; FORCED: [[SCALAR_PH]]:239; FORCED-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]240; FORCED-NEXT: br label %[[LOOP_HEADER:.*]]241; FORCED: [[LOOP_HEADER]]:242; FORCED-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]243; FORCED-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 1244; FORCED-NEXT: [[EQ_1:%.*]] = icmp eq i64 [[L]], -12245; FORCED-NEXT: [[EQ_2:%.*]] = icmp eq i64 [[L]], 13246; FORCED-NEXT: br i1 [[EQ_1]], label %[[IF_THEN:.*]], label %[[ELSE:.*]]247; FORCED: [[IF_THEN]]:248; FORCED-NEXT: store i64 42, ptr [[PTR_IV]], align 1249; FORCED-NEXT: br label %[[LOOP_LATCH]]250; FORCED: [[ELSE]]:251; FORCED-NEXT: br i1 [[EQ_2]], label %[[IF_THEN]], label %[[LOOP_LATCH]]252; FORCED: [[LOOP_LATCH]]:253; FORCED-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 1254; FORCED-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]255; FORCED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP5:![0-9]+]]256; FORCED: [[EXIT]]:257; FORCED-NEXT: ret void258;259entry:260 br label %loop.header261 262loop.header:263 %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]264 %l = load i64, ptr %ptr.iv, align 1265 %eq.1 = icmp eq i64 %l, -12266 %eq.2 = icmp eq i64 %l, 13267 br i1 %eq.1, label %if.then, label %else268 269if.then:270 store i64 42, ptr %ptr.iv, align 1271 br label %loop.latch272 273else:274 br i1 %eq.2, label %if.then, label %loop.latch275 276loop.latch:277 %ptr.iv.next = getelementptr inbounds i64, ptr %ptr.iv, i64 1278 %ec = icmp eq ptr %ptr.iv.next, %end279 br i1 %ec, label %exit, label %loop.header280 281exit:282 ret void283}284 285; TODO: Instead of using masked stores, the store can be sunk, executed286; unconditionally and fed by selects.287define void @switch_all_dests_distinct(ptr %start, ptr %end) {288; COST-LABEL: define void @switch_all_dests_distinct(289; COST-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {290; COST-NEXT: [[ENTRY:.*]]:291; COST-NEXT: br label %[[LOOP_HEADER:.*]]292; COST: [[LOOP_HEADER]]:293; COST-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[START]], %[[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]294; COST-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 1295; COST-NEXT: switch i64 [[L]], label %[[DEFAULT:.*]] [296; COST-NEXT: i64 -12, label %[[IF_THEN_1:.*]]297; COST-NEXT: i64 13, label %[[IF_THEN_2:.*]]298; COST-NEXT: i64 0, label %[[IF_THEN_3:.*]]299; COST-NEXT: ]300; COST: [[IF_THEN_1]]:301; COST-NEXT: store i64 42, ptr [[PTR_IV]], align 1302; COST-NEXT: br label %[[LOOP_LATCH]]303; COST: [[IF_THEN_2]]:304; COST-NEXT: store i64 0, ptr [[PTR_IV]], align 1305; COST-NEXT: br label %[[LOOP_LATCH]]306; COST: [[IF_THEN_3]]:307; COST-NEXT: store i64 1, ptr [[PTR_IV]], align 1308; COST-NEXT: br label %[[LOOP_LATCH]]309; COST: [[DEFAULT]]:310; COST-NEXT: store i64 2, ptr [[PTR_IV]], align 1311; COST-NEXT: br label %[[LOOP_LATCH]]312; COST: [[LOOP_LATCH]]:313; COST-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 1314; COST-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]315; COST-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]316; COST: [[EXIT]]:317; COST-NEXT: ret void318;319; FORCED-LABEL: define void @switch_all_dests_distinct(320; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {321; FORCED-NEXT: [[ENTRY:.*]]:322; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64323; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64324; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8325; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]326; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3327; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1328; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8329; FORCED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]330; FORCED: [[VECTOR_PH]]:331; FORCED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 8332; FORCED-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]333; FORCED-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 8334; FORCED-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]335; FORCED-NEXT: br label %[[VECTOR_BODY:.*]]336; FORCED: [[VECTOR_BODY]]:337; FORCED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]338; FORCED-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8339; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]]340; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i64 4341; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[NEXT_GEP]], align 1342; FORCED-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP8]], align 1343; FORCED-NEXT: [[TMP9:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 -12)344; FORCED-NEXT: [[TMP10:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 -12)345; FORCED-NEXT: [[TMP11:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 13)346; FORCED-NEXT: [[TMP12:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 13)347; FORCED-NEXT: [[TMP13:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], zeroinitializer348; FORCED-NEXT: [[TMP14:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], zeroinitializer349; FORCED-NEXT: [[TMP15:%.*]] = or <4 x i1> [[TMP9]], [[TMP11]]350; FORCED-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP10]], [[TMP12]]351; FORCED-NEXT: [[TMP17:%.*]] = or <4 x i1> [[TMP15]], [[TMP13]]352; FORCED-NEXT: [[TMP18:%.*]] = or <4 x i1> [[TMP16]], [[TMP14]]353; FORCED-NEXT: [[TMP19:%.*]] = xor <4 x i1> [[TMP17]], splat (i1 true)354; FORCED-NEXT: [[TMP20:%.*]] = xor <4 x i1> [[TMP18]], splat (i1 true)355; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 1), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP13]])356; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 1), ptr align 1 [[TMP8]], <4 x i1> [[TMP14]])357; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP11]])358; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[TMP8]], <4 x i1> [[TMP12]])359; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP9]])360; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[TMP8]], <4 x i1> [[TMP10]])361; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 2), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP19]])362; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 2), ptr align 1 [[TMP8]], <4 x i1> [[TMP20]])363; FORCED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8364; FORCED-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]365; FORCED-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]366; FORCED: [[MIDDLE_BLOCK]]:367; FORCED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]368; FORCED-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]369; FORCED: [[SCALAR_PH]]:370; FORCED-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]371; FORCED-NEXT: br label %[[LOOP_HEADER:.*]]372; FORCED: [[LOOP_HEADER]]:373; FORCED-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]374; FORCED-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 1375; FORCED-NEXT: switch i64 [[L]], label %[[DEFAULT:.*]] [376; FORCED-NEXT: i64 -12, label %[[IF_THEN_1:.*]]377; FORCED-NEXT: i64 13, label %[[IF_THEN_2:.*]]378; FORCED-NEXT: i64 0, label %[[IF_THEN_3:.*]]379; FORCED-NEXT: ]380; FORCED: [[IF_THEN_1]]:381; FORCED-NEXT: store i64 42, ptr [[PTR_IV]], align 1382; FORCED-NEXT: br label %[[LOOP_LATCH]]383; FORCED: [[IF_THEN_2]]:384; FORCED-NEXT: store i64 0, ptr [[PTR_IV]], align 1385; FORCED-NEXT: br label %[[LOOP_LATCH]]386; FORCED: [[IF_THEN_3]]:387; FORCED-NEXT: store i64 1, ptr [[PTR_IV]], align 1388; FORCED-NEXT: br label %[[LOOP_LATCH]]389; FORCED: [[DEFAULT]]:390; FORCED-NEXT: store i64 2, ptr [[PTR_IV]], align 1391; FORCED-NEXT: br label %[[LOOP_LATCH]]392; FORCED: [[LOOP_LATCH]]:393; FORCED-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 1394; FORCED-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]395; FORCED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP7:![0-9]+]]396; FORCED: [[EXIT]]:397; FORCED-NEXT: ret void398;399entry:400 br label %loop.header401 402loop.header:403 %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]404 %l = load i64, ptr %ptr.iv, align 1405 switch i64 %l, label %default [406 i64 -12, label %if.then.1407 i64 13, label %if.then.2408 i64 0, label %if.then.3409 ]410 411if.then.1:412 store i64 42, ptr %ptr.iv, align 1413 br label %loop.latch414 415if.then.2:416 store i64 0, ptr %ptr.iv, align 1417 br label %loop.latch418 419if.then.3:420 store i64 1, ptr %ptr.iv, align 1421 br label %loop.latch422 423default:424 store i64 2, ptr %ptr.iv, align 1425 br label %loop.latch426 427loop.latch:428 %ptr.iv.next = getelementptr inbounds i64, ptr %ptr.iv, i64 1429 %ec = icmp eq ptr %ptr.iv.next, %end430 br i1 %ec, label %exit, label %loop.header431 432exit:433 ret void434}435 436define void @switch_all_dests_distinct_variant_using_branches(ptr %start, ptr %end) {437; COST-LABEL: define void @switch_all_dests_distinct_variant_using_branches(438; COST-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {439; COST-NEXT: [[ENTRY:.*]]:440; COST-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64441; COST-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64442; COST-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8443; COST-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]444; COST-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3445; COST-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1446; COST-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4447; COST-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]448; COST: [[VECTOR_PH]]:449; COST-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 4450; COST-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]451; COST-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 8452; COST-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]453; COST-NEXT: br label %[[VECTOR_BODY:.*]]454; COST: [[VECTOR_BODY]]:455; COST-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]456; COST-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8457; COST-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]]458; COST-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[NEXT_GEP]], align 1459; COST-NEXT: [[TMP7:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 -12)460; COST-NEXT: [[TMP8:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 13)461; COST-NEXT: [[TMP9:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], zeroinitializer462; COST-NEXT: [[TMP10:%.*]] = xor <4 x i1> [[TMP7]], splat (i1 true)463; COST-NEXT: [[TMP11:%.*]] = xor <4 x i1> [[TMP8]], splat (i1 true)464; COST-NEXT: [[TMP12:%.*]] = select <4 x i1> [[TMP11]], <4 x i1> [[TMP9]], <4 x i1> zeroinitializer465; COST-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP10]], <4 x i1> [[TMP12]], <4 x i1> zeroinitializer466; COST-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 1), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP13]])467; COST-NEXT: [[TMP14:%.*]] = select <4 x i1> [[TMP10]], <4 x i1> [[TMP8]], <4 x i1> zeroinitializer468; COST-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP14]])469; COST-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP7]])470; COST-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4471; COST-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]472; COST-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]473; COST: [[MIDDLE_BLOCK]]:474; COST-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]475; COST-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]476; COST: [[SCALAR_PH]]:477; COST-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]478; COST-NEXT: br label %[[LOOP_HEADER:.*]]479; COST: [[LOOP_HEADER]]:480; COST-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]481; COST-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 1482; COST-NEXT: [[EQ_0:%.*]] = icmp eq i64 [[L]], -12483; COST-NEXT: [[EQ_1:%.*]] = icmp eq i64 [[L]], 13484; COST-NEXT: [[EQ_2:%.*]] = icmp eq i64 [[L]], 0485; COST-NEXT: br i1 [[EQ_0]], label %[[IF_THEN_1:.*]], label %[[ELSE_1:.*]]486; COST: [[ELSE_1]]:487; COST-NEXT: br i1 [[EQ_1]], label %[[IF_THEN_2:.*]], label %[[ELSE_2:.*]]488; COST: [[ELSE_2]]:489; COST-NEXT: br i1 [[EQ_2]], label %[[IF_THEN_3:.*]], label %[[LOOP_LATCH]]490; COST: [[IF_THEN_1]]:491; COST-NEXT: store i64 42, ptr [[PTR_IV]], align 1492; COST-NEXT: br label %[[LOOP_LATCH]]493; COST: [[IF_THEN_2]]:494; COST-NEXT: store i64 0, ptr [[PTR_IV]], align 1495; COST-NEXT: br label %[[LOOP_LATCH]]496; COST: [[IF_THEN_3]]:497; COST-NEXT: store i64 1, ptr [[PTR_IV]], align 1498; COST-NEXT: br label %[[LOOP_LATCH]]499; COST: [[DEFAULT:.*:]]500; COST-NEXT: store i64 2, ptr poison, align 1501; COST-NEXT: unreachable502; COST: [[LOOP_LATCH]]:503; COST-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 1504; COST-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]505; COST-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP7:![0-9]+]]506; COST: [[EXIT]]:507; COST-NEXT: ret void508;509; FORCED-LABEL: define void @switch_all_dests_distinct_variant_using_branches(510; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {511; FORCED-NEXT: [[ENTRY:.*]]:512; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64513; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64514; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8515; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]516; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3517; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1518; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8519; FORCED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]520; FORCED: [[VECTOR_PH]]:521; FORCED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 8522; FORCED-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]523; FORCED-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 8524; FORCED-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]525; FORCED-NEXT: br label %[[VECTOR_BODY:.*]]526; FORCED: [[VECTOR_BODY]]:527; FORCED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]528; FORCED-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8529; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]]530; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i64 4531; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[NEXT_GEP]], align 1532; FORCED-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP8]], align 1533; FORCED-NEXT: [[TMP9:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 -12)534; FORCED-NEXT: [[TMP10:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 -12)535; FORCED-NEXT: [[TMP11:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 13)536; FORCED-NEXT: [[TMP12:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 13)537; FORCED-NEXT: [[TMP13:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], zeroinitializer538; FORCED-NEXT: [[TMP14:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], zeroinitializer539; FORCED-NEXT: [[TMP15:%.*]] = xor <4 x i1> [[TMP9]], splat (i1 true)540; FORCED-NEXT: [[TMP16:%.*]] = xor <4 x i1> [[TMP10]], splat (i1 true)541; FORCED-NEXT: [[TMP17:%.*]] = xor <4 x i1> [[TMP11]], splat (i1 true)542; FORCED-NEXT: [[TMP18:%.*]] = xor <4 x i1> [[TMP12]], splat (i1 true)543; FORCED-NEXT: [[TMP19:%.*]] = select <4 x i1> [[TMP17]], <4 x i1> [[TMP13]], <4 x i1> zeroinitializer544; FORCED-NEXT: [[TMP20:%.*]] = select <4 x i1> [[TMP18]], <4 x i1> [[TMP14]], <4 x i1> zeroinitializer545; FORCED-NEXT: [[TMP21:%.*]] = select <4 x i1> [[TMP15]], <4 x i1> [[TMP19]], <4 x i1> zeroinitializer546; FORCED-NEXT: [[TMP22:%.*]] = select <4 x i1> [[TMP16]], <4 x i1> [[TMP20]], <4 x i1> zeroinitializer547; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 1), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP21]])548; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 1), ptr align 1 [[TMP8]], <4 x i1> [[TMP22]])549; FORCED-NEXT: [[TMP23:%.*]] = select <4 x i1> [[TMP15]], <4 x i1> [[TMP11]], <4 x i1> zeroinitializer550; FORCED-NEXT: [[TMP24:%.*]] = select <4 x i1> [[TMP16]], <4 x i1> [[TMP12]], <4 x i1> zeroinitializer551; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP23]])552; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[TMP8]], <4 x i1> [[TMP24]])553; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP9]])554; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[TMP8]], <4 x i1> [[TMP10]])555; FORCED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8556; FORCED-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]557; FORCED-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]558; FORCED: [[MIDDLE_BLOCK]]:559; FORCED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]560; FORCED-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]561; FORCED: [[SCALAR_PH]]:562; FORCED-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]563; FORCED-NEXT: br label %[[LOOP_HEADER:.*]]564; FORCED: [[LOOP_HEADER]]:565; FORCED-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]566; FORCED-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 1567; FORCED-NEXT: [[EQ_0:%.*]] = icmp eq i64 [[L]], -12568; FORCED-NEXT: [[EQ_1:%.*]] = icmp eq i64 [[L]], 13569; FORCED-NEXT: [[EQ_2:%.*]] = icmp eq i64 [[L]], 0570; FORCED-NEXT: br i1 [[EQ_0]], label %[[IF_THEN_1:.*]], label %[[ELSE_1:.*]]571; FORCED: [[ELSE_1]]:572; FORCED-NEXT: br i1 [[EQ_1]], label %[[IF_THEN_2:.*]], label %[[ELSE_2:.*]]573; FORCED: [[ELSE_2]]:574; FORCED-NEXT: br i1 [[EQ_2]], label %[[IF_THEN_3:.*]], label %[[LOOP_LATCH]]575; FORCED: [[IF_THEN_1]]:576; FORCED-NEXT: store i64 42, ptr [[PTR_IV]], align 1577; FORCED-NEXT: br label %[[LOOP_LATCH]]578; FORCED: [[IF_THEN_2]]:579; FORCED-NEXT: store i64 0, ptr [[PTR_IV]], align 1580; FORCED-NEXT: br label %[[LOOP_LATCH]]581; FORCED: [[IF_THEN_3]]:582; FORCED-NEXT: store i64 1, ptr [[PTR_IV]], align 1583; FORCED-NEXT: br label %[[LOOP_LATCH]]584; FORCED: [[DEFAULT:.*:]]585; FORCED-NEXT: store i64 2, ptr poison, align 1586; FORCED-NEXT: unreachable587; FORCED: [[LOOP_LATCH]]:588; FORCED-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 1589; FORCED-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]590; FORCED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP9:![0-9]+]]591; FORCED: [[EXIT]]:592; FORCED-NEXT: ret void593;594entry:595 br label %loop.header596 597loop.header:598 %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]599 %l = load i64, ptr %ptr.iv, align 1600 %eq.0 = icmp eq i64 %l, -12601 %eq.1 = icmp eq i64 %l, 13602 %eq.2 = icmp eq i64 %l, 0603 br i1 %eq.0, label %if.then.1, label %else.1604 605else.1:606 br i1 %eq.1, label %if.then.2, label %else.2607 608else.2:609 br i1 %eq.2, label %if.then.3, label %loop.latch610 611if.then.1:612 store i64 42, ptr %ptr.iv, align 1613 br label %loop.latch614 615if.then.2:616 store i64 0, ptr %ptr.iv, align 1617 br label %loop.latch618 619if.then.3:620 store i64 1, ptr %ptr.iv, align 1621 br label %loop.latch622 623default:624 store i64 2, ptr %ptr.iv, align 1625 br label %loop.latch626 627loop.latch:628 %ptr.iv.next = getelementptr inbounds i64, ptr %ptr.iv, i64 1629 %ec = icmp eq ptr %ptr.iv.next, %end630 br i1 %ec, label %exit, label %loop.header631 632exit:633 ret void634}635 636 637 638define void @switch_multiple_common_dests(ptr %start, ptr %end) {639; COST-LABEL: define void @switch_multiple_common_dests(640; COST-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {641; COST-NEXT: [[ENTRY:.*]]:642; COST-NEXT: br label %[[LOOP_HEADER:.*]]643; COST: [[LOOP_HEADER]]:644; COST-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[START]], %[[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]645; COST-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 1646; COST-NEXT: switch i64 [[L]], label %[[DEFAULT:.*]] [647; COST-NEXT: i64 -12, label %[[IF_THEN_1:.*]]648; COST-NEXT: i64 0, label %[[IF_THEN_1]]649; COST-NEXT: i64 13, label %[[IF_THEN_2:.*]]650; COST-NEXT: i64 14, label %[[IF_THEN_2]]651; COST-NEXT: i64 15, label %[[IF_THEN_2]]652; COST-NEXT: ]653; COST: [[IF_THEN_1]]:654; COST-NEXT: store i64 42, ptr [[PTR_IV]], align 1655; COST-NEXT: br label %[[LOOP_LATCH]]656; COST: [[IF_THEN_2]]:657; COST-NEXT: store i64 0, ptr [[PTR_IV]], align 1658; COST-NEXT: br label %[[LOOP_LATCH]]659; COST: [[DEFAULT]]:660; COST-NEXT: store i64 2, ptr [[PTR_IV]], align 1661; COST-NEXT: br label %[[LOOP_LATCH]]662; COST: [[LOOP_LATCH]]:663; COST-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 1664; COST-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]665; COST-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]666; COST: [[EXIT]]:667; COST-NEXT: ret void668;669; FORCED-LABEL: define void @switch_multiple_common_dests(670; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {671; FORCED-NEXT: [[ENTRY:.*]]:672; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64673; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64674; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8675; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]676; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3677; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1678; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8679; FORCED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]680; FORCED: [[VECTOR_PH]]:681; FORCED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 8682; FORCED-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]683; FORCED-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 8684; FORCED-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]685; FORCED-NEXT: br label %[[VECTOR_BODY:.*]]686; FORCED: [[VECTOR_BODY]]:687; FORCED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]688; FORCED-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8689; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]]690; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i64 4691; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[NEXT_GEP]], align 1692; FORCED-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP8]], align 1693; FORCED-NEXT: [[TMP23:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 -12)694; FORCED-NEXT: [[TMP24:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 -12)695; FORCED-NEXT: [[TMP25:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], zeroinitializer696; FORCED-NEXT: [[TMP26:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], zeroinitializer697; FORCED-NEXT: [[TMP13:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 13)698; FORCED-NEXT: [[TMP14:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 13)699; FORCED-NEXT: [[TMP17:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 14)700; FORCED-NEXT: [[TMP18:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 14)701; FORCED-NEXT: [[TMP15:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 15)702; FORCED-NEXT: [[TMP16:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 15)703; FORCED-NEXT: [[TMP27:%.*]] = or <4 x i1> [[TMP23]], [[TMP25]]704; FORCED-NEXT: [[TMP28:%.*]] = or <4 x i1> [[TMP24]], [[TMP26]]705; FORCED-NEXT: [[TMP21:%.*]] = or <4 x i1> [[TMP13]], [[TMP17]]706; FORCED-NEXT: [[TMP22:%.*]] = or <4 x i1> [[TMP14]], [[TMP18]]707; FORCED-NEXT: [[TMP35:%.*]] = or <4 x i1> [[TMP21]], [[TMP15]]708; FORCED-NEXT: [[TMP36:%.*]] = or <4 x i1> [[TMP22]], [[TMP16]]709; FORCED-NEXT: [[TMP37:%.*]] = or <4 x i1> [[TMP27]], [[TMP35]]710; FORCED-NEXT: [[TMP38:%.*]] = or <4 x i1> [[TMP28]], [[TMP36]]711; FORCED-NEXT: [[TMP39:%.*]] = xor <4 x i1> [[TMP37]], splat (i1 true)712; FORCED-NEXT: [[TMP40:%.*]] = xor <4 x i1> [[TMP38]], splat (i1 true)713; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP35]])714; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[TMP8]], <4 x i1> [[TMP36]])715; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP27]])716; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[TMP8]], <4 x i1> [[TMP28]])717; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 2), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP39]])718; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 2), ptr align 1 [[TMP8]], <4 x i1> [[TMP40]])719; FORCED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8720; FORCED-NEXT: [[TMP41:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]721; FORCED-NEXT: br i1 [[TMP41]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]722; FORCED: [[MIDDLE_BLOCK]]:723; FORCED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]724; FORCED-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]725; FORCED: [[SCALAR_PH]]:726; FORCED-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]727; FORCED-NEXT: br label %[[LOOP_HEADER:.*]]728; FORCED: [[LOOP_HEADER]]:729; FORCED-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]730; FORCED-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 1731; FORCED-NEXT: switch i64 [[L]], label %[[DEFAULT:.*]] [732; FORCED-NEXT: i64 -12, label %[[IF_THEN_1:.*]]733; FORCED-NEXT: i64 0, label %[[IF_THEN_1]]734; FORCED-NEXT: i64 13, label %[[IF_THEN_2:.*]]735; FORCED-NEXT: i64 14, label %[[IF_THEN_2]]736; FORCED-NEXT: i64 15, label %[[IF_THEN_2]]737; FORCED-NEXT: ]738; FORCED: [[IF_THEN_1]]:739; FORCED-NEXT: store i64 42, ptr [[PTR_IV]], align 1740; FORCED-NEXT: br label %[[LOOP_LATCH]]741; FORCED: [[IF_THEN_2]]:742; FORCED-NEXT: store i64 0, ptr [[PTR_IV]], align 1743; FORCED-NEXT: br label %[[LOOP_LATCH]]744; FORCED: [[DEFAULT]]:745; FORCED-NEXT: store i64 2, ptr [[PTR_IV]], align 1746; FORCED-NEXT: br label %[[LOOP_LATCH]]747; FORCED: [[LOOP_LATCH]]:748; FORCED-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 1749; FORCED-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]750; FORCED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP11:![0-9]+]]751; FORCED: [[EXIT]]:752; FORCED-NEXT: ret void753;754entry:755 br label %loop.header756 757loop.header:758 %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]759 %l = load i64, ptr %ptr.iv, align 1760 switch i64 %l, label %default [761 i64 -12, label %if.then.1762 i64 0, label %if.then.1763 i64 13, label %if.then.2764 i64 14, label %if.then.2765 i64 15, label %if.then.2766 ]767 768if.then.1:769 store i64 42, ptr %ptr.iv, align 1770 br label %loop.latch771 772if.then.2:773 store i64 0, ptr %ptr.iv, align 1774 br label %loop.latch775 776default:777 store i64 2, ptr %ptr.iv, align 1778 br label %loop.latch779 780loop.latch:781 %ptr.iv.next = getelementptr inbounds i64, ptr %ptr.iv, i64 1782 %ec = icmp eq ptr %ptr.iv.next, %end783 br i1 %ec, label %exit, label %loop.header784 785exit:786 ret void787}788 789define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {790; COST-LABEL: define void @switch4_default_common_dest_with_case(791; COST-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {792; COST-NEXT: [[ENTRY:.*]]:793; COST-NEXT: br label %[[LOOP_HEADER:.*]]794; COST: [[LOOP_HEADER]]:795; COST-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[START]], %[[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]796; COST-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 1797; COST-NEXT: switch i64 [[L]], label %[[DEFAULT:.*]] [798; COST-NEXT: i64 -12, label %[[IF_THEN_1:.*]]799; COST-NEXT: i64 13, label %[[IF_THEN_2:.*]]800; COST-NEXT: i64 0, label %[[DEFAULT]]801; COST-NEXT: ]802; COST: [[IF_THEN_1]]:803; COST-NEXT: store i64 42, ptr [[PTR_IV]], align 1804; COST-NEXT: br label %[[LOOP_LATCH]]805; COST: [[IF_THEN_2]]:806; COST-NEXT: store i64 0, ptr [[PTR_IV]], align 1807; COST-NEXT: br label %[[LOOP_LATCH]]808; COST: [[DEFAULT]]:809; COST-NEXT: store i64 2, ptr [[PTR_IV]], align 1810; COST-NEXT: br label %[[LOOP_LATCH]]811; COST: [[LOOP_LATCH]]:812; COST-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 1813; COST-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]814; COST-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]815; COST: [[EXIT]]:816; COST-NEXT: ret void817;818; FORCED-LABEL: define void @switch4_default_common_dest_with_case(819; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {820; FORCED-NEXT: [[ENTRY:.*]]:821; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64822; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64823; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8824; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]825; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3826; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1827; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8828; FORCED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]829; FORCED: [[VECTOR_PH]]:830; FORCED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 8831; FORCED-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]832; FORCED-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 8833; FORCED-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]834; FORCED-NEXT: br label %[[VECTOR_BODY:.*]]835; FORCED: [[VECTOR_BODY]]:836; FORCED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]837; FORCED-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8838; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]]839; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i64 4840; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[NEXT_GEP]], align 1841; FORCED-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP8]], align 1842; FORCED-NEXT: [[TMP15:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 -12)843; FORCED-NEXT: [[TMP16:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 -12)844; FORCED-NEXT: [[TMP11:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 13)845; FORCED-NEXT: [[TMP12:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 13)846; FORCED-NEXT: [[TMP17:%.*]] = or <4 x i1> [[TMP15]], [[TMP11]]847; FORCED-NEXT: [[TMP18:%.*]] = or <4 x i1> [[TMP16]], [[TMP12]]848; FORCED-NEXT: [[TMP20:%.*]] = xor <4 x i1> [[TMP17]], splat (i1 true)849; FORCED-NEXT: [[TMP21:%.*]] = xor <4 x i1> [[TMP18]], splat (i1 true)850; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP11]])851; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[TMP8]], <4 x i1> [[TMP12]])852; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP15]])853; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[TMP8]], <4 x i1> [[TMP16]])854; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 2), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP20]])855; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 2), ptr align 1 [[TMP8]], <4 x i1> [[TMP21]])856; FORCED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8857; FORCED-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]858; FORCED-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]859; FORCED: [[MIDDLE_BLOCK]]:860; FORCED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]861; FORCED-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]862; FORCED: [[SCALAR_PH]]:863; FORCED-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]864; FORCED-NEXT: br label %[[LOOP_HEADER:.*]]865; FORCED: [[LOOP_HEADER]]:866; FORCED-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]867; FORCED-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 1868; FORCED-NEXT: switch i64 [[L]], label %[[DEFAULT:.*]] [869; FORCED-NEXT: i64 -12, label %[[IF_THEN_1:.*]]870; FORCED-NEXT: i64 13, label %[[IF_THEN_2:.*]]871; FORCED-NEXT: i64 0, label %[[DEFAULT]]872; FORCED-NEXT: ]873; FORCED: [[IF_THEN_1]]:874; FORCED-NEXT: store i64 42, ptr [[PTR_IV]], align 1875; FORCED-NEXT: br label %[[LOOP_LATCH]]876; FORCED: [[IF_THEN_2]]:877; FORCED-NEXT: store i64 0, ptr [[PTR_IV]], align 1878; FORCED-NEXT: br label %[[LOOP_LATCH]]879; FORCED: [[DEFAULT]]:880; FORCED-NEXT: store i64 2, ptr [[PTR_IV]], align 1881; FORCED-NEXT: br label %[[LOOP_LATCH]]882; FORCED: [[LOOP_LATCH]]:883; FORCED-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 1884; FORCED-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]885; FORCED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP13:![0-9]+]]886; FORCED: [[EXIT]]:887; FORCED-NEXT: ret void888;889entry:890 br label %loop.header891 892loop.header:893 %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]894 %l = load i64, ptr %ptr.iv, align 1895 switch i64 %l, label %default [896 i64 -12, label %if.then.1897 i64 13, label %if.then.2898 i64 0, label %default899 ]900 901if.then.1:902 store i64 42, ptr %ptr.iv, align 1903 br label %loop.latch904 905if.then.2:906 store i64 0, ptr %ptr.iv, align 1907 br label %loop.latch908 909default:910 store i64 2, ptr %ptr.iv, align 1911 br label %loop.latch912 913loop.latch:914 %ptr.iv.next = getelementptr inbounds i64, ptr %ptr.iv, i64 1915 %ec = icmp eq ptr %ptr.iv.next, %end916 br i1 %ec, label %exit, label %loop.header917 918exit:919 ret void920}921 922define void @switch_under_br_default_common_dest_with_case(ptr %start, ptr %end, i64 %x) {923; COST-LABEL: define void @switch_under_br_default_common_dest_with_case(924; COST-SAME: ptr [[START:%.*]], ptr [[END:%.*]], i64 [[X:%.*]]) #[[ATTR0]] {925; COST-NEXT: [[ENTRY:.*]]:926; COST-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64927; COST-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64928; COST-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8929; COST-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]930; COST-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3931; COST-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1932; COST-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4933; COST-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]934; COST: [[VECTOR_PH]]:935; COST-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 4936; COST-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]937; COST-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 8938; COST-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]939; COST-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[X]], i64 0940; COST-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer941; COST-NEXT: br label %[[VECTOR_BODY:.*]]942; COST: [[VECTOR_BODY]]:943; COST-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]944; COST-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8945; COST-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]]946; COST-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[NEXT_GEP]], align 1947; COST-NEXT: [[TMP7:%.*]] = icmp ule <4 x i64> [[WIDE_LOAD]], [[BROADCAST_SPLAT]]948; COST-NEXT: [[TMP8:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 -12)949; COST-NEXT: [[TMP9:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 13)950; COST-NEXT: [[TMP10:%.*]] = select <4 x i1> [[TMP7]], <4 x i1> [[TMP8]], <4 x i1> zeroinitializer951; COST-NEXT: [[TMP11:%.*]] = select <4 x i1> [[TMP7]], <4 x i1> [[TMP9]], <4 x i1> zeroinitializer952; COST-NEXT: [[TMP12:%.*]] = or <4 x i1> [[TMP10]], [[TMP11]]953; COST-NEXT: [[TMP13:%.*]] = xor <4 x i1> [[TMP12]], splat (i1 true)954; COST-NEXT: [[TMP14:%.*]] = select <4 x i1> [[TMP7]], <4 x i1> [[TMP13]], <4 x i1> zeroinitializer955; COST-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP11]])956; COST-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP10]])957; COST-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 2), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP14]])958; COST-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4959; COST-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]960; COST-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]961; COST: [[MIDDLE_BLOCK]]:962; COST-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]963; COST-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]964; COST: [[SCALAR_PH]]:965; COST-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]966; COST-NEXT: br label %[[LOOP_HEADER:.*]]967; COST: [[LOOP_HEADER]]:968; COST-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]969; COST-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 1970; COST-NEXT: [[C:%.*]] = icmp ule i64 [[L]], [[X]]971; COST-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_LATCH]]972; COST: [[THEN]]:973; COST-NEXT: switch i64 [[L]], label %[[DEFAULT:.*]] [974; COST-NEXT: i64 -12, label %[[IF_THEN_1:.*]]975; COST-NEXT: i64 13, label %[[IF_THEN_2:.*]]976; COST-NEXT: i64 0, label %[[DEFAULT]]977; COST-NEXT: ]978; COST: [[IF_THEN_1]]:979; COST-NEXT: store i64 42, ptr [[PTR_IV]], align 1980; COST-NEXT: br label %[[LOOP_LATCH]]981; COST: [[IF_THEN_2]]:982; COST-NEXT: store i64 0, ptr [[PTR_IV]], align 1983; COST-NEXT: br label %[[LOOP_LATCH]]984; COST: [[DEFAULT]]:985; COST-NEXT: store i64 2, ptr [[PTR_IV]], align 1986; COST-NEXT: br label %[[LOOP_LATCH]]987; COST: [[LOOP_LATCH]]:988; COST-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 1989; COST-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]990; COST-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP9:![0-9]+]]991; COST: [[EXIT]]:992; COST-NEXT: ret void993;994; FORCED-LABEL: define void @switch_under_br_default_common_dest_with_case(995; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]], i64 [[X:%.*]]) #[[ATTR0]] {996; FORCED-NEXT: [[ENTRY:.*]]:997; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64998; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64999; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -81000; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]1001; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 31002; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 11003; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 81004; FORCED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]1005; FORCED: [[VECTOR_PH]]:1006; FORCED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 81007; FORCED-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]1008; FORCED-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 81009; FORCED-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]1010; FORCED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[X]], i64 01011; FORCED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer1012; FORCED-NEXT: br label %[[VECTOR_BODY:.*]]1013; FORCED: [[VECTOR_BODY]]:1014; FORCED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1015; FORCED-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 81016; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]]1017; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i64 41018; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[NEXT_GEP]], align 11019; FORCED-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP8]], align 11020; FORCED-NEXT: [[TMP9:%.*]] = icmp ule <4 x i64> [[WIDE_LOAD]], [[BROADCAST_SPLAT]]1021; FORCED-NEXT: [[TMP10:%.*]] = icmp ule <4 x i64> [[WIDE_LOAD4]], [[BROADCAST_SPLAT]]1022; FORCED-NEXT: [[TMP11:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 -12)1023; FORCED-NEXT: [[TMP12:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 -12)1024; FORCED-NEXT: [[TMP13:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 13)1025; FORCED-NEXT: [[TMP14:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 13)1026; FORCED-NEXT: [[TMP15:%.*]] = select <4 x i1> [[TMP9]], <4 x i1> [[TMP11]], <4 x i1> zeroinitializer1027; FORCED-NEXT: [[TMP16:%.*]] = select <4 x i1> [[TMP10]], <4 x i1> [[TMP12]], <4 x i1> zeroinitializer1028; FORCED-NEXT: [[TMP25:%.*]] = select <4 x i1> [[TMP9]], <4 x i1> [[TMP13]], <4 x i1> zeroinitializer1029; FORCED-NEXT: [[TMP26:%.*]] = select <4 x i1> [[TMP10]], <4 x i1> [[TMP14]], <4 x i1> zeroinitializer1030; FORCED-NEXT: [[TMP27:%.*]] = or <4 x i1> [[TMP15]], [[TMP25]]1031; FORCED-NEXT: [[TMP20:%.*]] = or <4 x i1> [[TMP16]], [[TMP26]]1032; FORCED-NEXT: [[TMP21:%.*]] = xor <4 x i1> [[TMP27]], splat (i1 true)1033; FORCED-NEXT: [[TMP22:%.*]] = xor <4 x i1> [[TMP20]], splat (i1 true)1034; FORCED-NEXT: [[TMP23:%.*]] = select <4 x i1> [[TMP9]], <4 x i1> [[TMP21]], <4 x i1> zeroinitializer1035; FORCED-NEXT: [[TMP24:%.*]] = select <4 x i1> [[TMP10]], <4 x i1> [[TMP22]], <4 x i1> zeroinitializer1036; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP25]])1037; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[TMP8]], <4 x i1> [[TMP26]])1038; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP15]])1039; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[TMP8]], <4 x i1> [[TMP16]])1040; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 2), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP23]])1041; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 2), ptr align 1 [[TMP8]], <4 x i1> [[TMP24]])1042; FORCED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 81043; FORCED-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]1044; FORCED-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]1045; FORCED: [[MIDDLE_BLOCK]]:1046; FORCED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]1047; FORCED-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]1048; FORCED: [[SCALAR_PH]]:1049; FORCED-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]1050; FORCED-NEXT: br label %[[LOOP_HEADER:.*]]1051; FORCED: [[LOOP_HEADER]]:1052; FORCED-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]1053; FORCED-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 11054; FORCED-NEXT: [[C:%.*]] = icmp ule i64 [[L]], [[X]]1055; FORCED-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_LATCH]]1056; FORCED: [[THEN]]:1057; FORCED-NEXT: switch i64 [[L]], label %[[DEFAULT:.*]] [1058; FORCED-NEXT: i64 -12, label %[[IF_THEN_1:.*]]1059; FORCED-NEXT: i64 13, label %[[IF_THEN_2:.*]]1060; FORCED-NEXT: i64 0, label %[[DEFAULT]]1061; FORCED-NEXT: ]1062; FORCED: [[IF_THEN_1]]:1063; FORCED-NEXT: store i64 42, ptr [[PTR_IV]], align 11064; FORCED-NEXT: br label %[[LOOP_LATCH]]1065; FORCED: [[IF_THEN_2]]:1066; FORCED-NEXT: store i64 0, ptr [[PTR_IV]], align 11067; FORCED-NEXT: br label %[[LOOP_LATCH]]1068; FORCED: [[DEFAULT]]:1069; FORCED-NEXT: store i64 2, ptr [[PTR_IV]], align 11070; FORCED-NEXT: br label %[[LOOP_LATCH]]1071; FORCED: [[LOOP_LATCH]]:1072; FORCED-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 11073; FORCED-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]1074; FORCED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP15:![0-9]+]]1075; FORCED: [[EXIT]]:1076; FORCED-NEXT: ret void1077;1078entry:1079 br label %loop.header1080 1081loop.header:1082 %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]1083 %l = load i64, ptr %ptr.iv, align 11084 %c = icmp ule i64 %l, %x1085 br i1 %c, label %then, label %loop.latch1086 1087then:1088 switch i64 %l, label %default [1089 i64 -12, label %if.then.11090 i64 13, label %if.then.21091 i64 0, label %default1092 ]1093 1094if.then.1:1095 store i64 42, ptr %ptr.iv, align 11096 br label %loop.latch1097 1098if.then.2:1099 store i64 0, ptr %ptr.iv, align 11100 br label %loop.latch1101 1102default:1103 store i64 2, ptr %ptr.iv, align 11104 br label %loop.latch1105 1106loop.latch:1107 %ptr.iv.next = getelementptr inbounds i64, ptr %ptr.iv, i64 11108 %ec = icmp eq ptr %ptr.iv.next, %end1109 br i1 %ec, label %exit, label %loop.header1110 1111exit:1112 ret void1113}1114 1115define void @br_under_switch_default_common_dest_with_case(ptr %start, ptr %end, i64 %x) {1116; COST-LABEL: define void @br_under_switch_default_common_dest_with_case(1117; COST-SAME: ptr [[START:%.*]], ptr [[END:%.*]], i64 [[X:%.*]]) #[[ATTR0]] {1118; COST-NEXT: [[ENTRY:.*]]:1119; COST-NEXT: br label %[[LOOP_HEADER:.*]]1120; COST: [[LOOP_HEADER]]:1121; COST-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[START]], %[[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]1122; COST-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 11123; COST-NEXT: switch i64 [[L]], label %[[DEFAULT:.*]] [1124; COST-NEXT: i64 -12, label %[[IF_THEN_1:.*]]1125; COST-NEXT: i64 13, label %[[IF_THEN_2:.*]]1126; COST-NEXT: i64 0, label %[[DEFAULT]]1127; COST-NEXT: ]1128; COST: [[IF_THEN_1]]:1129; COST-NEXT: [[C:%.*]] = icmp ule i64 [[L]], [[X]]1130; COST-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[IF_THEN_2]]1131; COST: [[THEN]]:1132; COST-NEXT: store i64 42, ptr [[PTR_IV]], align 11133; COST-NEXT: br label %[[DEFAULT]]1134; COST: [[IF_THEN_2]]:1135; COST-NEXT: store i64 0, ptr [[PTR_IV]], align 11136; COST-NEXT: br label %[[LOOP_LATCH]]1137; COST: [[DEFAULT]]:1138; COST-NEXT: store i64 2, ptr [[PTR_IV]], align 11139; COST-NEXT: br label %[[LOOP_LATCH]]1140; COST: [[LOOP_LATCH]]:1141; COST-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 11142; COST-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]1143; COST-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]1144; COST: [[EXIT]]:1145; COST-NEXT: ret void1146;1147; FORCED-LABEL: define void @br_under_switch_default_common_dest_with_case(1148; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]], i64 [[X:%.*]]) #[[ATTR0]] {1149; FORCED-NEXT: [[ENTRY:.*]]:1150; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i641151; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i641152; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -81153; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]1154; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 31155; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 11156; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 81157; FORCED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]1158; FORCED: [[VECTOR_PH]]:1159; FORCED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 81160; FORCED-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]1161; FORCED-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 81162; FORCED-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]1163; FORCED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[X]], i64 01164; FORCED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer1165; FORCED-NEXT: br label %[[VECTOR_BODY:.*]]1166; FORCED: [[VECTOR_BODY]]:1167; FORCED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1168; FORCED-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 81169; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]]1170; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i64 41171; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[NEXT_GEP]], align 11172; FORCED-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP8]], align 11173; FORCED-NEXT: [[TMP9:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 -12)1174; FORCED-NEXT: [[TMP10:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 -12)1175; FORCED-NEXT: [[TMP25:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 13)1176; FORCED-NEXT: [[TMP26:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 13)1177; FORCED-NEXT: [[TMP13:%.*]] = or <4 x i1> [[TMP9]], [[TMP25]]1178; FORCED-NEXT: [[TMP14:%.*]] = or <4 x i1> [[TMP10]], [[TMP26]]1179; FORCED-NEXT: [[TMP15:%.*]] = xor <4 x i1> [[TMP13]], splat (i1 true)1180; FORCED-NEXT: [[TMP16:%.*]] = xor <4 x i1> [[TMP14]], splat (i1 true)1181; FORCED-NEXT: [[TMP17:%.*]] = icmp ule <4 x i64> [[WIDE_LOAD]], [[BROADCAST_SPLAT]]1182; FORCED-NEXT: [[TMP18:%.*]] = icmp ule <4 x i64> [[WIDE_LOAD4]], [[BROADCAST_SPLAT]]1183; FORCED-NEXT: [[TMP19:%.*]] = xor <4 x i1> [[TMP17]], splat (i1 true)1184; FORCED-NEXT: [[TMP20:%.*]] = xor <4 x i1> [[TMP18]], splat (i1 true)1185; FORCED-NEXT: [[TMP27:%.*]] = select <4 x i1> [[TMP9]], <4 x i1> [[TMP19]], <4 x i1> zeroinitializer1186; FORCED-NEXT: [[TMP28:%.*]] = select <4 x i1> [[TMP10]], <4 x i1> [[TMP20]], <4 x i1> zeroinitializer1187; FORCED-NEXT: [[TMP29:%.*]] = or <4 x i1> [[TMP27]], [[TMP25]]1188; FORCED-NEXT: [[TMP30:%.*]] = or <4 x i1> [[TMP28]], [[TMP26]]1189; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP29]])1190; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr align 1 [[TMP8]], <4 x i1> [[TMP30]])1191; FORCED-NEXT: [[TMP32:%.*]] = select <4 x i1> [[TMP9]], <4 x i1> [[TMP17]], <4 x i1> zeroinitializer1192; FORCED-NEXT: [[TMP33:%.*]] = select <4 x i1> [[TMP10]], <4 x i1> [[TMP18]], <4 x i1> zeroinitializer1193; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP32]])1194; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[TMP8]], <4 x i1> [[TMP33]])1195; FORCED-NEXT: [[TMP36:%.*]] = or <4 x i1> [[TMP32]], [[TMP15]]1196; FORCED-NEXT: [[TMP37:%.*]] = or <4 x i1> [[TMP33]], [[TMP16]]1197; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 2), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP36]])1198; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 2), ptr align 1 [[TMP8]], <4 x i1> [[TMP37]])1199; FORCED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 81200; FORCED-NEXT: [[TMP31:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]1201; FORCED-NEXT: br i1 [[TMP31]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]1202; FORCED: [[MIDDLE_BLOCK]]:1203; FORCED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]1204; FORCED-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]1205; FORCED: [[SCALAR_PH]]:1206; FORCED-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]1207; FORCED-NEXT: br label %[[LOOP_HEADER:.*]]1208; FORCED: [[LOOP_HEADER]]:1209; FORCED-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]1210; FORCED-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 11211; FORCED-NEXT: switch i64 [[L]], label %[[DEFAULT:.*]] [1212; FORCED-NEXT: i64 -12, label %[[IF_THEN_1:.*]]1213; FORCED-NEXT: i64 13, label %[[IF_THEN_2:.*]]1214; FORCED-NEXT: i64 0, label %[[DEFAULT]]1215; FORCED-NEXT: ]1216; FORCED: [[IF_THEN_1]]:1217; FORCED-NEXT: [[C:%.*]] = icmp ule i64 [[L]], [[X]]1218; FORCED-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[IF_THEN_2]]1219; FORCED: [[THEN]]:1220; FORCED-NEXT: store i64 42, ptr [[PTR_IV]], align 11221; FORCED-NEXT: br label %[[DEFAULT]]1222; FORCED: [[IF_THEN_2]]:1223; FORCED-NEXT: store i64 0, ptr [[PTR_IV]], align 11224; FORCED-NEXT: br label %[[LOOP_LATCH]]1225; FORCED: [[DEFAULT]]:1226; FORCED-NEXT: store i64 2, ptr [[PTR_IV]], align 11227; FORCED-NEXT: br label %[[LOOP_LATCH]]1228; FORCED: [[LOOP_LATCH]]:1229; FORCED-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 11230; FORCED-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]1231; FORCED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP17:![0-9]+]]1232; FORCED: [[EXIT]]:1233; FORCED-NEXT: ret void1234;1235entry:1236 br label %loop.header1237 1238loop.header:1239 %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]1240 %l = load i64, ptr %ptr.iv, align 11241 switch i64 %l, label %default [1242 i64 -12, label %if.then.11243 i64 13, label %if.then.21244 i64 0, label %default1245 ]1246 1247if.then.1:1248 %c = icmp ule i64 %l, %x1249 br i1 %c, label %then, label %if.then.21250 1251then:1252 store i64 42, ptr %ptr.iv, align 11253 br label %default1254 1255if.then.2:1256 store i64 0, ptr %ptr.iv, align 11257 br label %loop.latch1258 1259default:1260 store i64 2, ptr %ptr.iv, align 11261 br label %loop.latch1262 1263loop.latch:1264 %ptr.iv.next = getelementptr inbounds i64, ptr %ptr.iv, i64 11265 %ec = icmp eq ptr %ptr.iv.next, %end1266 br i1 %ec, label %exit, label %loop.header1267 1268exit:1269 ret void1270}1271 1272define void @large_number_of_cases(ptr %start, ptr %end) {1273; COST-LABEL: define void @large_number_of_cases(1274; COST-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {1275; COST-NEXT: [[ENTRY:.*]]:1276; COST-NEXT: br label %[[LOOP_HEADER:.*]]1277; COST: [[LOOP_HEADER]]:1278; COST-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[START]], %[[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]1279; COST-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 11280; COST-NEXT: switch i64 [[L]], label %[[LOOP_LATCH]] [1281; COST-NEXT: i64 1, label %[[IF_THEN:.*]]1282; COST-NEXT: i64 3, label %[[IF_THEN]]1283; COST-NEXT: i64 11, label %[[IF_THEN]]1284; COST-NEXT: i64 99, label %[[IF_THEN]]1285; COST-NEXT: i64 213, label %[[IF_THEN]]1286; COST-NEXT: i64 238, label %[[IF_THEN]]1287; COST-NEXT: i64 513, label %[[IF_THEN]]1288; COST-NEXT: i64 791, label %[[IF_THEN]]1289; COST-NEXT: i64 899, label %[[IF_THEN]]1290; COST-NEXT: ]1291; COST: [[IF_THEN]]:1292; COST-NEXT: store i64 42, ptr [[PTR_IV]], align 11293; COST-NEXT: br label %[[LOOP_LATCH]]1294; COST: [[LOOP_LATCH]]:1295; COST-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 11296; COST-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]1297; COST-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]1298; COST: [[EXIT]]:1299; COST-NEXT: ret void1300;1301; FORCED-LABEL: define void @large_number_of_cases(1302; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {1303; FORCED-NEXT: [[ENTRY:.*]]:1304; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i641305; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i641306; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -81307; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]1308; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 31309; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 11310; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 81311; FORCED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]1312; FORCED: [[VECTOR_PH]]:1313; FORCED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 81314; FORCED-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]1315; FORCED-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 81316; FORCED-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]1317; FORCED-NEXT: br label %[[VECTOR_BODY:.*]]1318; FORCED: [[VECTOR_BODY]]:1319; FORCED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1320; FORCED-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 81321; FORCED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]]1322; FORCED-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i64 41323; FORCED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[NEXT_GEP]], align 11324; FORCED-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP8]], align 11325; FORCED-NEXT: [[TMP9:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 1)1326; FORCED-NEXT: [[TMP10:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 1)1327; FORCED-NEXT: [[TMP11:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 3)1328; FORCED-NEXT: [[TMP12:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 3)1329; FORCED-NEXT: [[TMP13:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 11)1330; FORCED-NEXT: [[TMP14:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 11)1331; FORCED-NEXT: [[TMP15:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 99)1332; FORCED-NEXT: [[TMP16:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 99)1333; FORCED-NEXT: [[TMP17:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 213)1334; FORCED-NEXT: [[TMP18:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 213)1335; FORCED-NEXT: [[TMP19:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 238)1336; FORCED-NEXT: [[TMP20:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 238)1337; FORCED-NEXT: [[TMP21:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 513)1338; FORCED-NEXT: [[TMP22:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 513)1339; FORCED-NEXT: [[TMP23:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 791)1340; FORCED-NEXT: [[TMP24:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 791)1341; FORCED-NEXT: [[TMP25:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 899)1342; FORCED-NEXT: [[TMP26:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 899)1343; FORCED-NEXT: [[TMP27:%.*]] = or <4 x i1> [[TMP9]], [[TMP11]]1344; FORCED-NEXT: [[TMP28:%.*]] = or <4 x i1> [[TMP10]], [[TMP12]]1345; FORCED-NEXT: [[TMP29:%.*]] = or <4 x i1> [[TMP27]], [[TMP13]]1346; FORCED-NEXT: [[TMP30:%.*]] = or <4 x i1> [[TMP28]], [[TMP14]]1347; FORCED-NEXT: [[TMP31:%.*]] = or <4 x i1> [[TMP29]], [[TMP15]]1348; FORCED-NEXT: [[TMP32:%.*]] = or <4 x i1> [[TMP30]], [[TMP16]]1349; FORCED-NEXT: [[TMP33:%.*]] = or <4 x i1> [[TMP31]], [[TMP17]]1350; FORCED-NEXT: [[TMP34:%.*]] = or <4 x i1> [[TMP32]], [[TMP18]]1351; FORCED-NEXT: [[TMP35:%.*]] = or <4 x i1> [[TMP33]], [[TMP19]]1352; FORCED-NEXT: [[TMP36:%.*]] = or <4 x i1> [[TMP34]], [[TMP20]]1353; FORCED-NEXT: [[TMP37:%.*]] = or <4 x i1> [[TMP35]], [[TMP21]]1354; FORCED-NEXT: [[TMP38:%.*]] = or <4 x i1> [[TMP36]], [[TMP22]]1355; FORCED-NEXT: [[TMP39:%.*]] = or <4 x i1> [[TMP37]], [[TMP23]]1356; FORCED-NEXT: [[TMP40:%.*]] = or <4 x i1> [[TMP38]], [[TMP24]]1357; FORCED-NEXT: [[TMP57:%.*]] = or <4 x i1> [[TMP39]], [[TMP25]]1358; FORCED-NEXT: [[TMP58:%.*]] = or <4 x i1> [[TMP40]], [[TMP26]]1359; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[NEXT_GEP]], <4 x i1> [[TMP57]])1360; FORCED-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 42), ptr align 1 [[TMP8]], <4 x i1> [[TMP58]])1361; FORCED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 81362; FORCED-NEXT: [[TMP59:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]1363; FORCED-NEXT: br i1 [[TMP59]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]1364; FORCED: [[MIDDLE_BLOCK]]:1365; FORCED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]1366; FORCED-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]1367; FORCED: [[SCALAR_PH]]:1368; FORCED-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]1369; FORCED-NEXT: br label %[[LOOP_HEADER:.*]]1370; FORCED: [[LOOP_HEADER]]:1371; FORCED-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]1372; FORCED-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 11373; FORCED-NEXT: switch i64 [[L]], label %[[LOOP_LATCH]] [1374; FORCED-NEXT: i64 1, label %[[IF_THEN:.*]]1375; FORCED-NEXT: i64 3, label %[[IF_THEN]]1376; FORCED-NEXT: i64 11, label %[[IF_THEN]]1377; FORCED-NEXT: i64 99, label %[[IF_THEN]]1378; FORCED-NEXT: i64 213, label %[[IF_THEN]]1379; FORCED-NEXT: i64 238, label %[[IF_THEN]]1380; FORCED-NEXT: i64 513, label %[[IF_THEN]]1381; FORCED-NEXT: i64 791, label %[[IF_THEN]]1382; FORCED-NEXT: i64 899, label %[[IF_THEN]]1383; FORCED-NEXT: ]1384; FORCED: [[IF_THEN]]:1385; FORCED-NEXT: store i64 42, ptr [[PTR_IV]], align 11386; FORCED-NEXT: br label %[[LOOP_LATCH]]1387; FORCED: [[LOOP_LATCH]]:1388; FORCED-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 11389; FORCED-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]1390; FORCED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP19:![0-9]+]]1391; FORCED: [[EXIT]]:1392; FORCED-NEXT: ret void1393;1394entry:1395 br label %loop.header1396 1397loop.header:1398 %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]1399 %l = load i64, ptr %ptr.iv, align 11400 switch i64 %l, label %loop.latch [1401 i64 1, label %if.then1402 i64 3, label %if.then1403 i64 11, label %if.then1404 i64 99, label %if.then1405 i64 213, label %if.then1406 i64 238, label %if.then1407 i64 513, label %if.then1408 i64 791, label %if.then1409 i64 899, label %if.then1410 ]1411 1412if.then:1413 store i64 42, ptr %ptr.iv, align 11414 br label %loop.latch1415 1416loop.latch:1417 %ptr.iv.next = getelementptr inbounds i64, ptr %ptr.iv, i64 11418 %ec = icmp eq ptr %ptr.iv.next, %end1419 br i1 %ec, label %exit, label %loop.header1420 1421exit:1422 ret void1423}1424 1425;.1426; COST: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}1427; COST: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}1428; COST: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}1429; COST: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}1430; COST: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}1431; COST: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}1432; COST: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}1433; COST: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}1434; COST: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}1435; COST: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]}1436;.1437; FORCED: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}1438; FORCED: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}1439; FORCED: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}1440; FORCED: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}1441; FORCED: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}1442; FORCED: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}1443; FORCED: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}1444; FORCED: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}1445; FORCED: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}1446; FORCED: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]}1447; FORCED: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]}1448; FORCED: [[LOOP11]] = distinct !{[[LOOP11]], [[META2]], [[META1]]}1449; FORCED: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]], [[META2]]}1450; FORCED: [[LOOP13]] = distinct !{[[LOOP13]], [[META2]], [[META1]]}1451; FORCED: [[LOOP14]] = distinct !{[[LOOP14]], [[META1]], [[META2]]}1452; FORCED: [[LOOP15]] = distinct !{[[LOOP15]], [[META2]], [[META1]]}1453; FORCED: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]], [[META2]]}1454; FORCED: [[LOOP17]] = distinct !{[[LOOP17]], [[META2]], [[META1]]}1455; FORCED: [[LOOP18]] = distinct !{[[LOOP18]], [[META1]], [[META2]]}1456; FORCED: [[LOOP19]] = distinct !{[[LOOP19]], [[META2]], [[META1]]}1457;.1458