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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt -p loop-vectorize -mtriple=x86_64-apple-macosx -vectorizer-maximize-bandwidth -S %s | FileCheck %s3 4declare void @init(ptr captures(none), ptr captures(none), ptr captures(none))5 6define void @replicating_store_with_phi_addr1(ptr noalias %array, i64 %N, i32 %x, i1 %cond) {7; CHECK-LABEL: define void @replicating_store_with_phi_addr1(8; CHECK-SAME: ptr noalias [[ARRAY:%.*]], i64 [[N:%.*]], i32 [[X:%.*]], i1 [[COND:%.*]]) {9; CHECK-NEXT: [[ENTRY:.*:]]10; CHECK-NEXT: [[PTR1:%.*]] = alloca i8, align 111; CHECK-NEXT: [[PTR2:%.*]] = alloca i8, align 112; CHECK-NEXT: [[PTR3:%.*]] = alloca i8, align 113; CHECK-NEXT: call void @init(ptr [[PTR1]], ptr [[PTR2]], ptr [[PTR3]])14; CHECK-NEXT: br label %[[VECTOR_PH:.*]]15; CHECK: [[VECTOR_PH]]:16; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x ptr> poison, ptr [[PTR1]], i64 017; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x ptr> [[BROADCAST_SPLATINSERT]], <16 x ptr> poison, <16 x i32> zeroinitializer18; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <16 x i1> poison, i1 [[COND]], i64 019; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <16 x i1> [[BROADCAST_SPLATINSERT1]], <16 x i1> poison, <16 x i32> zeroinitializer20; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]21; CHECK: [[VECTOR_BODY]]:22; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE32:.*]] ]23; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAY]], align 824; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 425; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 426; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 427; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP0]], align 428; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 429; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 430; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP0]], align 431; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP0]], align 432; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP0]], align 433; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP0]], align 434; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP0]], align 435; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP0]], align 436; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP0]], align 437; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 438; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP0]], align 439; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 440; CHECK-NEXT: [[TMP17:%.*]] = insertelement <16 x i32> poison, i32 [[TMP1]], i32 041; CHECK-NEXT: [[TMP18:%.*]] = insertelement <16 x i32> [[TMP17]], i32 [[TMP2]], i32 142; CHECK-NEXT: [[TMP19:%.*]] = insertelement <16 x i32> [[TMP18]], i32 [[TMP3]], i32 243; CHECK-NEXT: [[TMP20:%.*]] = insertelement <16 x i32> [[TMP19]], i32 [[TMP4]], i32 344; CHECK-NEXT: [[TMP21:%.*]] = insertelement <16 x i32> [[TMP20]], i32 [[TMP5]], i32 445; CHECK-NEXT: [[TMP22:%.*]] = insertelement <16 x i32> [[TMP21]], i32 [[TMP6]], i32 546; CHECK-NEXT: [[TMP23:%.*]] = insertelement <16 x i32> [[TMP22]], i32 [[TMP7]], i32 647; CHECK-NEXT: [[TMP24:%.*]] = insertelement <16 x i32> [[TMP23]], i32 [[TMP8]], i32 748; CHECK-NEXT: [[TMP25:%.*]] = insertelement <16 x i32> [[TMP24]], i32 [[TMP9]], i32 849; CHECK-NEXT: [[TMP26:%.*]] = insertelement <16 x i32> [[TMP25]], i32 [[TMP10]], i32 950; CHECK-NEXT: [[TMP27:%.*]] = insertelement <16 x i32> [[TMP26]], i32 [[TMP11]], i32 1051; CHECK-NEXT: [[TMP28:%.*]] = insertelement <16 x i32> [[TMP27]], i32 [[TMP12]], i32 1152; CHECK-NEXT: [[TMP29:%.*]] = insertelement <16 x i32> [[TMP28]], i32 [[TMP13]], i32 1253; CHECK-NEXT: [[TMP30:%.*]] = insertelement <16 x i32> [[TMP29]], i32 [[TMP14]], i32 1354; CHECK-NEXT: [[TMP31:%.*]] = insertelement <16 x i32> [[TMP30]], i32 [[TMP15]], i32 1455; CHECK-NEXT: [[TMP32:%.*]] = insertelement <16 x i32> [[TMP31]], i32 [[TMP16]], i32 1556; CHECK-NEXT: [[TMP33:%.*]] = icmp sgt <16 x i32> [[TMP32]], zeroinitializer57; CHECK-NEXT: [[TMP34:%.*]] = xor <16 x i1> [[TMP33]], splat (i1 true)58; CHECK-NEXT: [[TMP35:%.*]] = icmp slt i32 [[X]], [[TMP1]]59; CHECK-NEXT: [[TMP36:%.*]] = icmp slt i32 [[X]], [[TMP2]]60; CHECK-NEXT: [[TMP37:%.*]] = icmp slt i32 [[X]], [[TMP3]]61; CHECK-NEXT: [[TMP38:%.*]] = icmp slt i32 [[X]], [[TMP4]]62; CHECK-NEXT: [[TMP39:%.*]] = icmp slt i32 [[X]], [[TMP5]]63; CHECK-NEXT: [[TMP40:%.*]] = icmp slt i32 [[X]], [[TMP6]]64; CHECK-NEXT: [[TMP41:%.*]] = icmp slt i32 [[X]], [[TMP7]]65; CHECK-NEXT: [[TMP42:%.*]] = icmp slt i32 [[X]], [[TMP8]]66; CHECK-NEXT: [[TMP43:%.*]] = icmp slt i32 [[X]], [[TMP9]]67; CHECK-NEXT: [[TMP44:%.*]] = icmp slt i32 [[X]], [[TMP10]]68; CHECK-NEXT: [[TMP45:%.*]] = icmp slt i32 [[X]], [[TMP11]]69; CHECK-NEXT: [[TMP46:%.*]] = icmp slt i32 [[X]], [[TMP12]]70; CHECK-NEXT: [[TMP47:%.*]] = icmp slt i32 [[X]], [[TMP13]]71; CHECK-NEXT: [[TMP48:%.*]] = icmp slt i32 [[X]], [[TMP14]]72; CHECK-NEXT: [[TMP49:%.*]] = icmp slt i32 [[X]], [[TMP15]]73; CHECK-NEXT: [[TMP50:%.*]] = icmp slt i32 [[X]], [[TMP16]]74; CHECK-NEXT: [[TMP51:%.*]] = select i1 [[TMP35]], ptr [[PTR2]], ptr [[PTR3]]75; CHECK-NEXT: [[TMP52:%.*]] = select i1 [[TMP36]], ptr [[PTR2]], ptr [[PTR3]]76; CHECK-NEXT: [[TMP53:%.*]] = select i1 [[TMP37]], ptr [[PTR2]], ptr [[PTR3]]77; CHECK-NEXT: [[TMP54:%.*]] = select i1 [[TMP38]], ptr [[PTR2]], ptr [[PTR3]]78; CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP39]], ptr [[PTR2]], ptr [[PTR3]]79; CHECK-NEXT: [[TMP56:%.*]] = select i1 [[TMP40]], ptr [[PTR2]], ptr [[PTR3]]80; CHECK-NEXT: [[TMP57:%.*]] = select i1 [[TMP41]], ptr [[PTR2]], ptr [[PTR3]]81; CHECK-NEXT: [[TMP58:%.*]] = select i1 [[TMP42]], ptr [[PTR2]], ptr [[PTR3]]82; CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP43]], ptr [[PTR2]], ptr [[PTR3]]83; CHECK-NEXT: [[TMP60:%.*]] = select i1 [[TMP44]], ptr [[PTR2]], ptr [[PTR3]]84; CHECK-NEXT: [[TMP61:%.*]] = select i1 [[TMP45]], ptr [[PTR2]], ptr [[PTR3]]85; CHECK-NEXT: [[TMP62:%.*]] = select i1 [[TMP46]], ptr [[PTR2]], ptr [[PTR3]]86; CHECK-NEXT: [[TMP63:%.*]] = select i1 [[TMP47]], ptr [[PTR2]], ptr [[PTR3]]87; CHECK-NEXT: [[TMP64:%.*]] = select i1 [[TMP48]], ptr [[PTR2]], ptr [[PTR3]]88; CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP49]], ptr [[PTR2]], ptr [[PTR3]]89; CHECK-NEXT: [[TMP66:%.*]] = select i1 [[TMP50]], ptr [[PTR2]], ptr [[PTR3]]90; CHECK-NEXT: [[TMP67:%.*]] = insertelement <16 x ptr> poison, ptr [[TMP51]], i32 091; CHECK-NEXT: [[TMP68:%.*]] = insertelement <16 x ptr> [[TMP67]], ptr [[TMP52]], i32 192; CHECK-NEXT: [[TMP69:%.*]] = insertelement <16 x ptr> [[TMP68]], ptr [[TMP53]], i32 293; CHECK-NEXT: [[TMP70:%.*]] = insertelement <16 x ptr> [[TMP69]], ptr [[TMP54]], i32 394; CHECK-NEXT: [[TMP71:%.*]] = insertelement <16 x ptr> [[TMP70]], ptr [[TMP55]], i32 495; CHECK-NEXT: [[TMP72:%.*]] = insertelement <16 x ptr> [[TMP71]], ptr [[TMP56]], i32 596; CHECK-NEXT: [[TMP73:%.*]] = insertelement <16 x ptr> [[TMP72]], ptr [[TMP57]], i32 697; CHECK-NEXT: [[TMP74:%.*]] = insertelement <16 x ptr> [[TMP73]], ptr [[TMP58]], i32 798; CHECK-NEXT: [[TMP75:%.*]] = insertelement <16 x ptr> [[TMP74]], ptr [[TMP59]], i32 899; CHECK-NEXT: [[TMP76:%.*]] = insertelement <16 x ptr> [[TMP75]], ptr [[TMP60]], i32 9100; CHECK-NEXT: [[TMP77:%.*]] = insertelement <16 x ptr> [[TMP76]], ptr [[TMP61]], i32 10101; CHECK-NEXT: [[TMP78:%.*]] = insertelement <16 x ptr> [[TMP77]], ptr [[TMP62]], i32 11102; CHECK-NEXT: [[TMP79:%.*]] = insertelement <16 x ptr> [[TMP78]], ptr [[TMP63]], i32 12103; CHECK-NEXT: [[TMP80:%.*]] = insertelement <16 x ptr> [[TMP79]], ptr [[TMP64]], i32 13104; CHECK-NEXT: [[TMP81:%.*]] = insertelement <16 x ptr> [[TMP80]], ptr [[TMP65]], i32 14105; CHECK-NEXT: [[TMP82:%.*]] = insertelement <16 x ptr> [[TMP81]], ptr [[TMP66]], i32 15106; CHECK-NEXT: [[TMP83:%.*]] = select <16 x i1> [[TMP33]], <16 x i1> [[BROADCAST_SPLAT2]], <16 x i1> zeroinitializer107; CHECK-NEXT: [[TMP84:%.*]] = or <16 x i1> [[TMP83]], [[TMP34]]108; CHECK-NEXT: [[PREDPHI:%.*]] = select <16 x i1> [[TMP33]], <16 x ptr> [[BROADCAST_SPLAT]], <16 x ptr> [[TMP82]]109; CHECK-NEXT: [[TMP85:%.*]] = extractelement <16 x i1> [[TMP84]], i32 0110; CHECK-NEXT: br i1 [[TMP85]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]111; CHECK: [[PRED_STORE_IF]]:112; CHECK-NEXT: [[TMP86:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 0113; CHECK-NEXT: store i8 0, ptr [[TMP86]], align 1114; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]115; CHECK: [[PRED_STORE_CONTINUE]]:116; CHECK-NEXT: [[TMP87:%.*]] = extractelement <16 x i1> [[TMP84]], i32 1117; CHECK-NEXT: br i1 [[TMP87]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]118; CHECK: [[PRED_STORE_IF3]]:119; CHECK-NEXT: [[TMP88:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 1120; CHECK-NEXT: store i8 0, ptr [[TMP88]], align 1121; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]122; CHECK: [[PRED_STORE_CONTINUE4]]:123; CHECK-NEXT: [[TMP89:%.*]] = extractelement <16 x i1> [[TMP84]], i32 2124; CHECK-NEXT: br i1 [[TMP89]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]125; CHECK: [[PRED_STORE_IF5]]:126; CHECK-NEXT: [[TMP90:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 2127; CHECK-NEXT: store i8 0, ptr [[TMP90]], align 1128; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]129; CHECK: [[PRED_STORE_CONTINUE6]]:130; CHECK-NEXT: [[TMP91:%.*]] = extractelement <16 x i1> [[TMP84]], i32 3131; CHECK-NEXT: br i1 [[TMP91]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]132; CHECK: [[PRED_STORE_IF7]]:133; CHECK-NEXT: [[TMP92:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 3134; CHECK-NEXT: store i8 0, ptr [[TMP92]], align 1135; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE8]]136; CHECK: [[PRED_STORE_CONTINUE8]]:137; CHECK-NEXT: [[TMP93:%.*]] = extractelement <16 x i1> [[TMP84]], i32 4138; CHECK-NEXT: br i1 [[TMP93]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]139; CHECK: [[PRED_STORE_IF9]]:140; CHECK-NEXT: [[TMP94:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 4141; CHECK-NEXT: store i8 0, ptr [[TMP94]], align 1142; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE10]]143; CHECK: [[PRED_STORE_CONTINUE10]]:144; CHECK-NEXT: [[TMP95:%.*]] = extractelement <16 x i1> [[TMP84]], i32 5145; CHECK-NEXT: br i1 [[TMP95]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]146; CHECK: [[PRED_STORE_IF11]]:147; CHECK-NEXT: [[TMP96:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 5148; CHECK-NEXT: store i8 0, ptr [[TMP96]], align 1149; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE12]]150; CHECK: [[PRED_STORE_CONTINUE12]]:151; CHECK-NEXT: [[TMP97:%.*]] = extractelement <16 x i1> [[TMP84]], i32 6152; CHECK-NEXT: br i1 [[TMP97]], label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14:.*]]153; CHECK: [[PRED_STORE_IF13]]:154; CHECK-NEXT: [[TMP98:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 6155; CHECK-NEXT: store i8 0, ptr [[TMP98]], align 1156; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE14]]157; CHECK: [[PRED_STORE_CONTINUE14]]:158; CHECK-NEXT: [[TMP99:%.*]] = extractelement <16 x i1> [[TMP84]], i32 7159; CHECK-NEXT: br i1 [[TMP99]], label %[[PRED_STORE_IF15:.*]], label %[[PRED_STORE_CONTINUE16:.*]]160; CHECK: [[PRED_STORE_IF15]]:161; CHECK-NEXT: [[TMP100:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 7162; CHECK-NEXT: store i8 0, ptr [[TMP100]], align 1163; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE16]]164; CHECK: [[PRED_STORE_CONTINUE16]]:165; CHECK-NEXT: [[TMP101:%.*]] = extractelement <16 x i1> [[TMP84]], i32 8166; CHECK-NEXT: br i1 [[TMP101]], label %[[PRED_STORE_IF17:.*]], label %[[PRED_STORE_CONTINUE18:.*]]167; CHECK: [[PRED_STORE_IF17]]:168; CHECK-NEXT: [[TMP102:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 8169; CHECK-NEXT: store i8 0, ptr [[TMP102]], align 1170; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE18]]171; CHECK: [[PRED_STORE_CONTINUE18]]:172; CHECK-NEXT: [[TMP103:%.*]] = extractelement <16 x i1> [[TMP84]], i32 9173; CHECK-NEXT: br i1 [[TMP103]], label %[[PRED_STORE_IF19:.*]], label %[[PRED_STORE_CONTINUE20:.*]]174; CHECK: [[PRED_STORE_IF19]]:175; CHECK-NEXT: [[TMP104:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 9176; CHECK-NEXT: store i8 0, ptr [[TMP104]], align 1177; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE20]]178; CHECK: [[PRED_STORE_CONTINUE20]]:179; CHECK-NEXT: [[TMP105:%.*]] = extractelement <16 x i1> [[TMP84]], i32 10180; CHECK-NEXT: br i1 [[TMP105]], label %[[PRED_STORE_IF21:.*]], label %[[PRED_STORE_CONTINUE22:.*]]181; CHECK: [[PRED_STORE_IF21]]:182; CHECK-NEXT: [[TMP106:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 10183; CHECK-NEXT: store i8 0, ptr [[TMP106]], align 1184; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE22]]185; CHECK: [[PRED_STORE_CONTINUE22]]:186; CHECK-NEXT: [[TMP107:%.*]] = extractelement <16 x i1> [[TMP84]], i32 11187; CHECK-NEXT: br i1 [[TMP107]], label %[[PRED_STORE_IF23:.*]], label %[[PRED_STORE_CONTINUE24:.*]]188; CHECK: [[PRED_STORE_IF23]]:189; CHECK-NEXT: [[TMP108:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 11190; CHECK-NEXT: store i8 0, ptr [[TMP108]], align 1191; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE24]]192; CHECK: [[PRED_STORE_CONTINUE24]]:193; CHECK-NEXT: [[TMP109:%.*]] = extractelement <16 x i1> [[TMP84]], i32 12194; CHECK-NEXT: br i1 [[TMP109]], label %[[PRED_STORE_IF25:.*]], label %[[PRED_STORE_CONTINUE26:.*]]195; CHECK: [[PRED_STORE_IF25]]:196; CHECK-NEXT: [[TMP110:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 12197; CHECK-NEXT: store i8 0, ptr [[TMP110]], align 1198; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE26]]199; CHECK: [[PRED_STORE_CONTINUE26]]:200; CHECK-NEXT: [[TMP111:%.*]] = extractelement <16 x i1> [[TMP84]], i32 13201; CHECK-NEXT: br i1 [[TMP111]], label %[[PRED_STORE_IF27:.*]], label %[[PRED_STORE_CONTINUE28:.*]]202; CHECK: [[PRED_STORE_IF27]]:203; CHECK-NEXT: [[TMP112:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 13204; CHECK-NEXT: store i8 0, ptr [[TMP112]], align 1205; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE28]]206; CHECK: [[PRED_STORE_CONTINUE28]]:207; CHECK-NEXT: [[TMP113:%.*]] = extractelement <16 x i1> [[TMP84]], i32 14208; CHECK-NEXT: br i1 [[TMP113]], label %[[PRED_STORE_IF29:.*]], label %[[PRED_STORE_CONTINUE30:.*]]209; CHECK: [[PRED_STORE_IF29]]:210; CHECK-NEXT: [[TMP114:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 14211; CHECK-NEXT: store i8 0, ptr [[TMP114]], align 1212; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE30]]213; CHECK: [[PRED_STORE_CONTINUE30]]:214; CHECK-NEXT: [[TMP115:%.*]] = extractelement <16 x i1> [[TMP84]], i32 15215; CHECK-NEXT: br i1 [[TMP115]], label %[[PRED_STORE_IF31:.*]], label %[[PRED_STORE_CONTINUE32]]216; CHECK: [[PRED_STORE_IF31]]:217; CHECK-NEXT: [[TMP116:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 15218; CHECK-NEXT: store i8 0, ptr [[TMP116]], align 1219; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE32]]220; CHECK: [[PRED_STORE_CONTINUE32]]:221; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16222; CHECK-NEXT: [[TMP117:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96223; CHECK-NEXT: br i1 [[TMP117]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]224; CHECK: [[MIDDLE_BLOCK]]:225; CHECK-NEXT: br label %[[SCALAR_PH:.*]]226; CHECK: [[SCALAR_PH]]:227; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]228; CHECK: [[LOOP_HEADER]]:229; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 96, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]230; CHECK-NEXT: [[EC:%.*]] = icmp ne i64 [[IV]], 99231; CHECK-NEXT: br i1 [[EC]], label %[[LOOP_BODY:.*]], label %[[EXIT:.*]]232; CHECK: [[LOOP_BODY]]:233; CHECK-NEXT: [[ARRAY_PTR:%.*]] = load ptr, ptr [[ARRAY]], align 8234; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ARRAY_PTR]], align 4235; CHECK-NEXT: [[CMP_POS:%.*]] = icmp sgt i32 [[VAL]], 0236; CHECK-NEXT: br i1 [[CMP_POS]], label %[[ELSE:.*]], label %[[THEN:.*]]237; CHECK: [[THEN]]:238; CHECK-NEXT: [[CMP_X:%.*]] = icmp slt i32 [[X]], [[VAL]]239; CHECK-NEXT: [[SELECT_PTR:%.*]] = select i1 [[CMP_X]], ptr [[PTR2]], ptr [[PTR3]]240; CHECK-NEXT: br label %[[MERGE_AND_STORE:.*]]241; CHECK: [[ELSE]]:242; CHECK-NEXT: br i1 [[COND]], label %[[MERGE_AND_STORE]], label %[[LOOP_LATCH]]243; CHECK: [[MERGE_AND_STORE]]:244; CHECK-NEXT: [[PTR_PHI:%.*]] = phi ptr [ [[SELECT_PTR]], %[[THEN]] ], [ [[PTR1]], %[[ELSE]] ]245; CHECK-NEXT: store i8 0, ptr [[PTR_PHI]], align 1246; CHECK-NEXT: br label %[[LOOP_LATCH]]247; CHECK: [[LOOP_LATCH]]:248; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1249; CHECK-NEXT: br label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]250; CHECK: [[EXIT]]:251; CHECK-NEXT: ret void252;253entry:254 %ptr1 = alloca i8, align 1255 %ptr2 = alloca i8, align 1256 %ptr3 = alloca i8, align 1257 call void @init(ptr %ptr1, ptr %ptr2, ptr %ptr3)258 br label %loop.header259 260loop.header:261 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]262 %ec = icmp ne i64 %iv, 99263 br i1 %ec, label %loop.body, label %exit264 265loop.body:266 %array.ptr = load ptr, ptr %array, align 8267 %val = load i32, ptr %array.ptr, align 4268 %cmp.pos = icmp sgt i32 %val, 0269 br i1 %cmp.pos, label %else, label %then270 271then:272 %cmp.x = icmp slt i32 %x, %val273 %select.ptr = select i1 %cmp.x, ptr %ptr2, ptr %ptr3274 br label %merge.and.store275 276else:277 br i1 %cond, label %merge.and.store, label %loop.latch278 279merge.and.store:280 %ptr.phi = phi ptr [ %select.ptr, %then ], [ %ptr1, %else ]281 store i8 0, ptr %ptr.phi, align 1282 br label %loop.latch283 284loop.latch:285 %iv.next = add i64 %iv, 1286 br label %loop.header287 288exit:289 ret void290}291 292define void @replicating_store_with_phi_addr2(ptr noalias %array, ptr noalias %base, i64 %N, i32 %x, i1 %cond) {293; CHECK-LABEL: define void @replicating_store_with_phi_addr2(294; CHECK-SAME: ptr noalias [[ARRAY:%.*]], ptr noalias [[BASE:%.*]], i64 [[N:%.*]], i32 [[X:%.*]], i1 [[COND:%.*]]) {295; CHECK-NEXT: [[ENTRY:.*]]:296; CHECK-NEXT: [[PTR1:%.*]] = alloca i8, align 1297; CHECK-NEXT: [[PTR2:%.*]] = alloca i8, align 1298; CHECK-NEXT: [[PTR3:%.*]] = alloca i8, align 1299; CHECK-NEXT: call void @init(ptr [[PTR1]], ptr [[PTR2]], ptr [[PTR3]])300; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]301; CHECK: [[LOOP_HEADER]]:302; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]303; CHECK-NEXT: [[EC:%.*]] = icmp ne i64 [[IV]], 99304; CHECK-NEXT: br i1 [[EC]], label %[[LOOP_BODY:.*]], label %[[EXIT:.*]]305; CHECK: [[LOOP_BODY]]:306; CHECK-NEXT: [[GEP_ARRAY:%.*]] = getelementptr i32, ptr [[ARRAY]], i64 [[IV]]307; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_ARRAY]], align 8308; CHECK-NEXT: [[L_PTR:%.*]] = load ptr, ptr [[BASE]], align 4309; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[L_PTR]], align 4310; CHECK-NEXT: [[CMP_POS:%.*]] = icmp sgt i32 [[VAL]], 0311; CHECK-NEXT: br i1 [[CMP_POS]], label %[[ELSE:.*]], label %[[THEN:.*]]312; CHECK: [[THEN]]:313; CHECK-NEXT: [[SEL_CMP:%.*]] = icmp slt i32 [[X]], [[L]]314; CHECK-NEXT: [[SELECT_PTR:%.*]] = select i1 [[SEL_CMP]], ptr [[PTR2]], ptr [[PTR3]]315; CHECK-NEXT: br label %[[MERGE_AND_STORE:.*]]316; CHECK: [[ELSE]]:317; CHECK-NEXT: br i1 [[COND]], label %[[MERGE_AND_STORE]], label %[[LOOP_LATCH]]318; CHECK: [[MERGE_AND_STORE]]:319; CHECK-NEXT: [[PTR_PHI:%.*]] = phi ptr [ [[SELECT_PTR]], %[[THEN]] ], [ [[PTR1]], %[[ELSE]] ]320; CHECK-NEXT: store i8 0, ptr [[PTR_PHI]], align 1321; CHECK-NEXT: br label %[[LOOP_LATCH]]322; CHECK: [[LOOP_LATCH]]:323; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1324; CHECK-NEXT: br label %[[LOOP_HEADER]]325; CHECK: [[EXIT]]:326; CHECK-NEXT: ret void327;328entry:329 %ptr1 = alloca i8, align 1330 %ptr2 = alloca i8, align 1331 %ptr3 = alloca i8, align 1332 call void @init(ptr %ptr1, ptr %ptr2, ptr %ptr3)333 br label %loop.header334 335loop.header:336 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]337 %ec = icmp ne i64 %iv, 99338 br i1 %ec, label %loop.body, label %exit339 340loop.body:341 %gep.array = getelementptr i32, ptr %array, i64 %iv342 %l = load i32, ptr %gep.array, align 8343 %l.ptr = load ptr, ptr %base, align 4344 %val = load i32, ptr %l.ptr, align 4345 %cmp.pos = icmp sgt i32 %val, 0346 br i1 %cmp.pos, label %else, label %then347 348then:349 %sel.cmp = icmp slt i32 %x, %l350 %select.ptr = select i1 %sel.cmp, ptr %ptr2, ptr %ptr3351 br label %merge.and.store352 353else:354 br i1 %cond, label %merge.and.store, label %loop.latch355 356merge.and.store:357 %ptr.phi = phi ptr [ %select.ptr, %then ], [ %ptr1, %else ]358 store i8 0, ptr %ptr.phi, align 1359 br label %loop.latch360 361loop.latch:362 %iv.next = add i64 %iv, 1363 br label %loop.header364 365exit:366 ret void367}368 369attributes #0 = { "target-cpu"="znver2" }370 371!0 = distinct !{!0, !1}372!1 = !{!"llvm.loop.vectorize.enable", i1 true}373;.374; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}375; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}376; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}377; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}378;.379