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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -p loop-vectorize -force-vector-width=4 -mtriple=x86_64-apple-macosx -mcpu=skylake-avx512 -S %s | FileCheck %s3 4define void @load_store_interleave_group_with_gaps(ptr noalias %data, i64 noundef %n) {5; CHECK-LABEL: define void @load_store_interleave_group_with_gaps(6; CHECK-SAME: ptr noalias [[DATA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: [[ENTRY:.*]]:8; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 49; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]10; CHECK: [[VECTOR_PH]]:11; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 412; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]13; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]14; CHECK: [[VECTOR_BODY]]:15; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]16; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]17; CHECK-NEXT: [[TMP0:%.*]] = shl nsw <4 x i64> [[VEC_IND]], splat (i64 2)18; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[DATA]], <4 x i64> [[TMP0]]19; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x ptr> [[TMP1]], i32 020; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <16 x i64>, ptr [[TMP2]], align 821; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <16 x i64> [[WIDE_VEC]], <16 x i64> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>22; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <16 x i64> [[WIDE_VEC]], <16 x i64> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>23; CHECK-NEXT: [[STRIDED_VEC2:%.*]] = shufflevector <16 x i64> [[WIDE_VEC]], <16 x i64> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>24; CHECK-NEXT: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> [[STRIDED_VEC]], <4 x ptr> align 8 [[TMP1]], <4 x i1> splat (i1 true))25; CHECK-NEXT: [[TMP3:%.*]] = or disjoint <4 x i64> [[TMP0]], splat (i64 1)26; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DATA]], <4 x i64> [[TMP3]]27; CHECK-NEXT: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> [[STRIDED_VEC1]], <4 x ptr> align 8 [[TMP4]], <4 x i1> splat (i1 true))28; CHECK-NEXT: [[TMP5:%.*]] = or disjoint <4 x i64> [[TMP0]], splat (i64 3)29; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[DATA]], <4 x i64> [[TMP5]]30; CHECK-NEXT: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> [[STRIDED_VEC2]], <4 x ptr> align 8 [[TMP6]], <4 x i1> splat (i1 true))31; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 432; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)33; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]34; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]35; CHECK: [[MIDDLE_BLOCK]]:36; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]37; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]38; CHECK: [[SCALAR_PH]]:39; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]40; CHECK-NEXT: br label %[[LOOP:.*]]41; CHECK: [[LOOP]]:42; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]43; CHECK-NEXT: [[MUL_4:%.*]] = shl nsw i64 [[IV]], 244; CHECK-NEXT: [[DATA_0:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[MUL_4]]45; CHECK-NEXT: [[L_0:%.*]] = load i64, ptr [[DATA_0]], align 846; CHECK-NEXT: store i64 [[L_0]], ptr [[DATA_0]], align 847; CHECK-NEXT: [[ADD_1:%.*]] = or disjoint i64 [[MUL_4]], 148; CHECK-NEXT: [[DATA_1:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[ADD_1]]49; CHECK-NEXT: [[L_1:%.*]] = load i64, ptr [[DATA_1]], align 850; CHECK-NEXT: store i64 [[L_1]], ptr [[DATA_1]], align 851; CHECK-NEXT: [[ADD_3:%.*]] = or disjoint i64 [[MUL_4]], 352; CHECK-NEXT: [[DATA_3:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[ADD_3]]53; CHECK-NEXT: [[L_3:%.*]] = load i64, ptr [[DATA_3]], align 854; CHECK-NEXT: store i64 [[L_3]], ptr [[DATA_3]], align 855; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 156; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]57; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]58; CHECK: [[EXIT]]:59; CHECK-NEXT: ret void60;61entry:62 br label %loop63 64loop:65 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]66 %mul.4 = shl nsw i64 %iv, 267 %data.0 = getelementptr inbounds i64, ptr %data, i64 %mul.468 %l.0 = load i64, ptr %data.0, align 869 store i64 %l.0, ptr %data.0, align 870 %add.1 = or disjoint i64 %mul.4, 171 %data.1 = getelementptr inbounds i64, ptr %data, i64 %add.172 %l.1 = load i64, ptr %data.1, align 873 store i64 %l.1, ptr %data.1, align 874 %add.3 = or disjoint i64 %mul.4, 375 %data.3 = getelementptr inbounds i64, ptr %data, i64 %add.376 %l.3 = load i64, ptr %data.3, align 877 store i64 %l.3, ptr %data.3, align 878 %iv.next = add nuw nsw i64 %iv, 179 %ec = icmp eq i64 %iv.next, %n80 br i1 %ec, label %exit, label %loop81 82exit:83 ret void84}85