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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "middle.block:" --version 52; RUN: opt -passes=loop-vectorize -S %s | FileCheck %s3 4target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"5target triple = "x86_64-unknown-linux-gnu"6 7@inc = global float 5.000000e-01, align 48 9;float inc = 0.5;10;void foo(ptr A, unsigned N) {11;12; for (unsigned i=0; i<N; i++){13; A[i] += inc;14; }15;}16 17define void @foo(ptr nocapture noalias %A, i64 %N) #0 {18; CHECK-LABEL: define void @foo(19; CHECK-SAME: ptr noalias captures(none) [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {20; CHECK-NEXT: [[ENTRY:.*:]]21; CHECK-NEXT: br label %[[VECTOR_PH:.*]]22; CHECK: [[VECTOR_PH]]:23; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]24; CHECK: [[VECTOR_BODY]]:25; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr @inc, align 426; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x float> poison, float [[TMP1]], i64 027; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT]], <8 x float> poison, <8 x i32> zeroinitializer28; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[A]], i64 829; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, ptr [[A]], i64 1630; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr [[A]], i64 2431; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x float>, ptr [[A]], align 432; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x float>, ptr [[TMP4]], align 433; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x float>, ptr [[TMP5]], align 434; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x float>, ptr [[TMP6]], align 435; CHECK-NEXT: [[TMP7:%.*]] = fadd <8 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]36; CHECK-NEXT: [[TMP8:%.*]] = fadd <8 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD2]]37; CHECK-NEXT: [[TMP9:%.*]] = fadd <8 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD3]]38; CHECK-NEXT: [[TMP10:%.*]] = fadd <8 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD4]]39; CHECK-NEXT: store <8 x float> [[TMP7]], ptr [[A]], align 440; CHECK-NEXT: store <8 x float> [[TMP8]], ptr [[TMP4]], align 441; CHECK-NEXT: store <8 x float> [[TMP9]], ptr [[TMP5]], align 442; CHECK-NEXT: store <8 x float> [[TMP10]], ptr [[TMP6]], align 443; CHECK-NEXT: br label %[[MIDDLE_BLOCK:.*]]44; CHECK: [[MIDDLE_BLOCK]]:45;46entry:47 br label %loop48 49loop:50 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]51 %l.inc = load float, ptr @inc, align 452 %gep.A = getelementptr inbounds float, ptr %A, i64 %iv53 %l.A = load float, ptr %gep.A, align 454 %add = fadd float %l.inc, %l.A55 store float %add, ptr %gep.A, align 456 %iv.next = add nuw nsw i64 %iv, 157 %ec = icmp eq i64 %iv.next, 3258 br i1 %ec, label %exit, label %loop59 60exit:61 ret void62}63 64define void @uniform_load_can_fold_users(ptr noalias %src, ptr %dst, i64 %start, double %d) {65; CHECK-LABEL: define void @uniform_load_can_fold_users(66; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr [[DST:%.*]], i64 [[START:%.*]], double [[D:%.*]]) {67; CHECK-NEXT: [[ENTRY:.*]]:68; CHECK-NEXT: br label %[[LOOP:.*]]69; CHECK: [[LOOP]]:70; CHECK-NEXT: [[TMP4:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP]] ]71; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[START]], %[[ENTRY]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP]] ]72; CHECK-NEXT: [[TMP5:%.*]] = load double, ptr [[SRC]], align 873; CHECK-NEXT: [[TMP7:%.*]] = fmul double [[TMP5]], 9.000000e+0074; CHECK-NEXT: [[TMP8:%.*]] = fdiv double [[TMP7]], [[D]]75; CHECK-NEXT: [[TMP10:%.*]] = sub i64 [[TMP4]], 176; CHECK-NEXT: [[TMP12:%.*]] = getelementptr double, ptr [[DST]], i64 [[TMP4]]77; CHECK-NEXT: [[TMP14:%.*]] = getelementptr double, ptr [[TMP12]], i64 [[TMP10]]78; CHECK-NEXT: store double [[TMP8]], ptr [[TMP14]], align 879; CHECK-NEXT: [[IV_1_NEXT]] = add i64 [[TMP4]], 180; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], -181; CHECK-NEXT: [[EC:%.*]] = icmp sgt i64 [[IV_2]], 082; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT:.*]]83; CHECK: [[EXIT]]:84; CHECK-NEXT: ret void85;86entry:87 br label %loop88 89loop:90 %iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ]91 %iv.2 = phi i64 [ %start, %entry ], [ %iv.2.next, %loop ]92 %l = load double, ptr %src, align 893 %m = fmul double %l, 9.094 %div = fdiv double %m, %d95 %sub = sub i64 %iv.1, 196 %gep.1 = getelementptr double, ptr %dst, i64 %iv.197 %gep.2 = getelementptr double, ptr %gep.1, i64 %sub98 store double %div, ptr %gep.2, align 899 %iv.1.next = add i64 %iv.1, 1100 %iv.2.next = add i64 %iv.2, -1101 %ec = icmp sgt i64 %iv.2, 0102 br i1 %ec , label %loop, label %exit103 104exit:105 ret void106}107 108attributes #0 = { "target-cpu"="core-avx2" }109