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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=loop-vectorize,dce,instcombine -force-vector-width=2 -force-vector-interleave=2 < %s | FileCheck %s3 4target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"5 6;PR 15830.7 8; When scalarizing stores we need to preserve the original order.9; Make sure that we are extracting in the correct order (0101, and not 0011).10 11define void @foo(ptr nocapture %A) {12; CHECK-LABEL: @foo(13; CHECK-NEXT: entry:14; CHECK-NEXT: br label [[VECTOR_PH:%.*]]15; CHECK: vector.ph:16; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]17; CHECK: vector.body:18; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]19; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]20; CHECK-NEXT: [[TMP0:%.*]] = shl nsw <2 x i64> [[VEC_IND]], splat (i64 2)21; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP0]], i64 022; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[TMP0]], i64 123; CHECK-NEXT: [[STEP_ADD:%.*]] = shl <2 x i64> [[VEC_IND]], splat (i64 2)24; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i64> [[STEP_ADD]], splat (i64 8)25; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[TMP1]], i64 026; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i64> [[TMP1]], i64 127; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[TMP4]]28; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP6]]29; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP8]]30; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP11]]31; CHECK-NEXT: store i32 4, ptr [[TMP5]], align 432; CHECK-NEXT: store i32 4, ptr [[TMP7]], align 433; CHECK-NEXT: store i32 4, ptr [[TMP9]], align 434; CHECK-NEXT: store i32 4, ptr [[TMP12]], align 435; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 436; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], splat (i64 4)37; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000038; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]39; CHECK: middle.block:40; CHECK-NEXT: br label [[FOR_BODY:%.*]]41; CHECK: for.end:42; CHECK-NEXT: ret void43;44entry:45 br label %for.body46 47for.body:48 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]49 %0 = shl nsw i64 %indvars.iv, 250 %arrayidx = getelementptr inbounds i32, ptr %A, i64 %051 store i32 4, ptr %arrayidx, align 452 %indvars.iv.next = add i64 %indvars.iv, 153 %lftr.wideiv = trunc i64 %indvars.iv.next to i3254 %exitcond = icmp eq i32 %lftr.wideiv, 1000055 br i1 %exitcond, label %for.end, label %for.body56 57for.end:58 ret void59}60 61 62