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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=loop-vectorize -force-vector-width=4 < %s | FileCheck %s3 4; This is a regression test. Without the fix it crashes on SSAUpdater due to5; LoopVectroizer created a phi node placeholder without incoming values but6; SSAUpdater expects that phi node is completely filled.7 8target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"9define void @test(i32 %arg, i32 %L1.limit, i32 %L2.switch, i1 %c, ptr %dst) {10; CHECK-LABEL: @test(11; CHECK-NEXT: L1.preheader:12; CHECK-NEXT: [[TMP0:%.*]] = sub i32 -1, [[ARG:%.*]]13; CHECK-NEXT: br label [[L1_HEADER:%.*]]14; CHECK: L1.header:15; CHECK-NEXT: [[INDUCTION_IV:%.*]] = phi i32 [ [[INDUCTION_IV_NEXT:%.*]], [[L1_BACKEDGE:%.*]] ], [ [[TMP0]], [[L1_PREHEADER:%.*]] ]16; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[L1_BACKEDGE]] ], [ 0, [[L1_PREHEADER]] ]17; CHECK-NEXT: [[L1_SUM:%.*]] = phi i32 [ [[ARG]], [[L1_PREHEADER]] ], [ [[L1_SUM_NEXT:%.*]], [[L1_BACKEDGE]] ]18; CHECK-NEXT: [[L1_IV:%.*]] = phi i32 [ 1, [[L1_PREHEADER]] ], [ [[L1_IV_NEXT:%.*]], [[L1_BACKEDGE]] ]19; CHECK-NEXT: [[TMP1:%.*]] = mul nsw i32 [[INDVAR]], -120; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -221; CHECK-NEXT: br i1 [[C:%.*]], label [[L1_BACKEDGE]], label [[L1_EARLY_EXIT:%.*]]22; CHECK: L1.backedge:23; CHECK-NEXT: [[L1_SUM_NEXT]] = add i32 [[L1_IV]], [[L1_SUM]]24; CHECK-NEXT: [[L1_IV_NEXT]] = add nuw nsw i32 [[L1_IV]], 125; CHECK-NEXT: [[L1_EXIT_COND:%.*]] = icmp ult i32 [[L1_IV_NEXT]], [[L1_LIMIT:%.*]]26; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 127; CHECK-NEXT: [[INDUCTION_IV_NEXT]] = add i32 [[INDUCTION_IV]], [[TMP2]]28; CHECK-NEXT: br i1 [[L1_EXIT_COND]], label [[L1_HEADER]], label [[L1_EXIT:%.*]]29; CHECK: L1.early.exit:30; CHECK-NEXT: ret void31; CHECK: L1.exit:32; CHECK-NEXT: [[L1_EXIT_VAL:%.*]] = phi i32 [ [[L1_SUM_NEXT]], [[L1_BACKEDGE]] ]33; CHECK-NEXT: br label [[L2_HEADER:%.*]]34; CHECK: L2.header.loopexit:35; CHECK-NEXT: br label [[L2_HEADER_BACKEDGE:%.*]]36; CHECK: L2.header:37; CHECK-NEXT: switch i32 [[L2_SWITCH:%.*]], label [[L2_HEADER_BACKEDGE]] [38; CHECK-NEXT: i32 8, label [[L2_EXIT:%.*]]39; CHECK-NEXT: i32 20, label [[L2_INNER_HEADER_PREHEADER:%.*]]40; CHECK-NEXT: ]41; CHECK: L2.header.backedge:42; CHECK-NEXT: br label [[L2_HEADER]]43; CHECK: L2.Inner.header.preheader:44; CHECK-NEXT: br label [[VECTOR_PH:%.*]]45; CHECK: vector.ph:46; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[L1_EXIT_VAL]], i64 047; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer48; CHECK-NEXT: [[DOTSPLATINSERT1:%.*]] = insertelement <4 x i32> poison, i32 [[INDUCTION_IV]], i64 049; CHECK-NEXT: [[DOTSPLAT1:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT1]], <4 x i32> poison, <4 x i32> zeroinitializer50; CHECK-NEXT: [[TMP4:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[DOTSPLAT1]]51; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> splat (i32 1), [[TMP4]]52; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[INDUCTION_IV]], 453; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[TMP5]], i64 054; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer55; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]56; CHECK: vector.body:57; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]58; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]59; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]]60; CHECK-NEXT: [[TMP7:%.*]] = sub <4 x i32> [[VEC_IND]], [[DOTSPLAT]]61; CHECK-NEXT: [[TMP8:%.*]] = sext <4 x i32> [[TMP7]] to <4 x i64>62; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[DST:%.*]], i64 [[OFFSET_IDX]]63; CHECK-NEXT: store <4 x i64> [[TMP8]], ptr [[TMP9]], align 864; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 465; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]]66; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1267; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]68; CHECK: middle.block:69; CHECK-NEXT: br label [[L2_INNER_HEADER:%.*]]70; CHECK: L2.exit:71; CHECK-NEXT: ret void72;73L1.preheader:74 br label %L1.header75 76L1.header: ; preds = %L1.preheader, %L1.backedge77 %L1.sum = phi i32 [ %arg, %L1.preheader ], [ %L1.sum.next, %L1.backedge ]78 %L1.iv = phi i32 [ 1, %L1.preheader ], [ %L1.iv.next, %L1.backedge ]79 br i1 %c, label %L1.backedge, label %L1.early.exit80 81L1.backedge: ; preds = %L1.header82 %L1.sum.next = add i32 %L1.iv, %L1.sum83 %L1.iv.next = add nuw nsw i32 %L1.iv, 184 %L1.exit.cond = icmp ult i32 %L1.iv.next, %L1.limit85 br i1 %L1.exit.cond, label %L1.header, label %L1.exit86 87L1.early.exit: ; preds = %L1.header88 ret void89 90L1.exit: ; preds = %L1.backedge91 %L1.exit.val = phi i32 [ %L1.sum.next, %L1.backedge ]92 br label %L2.header93 94L2.header: ; preds = %L2.Inner.header, %L1.exit, %L2.header95 switch i32 %L2.switch, label %L2.header [96 i32 8, label %L2.exit97 i32 20, label %L2.Inner.header98 ]99 100L2.Inner.header: ; preds = %L2.Inner.header, %L2.header101 %L2.accum = phi i32 [ %L2.accum.next, %L2.Inner.header ], [ 1, %L2.header ]102 %L2.iv = phi i64 [ %L2.iv.next, %L2.Inner.header ], [ 1, %L2.header ]103 %L2.accum.next = sub i32 %L2.accum, %L1.exit.val104 %L2.dummy.but.need.it = sext i32 %L2.accum.next to i64105 %gep = getelementptr inbounds i64 , ptr %dst, i64 %L2.iv106 store i64 %L2.dummy.but.need.it, ptr %gep107 %L2.iv.next = add nuw nsw i64 %L2.iv, 1108 %L2.exit_cond = icmp ugt i64 %L2.iv, 11109 br i1 %L2.exit_cond, label %L2.header, label %L2.Inner.header110 111L2.exit: ; preds = %L2.header112 ret void113}114 115