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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -scalable-vectorization=on -force-vector-width=1 -force-target-supports-scalable-vectors=true -S %s | FileCheck %s3 4target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"5 6 7define i64 @pr97452_scalable_vf1_for_live_out(ptr %src) {8; CHECK-LABEL: define i64 @pr97452_scalable_vf1_for_live_out(9; CHECK-SAME: ptr [[SRC:%.*]]) {10; CHECK-NEXT: [[ENTRY:.*]]:11; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()12; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 23, [[TMP0]]13; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]14; CHECK: [[VECTOR_PH]]:15; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()16; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 23, [[TMP1]]17; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 23, [[N_MOD_VF]]18; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vscale.i32()19; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP3]], 120; CHECK-NEXT: [[VECTOR_RECUR_INIT:%.*]] = insertelement <vscale x 1 x i64> poison, i64 0, i32 [[TMP4]]21; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]22; CHECK: [[VECTOR_BODY]]:23; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]24; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <vscale x 1 x i64> [ [[VECTOR_RECUR_INIT]], %[[VECTOR_PH]] ], [ [[WIDE_LOAD:%.*]], %[[VECTOR_BODY]] ]25; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[INDEX]]26; CHECK-NEXT: [[WIDE_LOAD]] = load <vscale x 1 x i64>, ptr [[TMP5]], align 827; CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 1 x i64> @llvm.vector.splice.nxv1i64(<vscale x 1 x i64> [[VECTOR_RECUR]], <vscale x 1 x i64> [[WIDE_LOAD]], i32 -1)28; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]]29; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]30; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]31; CHECK: [[MIDDLE_BLOCK]]:32; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vscale.i32()33; CHECK-NEXT: [[TMP10:%.*]] = sub i32 [[TMP9]], 134; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <vscale x 1 x i64> [[WIDE_LOAD]], i32 [[TMP10]]35; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.vscale.i32()36; CHECK-NEXT: [[TMP13:%.*]] = sub i32 [[TMP12]], 137; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x i64> [[TMP7]], i32 [[TMP13]]38; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 23, [[N_VEC]]39; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]40; CHECK: [[SCALAR_PH]]:41; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]42; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]43; CHECK-NEXT: br label %[[LOOP:.*]]44; CHECK: [[LOOP]]:45; CHECK-NEXT: [[FOR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[L:%.*]], %[[LOOP]] ]46; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]47; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 148; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[IV]]49; CHECK-NEXT: [[L]] = load i64, ptr [[GEP]], align 850; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 2251; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]52; CHECK: [[EXIT]]:53; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[FOR]], %[[LOOP]] ], [ [[TMP14]], %[[MIDDLE_BLOCK]] ]54; CHECK-NEXT: ret i64 [[RES]]55;56entry:57 br label %loop58 59loop:60 %for = phi i64 [ 0, %entry ], [ %l, %loop ]61 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]62 %iv.next = add i64 %iv, 163 %gep = getelementptr inbounds i64, ptr %src, i64 %iv64 %l = load i64, ptr %gep, align 865 %ec = icmp eq i64 %iv, 2266 br i1 %ec, label %exit, label %loop67 68exit:69 %res = phi i64 [ %for, %loop ]70 ret i64 %res71}72 73 74define void @pr97452_scalable_vf1_for_no_live_out(ptr %src, ptr noalias %dst) {75; CHECK-LABEL: define void @pr97452_scalable_vf1_for_no_live_out(76; CHECK-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]]) {77; CHECK-NEXT: [[ENTRY:.*]]:78; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()79; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 23, [[TMP0]]80; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]81; CHECK: [[VECTOR_PH]]:82; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()83; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 23, [[TMP1]]84; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 23, [[N_MOD_VF]]85; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vscale.i32()86; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP3]], 187; CHECK-NEXT: [[VECTOR_RECUR_INIT:%.*]] = insertelement <vscale x 1 x i64> poison, i64 0, i32 [[TMP4]]88; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]89; CHECK: [[VECTOR_BODY]]:90; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]91; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <vscale x 1 x i64> [ [[VECTOR_RECUR_INIT]], %[[VECTOR_PH]] ], [ [[WIDE_LOAD:%.*]], %[[VECTOR_BODY]] ]92; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[INDEX]]93; CHECK-NEXT: [[WIDE_LOAD]] = load <vscale x 1 x i64>, ptr [[TMP5]], align 894; CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 1 x i64> @llvm.vector.splice.nxv1i64(<vscale x 1 x i64> [[VECTOR_RECUR]], <vscale x 1 x i64> [[WIDE_LOAD]], i32 -1)95; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[INDEX]]96; CHECK-NEXT: store <vscale x 1 x i64> [[TMP7]], ptr [[TMP8]], align 897; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]]98; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]99; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]100; CHECK: [[MIDDLE_BLOCK]]:101; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.vscale.i32()102; CHECK-NEXT: [[TMP12:%.*]] = sub i32 [[TMP11]], 1103; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <vscale x 1 x i64> [[WIDE_LOAD]], i32 [[TMP12]]104; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 23, [[N_VEC]]105; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]106; CHECK: [[SCALAR_PH]]:107; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]108; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]109; CHECK-NEXT: br label %[[LOOP:.*]]110; CHECK: [[LOOP]]:111; CHECK-NEXT: [[FOR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[L:%.*]], %[[LOOP]] ]112; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]113; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1114; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[IV]]115; CHECK-NEXT: [[L]] = load i64, ptr [[GEP]], align 8116; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[IV]]117; CHECK-NEXT: store i64 [[FOR]], ptr [[GEP_DST]], align 8118; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 22119; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]120; CHECK: [[EXIT]]:121; CHECK-NEXT: ret void122;123entry:124 br label %loop125 126loop:127 %for = phi i64 [ 0, %entry ], [ %l, %loop ]128 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]129 %iv.next = add i64 %iv, 1130 %gep = getelementptr inbounds i64, ptr %src, i64 %iv131 %l = load i64, ptr %gep, align 8132 %gep.dst = getelementptr inbounds i64, ptr %dst, i64 %iv133 store i64 %for, ptr %gep.dst134 %ec = icmp eq i64 %iv, 22135 br i1 %ec, label %exit, label %loop136 137exit:138 ret void139}140;.141; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}142; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}143; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}144; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}145; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}146; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}147;.148