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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=loop-vectorize -force-vector-width=4 -S | FileCheck %s3 4; The function finds the smallest value from a float vector.5; Check if vectorization is enabled by instruction flag `fcmp nnan`.6 7define float @minloop(ptr nocapture readonly %arg) {8; CHECK-LABEL: @minloop(9; CHECK-NEXT: top:10; CHECK-NEXT: [[T:%.*]] = load float, ptr [[ARG:%.*]], align 411; CHECK-NEXT: br label [[LOOP:%.*]]12; CHECK: loop:13; CHECK-NEXT: [[T1:%.*]] = phi i64 [ [[T7:%.*]], [[LOOP]] ], [ 1, [[TOP:%.*]] ]14; CHECK-NEXT: [[T2:%.*]] = phi float [ [[T6:%.*]], [[LOOP]] ], [ [[T]], [[TOP]] ]15; CHECK-NEXT: [[T3:%.*]] = getelementptr float, ptr [[ARG]], i64 [[T1]]16; CHECK-NEXT: [[T4:%.*]] = load float, ptr [[T3]], align 417; CHECK-NEXT: [[T5:%.*]] = fcmp nnan olt float [[T2]], [[T4]]18; CHECK-NEXT: [[T6]] = select i1 [[T5]], float [[T2]], float [[T4]]19; CHECK-NEXT: [[T7]] = add i64 [[T1]], 120; CHECK-NEXT: [[T8:%.*]] = icmp eq i64 [[T7]], 6553721; CHECK-NEXT: br i1 [[T8]], label [[OUT:%.*]], label [[LOOP]]22; CHECK: out:23; CHECK-NEXT: [[T6_LCSSA:%.*]] = phi float [ [[T6]], [[LOOP]] ]24; CHECK-NEXT: ret float [[T6_LCSSA]]25;26top:27 %t = load float, ptr %arg28 br label %loop29 30loop: ; preds = %loop, %top31 %t1 = phi i64 [ %t7, %loop ], [ 1, %top ]32 %t2 = phi float [ %t6, %loop ], [ %t, %top ]33 %t3 = getelementptr float, ptr %arg, i64 %t134 %t4 = load float, ptr %t3, align 435 %t5 = fcmp nnan olt float %t2, %t436 %t6 = select i1 %t5, float %t2, float %t437 %t7 = add i64 %t1, 138 %t8 = icmp eq i64 %t7, 6553739 br i1 %t8, label %out, label %loop40 41out: ; preds = %loop42 ret float %t643}44 45; Check if vectorization is still enabled by function attribute.46 47define float @minloopattr(ptr nocapture readonly %arg) #0 {48; CHECK-LABEL: @minloopattr(49; CHECK-NEXT: top:50; CHECK-NEXT: [[T:%.*]] = load float, ptr [[ARG:%.*]], align 451; CHECK-NEXT: br label [[VECTOR_PH:%.*]]52; CHECK: vector.ph:53; CHECK-NEXT: [[MINMAX_IDENT_SPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[T]], i64 054; CHECK-NEXT: [[MINMAX_IDENT_SPLAT:%.*]] = shufflevector <4 x float> [[MINMAX_IDENT_SPLATINSERT]], <4 x float> poison, <4 x i32> zeroinitializer55; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]56; CHECK: vector.body:57; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]58; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ [[MINMAX_IDENT_SPLAT]], [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]59; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]]60; CHECK-NEXT: [[TMP1:%.*]] = getelementptr float, ptr [[ARG]], i64 [[OFFSET_IDX]]61; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP1]], align 462; CHECK-NEXT: [[TMP3:%.*]] = fcmp olt <4 x float> [[VEC_PHI]], [[WIDE_LOAD]]63; CHECK-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x float> [[VEC_PHI]], <4 x float> [[WIDE_LOAD]]64; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 465; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 6553666; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]67; CHECK: middle.block:68; CHECK-NEXT: [[TMP6:%.*]] = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> [[TMP4]])69; CHECK-NEXT: br label [[LOOP:%.*]]70; CHECK: out:71; CHECK-NEXT: ret float [[TMP6]]72;73top:74 %t = load float, ptr %arg75 br label %loop76 77loop: ; preds = %loop, %top78 %t1 = phi i64 [ %t7, %loop ], [ 1, %top ]79 %t2 = phi float [ %t6, %loop ], [ %t, %top ]80 %t3 = getelementptr float, ptr %arg, i64 %t181 %t4 = load float, ptr %t3, align 482 %t5 = fcmp olt float %t2, %t483 %t6 = select i1 %t5, float %t2, float %t484 %t7 = add i64 %t1, 185 %t8 = icmp eq i64 %t7, 6553786 br i1 %t8, label %out, label %loop87 88out: ; preds = %loop89 ret float %t690}91 92; Check if vectorization is prevented without the flag or attribute.93 94define float @minloopnovec(ptr nocapture readonly %arg) {95; CHECK-LABEL: @minloopnovec(96; CHECK-NEXT: top:97; CHECK-NEXT: [[T:%.*]] = load float, ptr [[ARG:%.*]], align 498; CHECK-NEXT: br label [[LOOP:%.*]]99; CHECK: loop:100; CHECK-NEXT: [[T1:%.*]] = phi i64 [ [[T7:%.*]], [[LOOP]] ], [ 1, [[TOP:%.*]] ]101; CHECK-NEXT: [[T2:%.*]] = phi float [ [[T6:%.*]], [[LOOP]] ], [ [[T]], [[TOP]] ]102; CHECK-NEXT: [[T3:%.*]] = getelementptr float, ptr [[ARG]], i64 [[T1]]103; CHECK-NEXT: [[T4:%.*]] = load float, ptr [[T3]], align 4104; CHECK-NEXT: [[T5:%.*]] = fcmp olt float [[T2]], [[T4]]105; CHECK-NEXT: [[T6]] = select i1 [[T5]], float [[T2]], float [[T4]]106; CHECK-NEXT: [[T7]] = add i64 [[T1]], 1107; CHECK-NEXT: [[T8:%.*]] = icmp eq i64 [[T7]], 65537108; CHECK-NEXT: br i1 [[T8]], label [[OUT:%.*]], label [[LOOP]]109; CHECK: out:110; CHECK-NEXT: [[T6_LCSSA:%.*]] = phi float [ [[T6]], [[LOOP]] ]111; CHECK-NEXT: ret float [[T6_LCSSA]]112;113top:114 %t = load float, ptr %arg115 br label %loop116 117loop: ; preds = %loop, %top118 %t1 = phi i64 [ %t7, %loop ], [ 1, %top ]119 %t2 = phi float [ %t6, %loop ], [ %t, %top ]120 %t3 = getelementptr float, ptr %arg, i64 %t1121 %t4 = load float, ptr %t3, align 4122 %t5 = fcmp olt float %t2, %t4123 %t6 = select i1 %t5, float %t2, float %t4124 %t7 = add i64 %t1, 1125 %t8 = icmp eq i64 %t7, 65537126 br i1 %t8, label %out, label %loop127 128out: ; preds = %loop129 ret float %t6130}131 132; This test is checking that we don't vectorize when only one of the required attributes is set.133; Note that this test should not vectorize even after switching to IR-level FMF.134define float @minloopmissingnsz(ptr nocapture readonly %arg) #1 {135; CHECK-LABEL: @minloopmissingnsz(136; CHECK-NEXT: top:137; CHECK-NEXT: [[T:%.*]] = load float, ptr [[ARG:%.*]], align 4138; CHECK-NEXT: br label [[LOOP:%.*]]139; CHECK: loop:140; CHECK-NEXT: [[T1:%.*]] = phi i64 [ [[T7:%.*]], [[LOOP]] ], [ 1, [[TOP:%.*]] ]141; CHECK-NEXT: [[T2:%.*]] = phi float [ [[T6:%.*]], [[LOOP]] ], [ [[T]], [[TOP]] ]142; CHECK-NEXT: [[T3:%.*]] = getelementptr float, ptr [[ARG]], i64 [[T1]]143; CHECK-NEXT: [[T4:%.*]] = load float, ptr [[T3]], align 4144; CHECK-NEXT: [[T5:%.*]] = fcmp olt float [[T2]], [[T4]]145; CHECK-NEXT: [[T6]] = select i1 [[T5]], float [[T2]], float [[T4]]146; CHECK-NEXT: [[T7]] = add i64 [[T1]], 1147; CHECK-NEXT: [[T8:%.*]] = icmp eq i64 [[T7]], 65537148; CHECK-NEXT: br i1 [[T8]], label [[OUT:%.*]], label [[LOOP]]149; CHECK: out:150; CHECK-NEXT: [[T6_LCSSA:%.*]] = phi float [ [[T6]], [[LOOP]] ]151; CHECK-NEXT: ret float [[T6_LCSSA]]152;153top:154 %t = load float, ptr %arg155 br label %loop156 157loop: ; preds = %loop, %top158 %t1 = phi i64 [ %t7, %loop ], [ 1, %top ]159 %t2 = phi float [ %t6, %loop ], [ %t, %top ]160 %t3 = getelementptr float, ptr %arg, i64 %t1161 %t4 = load float, ptr %t3, align 4162 %t5 = fcmp olt float %t2, %t4163 %t6 = select i1 %t5, float %t2, float %t4164 %t7 = add i64 %t1, 1165 %t8 = icmp eq i64 %t7, 65537166 br i1 %t8, label %out, label %loop167 168out: ; preds = %loop169 ret float %t6170}171 172; This would assert on FMF propagation.173 174define void @not_a_min_max() {175; CHECK-LABEL: @not_a_min_max(176; CHECK-NEXT: entry:177; CHECK-NEXT: br label [[LOOP:%.*]]178; CHECK: loop:179; CHECK-NEXT: [[F9_S0_V0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[LOOP]] ]180; CHECK-NEXT: [[T14:%.*]] = icmp eq i32 [[F9_S0_V0]], 5181; CHECK-NEXT: [[T15:%.*]] = select reassoc nnan ninf nsz contract afn i1 [[T14]], float 0x36A0000000000000, float 0.000000e+00182; CHECK-NEXT: [[ADD]] = add nuw nsw i32 [[F9_S0_V0]], 1183; CHECK-NEXT: br i1 false, label [[END:%.*]], label [[LOOP]]184; CHECK: end:185; CHECK-NEXT: ret void186;187entry:188 br label %loop189 190loop:191 %f9.s0.v0 = phi i32 [ 0, %entry ], [ %add, %loop ]192 %t14 = icmp eq i32 %f9.s0.v0, 5193 %t15 = select reassoc nnan ninf nsz contract afn i1 %t14, float 0x36A0000000000000, float 0.0194 %add = add nuw nsw i32 %f9.s0.v0, 1195 br i1 false, label %end, label %loop196 197end:198 ret void199}200 201attributes #0 = { "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" }202attributes #1 = { "no-nans-fp-math"="true" }203