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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s3 4define float @fmin_olt_with_select_1(ptr %src, i64 %n) {5; CHECK-LABEL: define float @fmin_olt_with_select_1(6; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*]]:8; CHECK-NEXT: br label %[[LOOP:.*]]9; CHECK: [[LOOP]]:10; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]11; CHECK-NEXT: [[MAX:%.*]] = phi float [ -1.000000e+07, %[[ENTRY]] ], [ [[MIN_NEXT:%.*]], %[[LOOP]] ]12; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[IV]]13; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 414; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[L]], [[MAX]]15; CHECK-NEXT: [[MIN_NEXT]] = select i1 [[CMP]], float [[L]], float [[MAX]]16; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 117; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]18; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]19; CHECK: [[EXIT]]:20; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MIN_NEXT]], %[[LOOP]] ]21; CHECK-NEXT: ret float [[MAX_NEXT_LCSSA]]22;23entry:24 br label %loop25 26loop:27 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]28 %min = phi float [ -1.000000e+07, %entry ], [ %min.next, %loop ]29 %gep.src = getelementptr inbounds nuw float, ptr %src, i64 %iv30 %l = load float, ptr %gep.src, align 431 %cmp = fcmp olt float %l, %min32 %min.next = select i1 %cmp, float %l, float %min33 %iv.next = add nuw nsw i64 %iv, 134 %ec = icmp eq i64 %iv.next, %n35 br i1 %ec, label %exit, label %loop36 37exit:38 ret float %min.next39}40 41define float @fmin_olt_with_select_2(ptr %src, i64 %n) {42; CHECK-LABEL: define float @fmin_olt_with_select_2(43; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {44; CHECK-NEXT: [[ENTRY:.*]]:45; CHECK-NEXT: br label %[[LOOP:.*]]46; CHECK: [[LOOP]]:47; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]48; CHECK-NEXT: [[MAX:%.*]] = phi float [ -1.000000e+07, %[[ENTRY]] ], [ [[MIN_NEXT:%.*]], %[[LOOP]] ]49; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[IV]]50; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 451; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[MAX]], [[L]]52; CHECK-NEXT: [[MIN_NEXT]] = select i1 [[CMP]], float [[MAX]], float [[L]]53; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 154; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]55; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]56; CHECK: [[EXIT]]:57; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MIN_NEXT]], %[[LOOP]] ]58; CHECK-NEXT: ret float [[MAX_NEXT_LCSSA]]59;60entry:61 br label %loop62 63loop:64 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]65 %min = phi float [ -1.000000e+07, %entry ], [ %min.next, %loop ]66 %gep.src = getelementptr inbounds nuw float, ptr %src, i64 %iv67 %l = load float, ptr %gep.src, align 468 %cmp = fcmp olt float %min, %l69 %min.next = select i1 %cmp, float %min, float %l70 %iv.next = add nuw nsw i64 %iv, 171 %ec = icmp eq i64 %iv.next, %n72 br i1 %ec, label %exit, label %loop73 74exit:75 ret float %min.next76}77 78define float @fmin_ogt_with_select_1(ptr %src, i64 %n) {79; CHECK-LABEL: define float @fmin_ogt_with_select_1(80; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {81; CHECK-NEXT: [[ENTRY:.*]]:82; CHECK-NEXT: br label %[[LOOP:.*]]83; CHECK: [[LOOP]]:84; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]85; CHECK-NEXT: [[MIN:%.*]] = phi float [ -1.000000e+07, %[[ENTRY]] ], [ [[MIN_NEXT:%.*]], %[[LOOP]] ]86; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[IV]]87; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 488; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[L]], [[MIN]]89; CHECK-NEXT: [[MIN_NEXT]] = select i1 [[CMP]], float [[MIN]], float [[L]]90; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 191; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]92; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]93; CHECK: [[EXIT]]:94; CHECK-NEXT: [[MIN_NEXT_LCSSA:%.*]] = phi float [ [[MIN_NEXT]], %[[LOOP]] ]95; CHECK-NEXT: ret float [[MIN_NEXT_LCSSA]]96;97entry:98 br label %loop99 100loop:101 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]102 %min = phi float [ -1.000000e+07, %entry ], [ %min.next, %loop ]103 %gep.src = getelementptr inbounds nuw float, ptr %src, i64 %iv104 %l = load float, ptr %gep.src, align 4105 %cmp = fcmp ogt float %l, %min106 %min.next = select i1 %cmp, float %min, float %l107 %iv.next = add nuw nsw i64 %iv, 1108 %ec = icmp eq i64 %iv.next, %n109 br i1 %ec, label %exit, label %loop110 111exit:112 ret float %min.next113}114 115define float @fmin_ogt_with_select_2(ptr %src, i64 %n) {116; CHECK-LABEL: define float @fmin_ogt_with_select_2(117; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {118; CHECK-NEXT: [[ENTRY:.*]]:119; CHECK-NEXT: br label %[[LOOP:.*]]120; CHECK: [[LOOP]]:121; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]122; CHECK-NEXT: [[MIN:%.*]] = phi float [ -1.000000e+07, %[[ENTRY]] ], [ [[MIN_NEXT:%.*]], %[[LOOP]] ]123; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[IV]]124; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 4125; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[MIN]], [[L]]126; CHECK-NEXT: [[MIN_NEXT]] = select i1 [[CMP]], float [[L]], float [[MIN]]127; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1128; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]129; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]130; CHECK: [[EXIT]]:131; CHECK-NEXT: [[MIN_NEXT_LCSSA:%.*]] = phi float [ [[MIN_NEXT]], %[[LOOP]] ]132; CHECK-NEXT: ret float [[MIN_NEXT_LCSSA]]133;134entry:135 br label %loop136 137loop:138 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]139 %min = phi float [ -1.000000e+07, %entry ], [ %min.next, %loop ]140 %gep.src = getelementptr inbounds nuw float, ptr %src, i64 %iv141 %l = load float, ptr %gep.src, align 4142 %cmp = fcmp ogt float %min, %l143 %min.next = select i1 %cmp, float %l, float %min144 %iv.next = add nuw nsw i64 %iv, 1145 %ec = icmp eq i64 %iv.next, %n146 br i1 %ec, label %exit, label %loop147 148exit:149 ret float %min.next150}151 152define float @fmin_olt_with_select_store_result(ptr %src, ptr %dst, i64 %n) {153; CHECK-LABEL: define float @fmin_olt_with_select_store_result(154; CHECK-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) {155; CHECK-NEXT: [[ENTRY:.*]]:156; CHECK-NEXT: br label %[[LOOP:.*]]157; CHECK: [[LOOP]]:158; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]159; CHECK-NEXT: [[MAX:%.*]] = phi float [ -1.000000e+07, %[[ENTRY]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]160; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[IV]]161; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 4162; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[L]], [[MAX]]163; CHECK-NEXT: [[MAX_NEXT]] = select i1 [[CMP]], float [[L]], float [[MAX]]164; CHECK-NEXT: store float [[MAX_NEXT]], ptr [[DST]], align 8165; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1166; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]167; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]168; CHECK: [[EXIT]]:169; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MAX_NEXT]], %[[LOOP]] ]170; CHECK-NEXT: ret float [[MAX_NEXT_LCSSA]]171;172entry:173 br label %loop174 175loop:176 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]177 %min = phi float [ -1.000000e+07, %entry ], [ %min.next, %loop ]178 %gep.src = getelementptr inbounds nuw float, ptr %src, i64 %iv179 %l = load float, ptr %gep.src, align 4180 %cmp = fcmp olt float %l, %min181 %min.next = select i1 %cmp, float %l, float %min182 store float %min.next, ptr %dst, align 8183 %iv.next = add nuw nsw i64 %iv, 1184 %ec = icmp eq i64 %iv.next, %n185 br i1 %ec, label %exit, label %loop186 187exit:188 ret float %min.next189}190 191define float @fminnum_1(ptr %src, i64 %n) {192; CHECK-LABEL: define float @fminnum_1(193; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {194; CHECK-NEXT: [[ENTRY:.*]]:195; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4196; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]197; CHECK: [[VECTOR_PH]]:198; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4199; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]200; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]201; CHECK: [[VECTOR_BODY]]:202; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]203; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]204; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[IV]]205; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[GEP_SRC]], align 4206; CHECK-NEXT: [[TMP4]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[WIDE_LOAD]], <4 x float> [[VEC_PHI]])207; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4208; CHECK-NEXT: [[TMP2:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD]]209; CHECK-NEXT: [[TMP10:%.*]] = freeze <4 x i1> [[TMP2]]210; CHECK-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP10]])211; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]212; CHECK-NEXT: [[TMP6:%.*]] = or i1 [[TMP3]], [[TMP5]]213; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]214; CHECK: [[MIDDLE_BLOCK]]:215; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP3]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP4]]216; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP3]], i64 [[IV]], i64 [[N_VEC]]217; CHECK-NEXT: [[TMP8:%.*]] = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> [[TMP7]])218; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]219; CHECK-NEXT: [[TMP11:%.*]] = xor i1 [[TMP3]], true220; CHECK-NEXT: [[TMP12:%.*]] = and i1 [[CMP_N]], [[TMP11]]221; CHECK-NEXT: br i1 [[TMP12]], label %[[EXIT:.*]], label %[[SCALAR_PH]]222; CHECK: [[SCALAR_PH]]:223; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]224; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP8]], %[[MIDDLE_BLOCK]] ], [ -1.000000e+07, %[[ENTRY]] ]225; CHECK-NEXT: br label %[[LOOP:.*]]226; CHECK: [[LOOP]]:227; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]228; CHECK-NEXT: [[MAX:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]229; CHECK-NEXT: [[GEP_SRC1:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[IV1]]230; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC1]], align 4231; CHECK-NEXT: [[MAX_NEXT]] = call float @llvm.minnum.f32(float [[L]], float [[MAX]])232; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1233; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]234; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]235; CHECK: [[EXIT]]:236; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MAX_NEXT]], %[[LOOP]] ], [ [[TMP8]], %[[MIDDLE_BLOCK]] ]237; CHECK-NEXT: ret float [[MAX_NEXT_LCSSA]]238;239entry:240 br label %loop241 242loop:243 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]244 %min = phi float [ -1.000000e+07, %entry ], [ %min.next, %loop ]245 %gep.src = getelementptr inbounds nuw float, ptr %src, i64 %iv246 %l = load float, ptr %gep.src, align 4247 %min.next = call float @llvm.minnum.f32(float %l, float %min)248 %iv.next = add nuw nsw i64 %iv, 1249 %ec = icmp eq i64 %iv.next, %n250 br i1 %ec, label %exit, label %loop251 252exit:253 ret float %min.next254}255 256define float @fminnum_2(ptr %src, i64 %n) {257; CHECK-LABEL: define float @fminnum_2(258; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {259; CHECK-NEXT: [[ENTRY:.*]]:260; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4261; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]262; CHECK: [[VECTOR_PH]]:263; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4264; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]265; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]266; CHECK: [[VECTOR_BODY]]:267; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]268; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]269; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[IV]]270; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[GEP_SRC]], align 4271; CHECK-NEXT: [[TMP4]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[VEC_PHI]], <4 x float> [[WIDE_LOAD]])272; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4273; CHECK-NEXT: [[TMP2:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD]]274; CHECK-NEXT: [[TMP10:%.*]] = freeze <4 x i1> [[TMP2]]275; CHECK-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP10]])276; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]277; CHECK-NEXT: [[TMP6:%.*]] = or i1 [[TMP3]], [[TMP5]]278; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]279; CHECK: [[MIDDLE_BLOCK]]:280; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP3]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP4]]281; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP3]], i64 [[IV]], i64 [[N_VEC]]282; CHECK-NEXT: [[TMP8:%.*]] = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> [[TMP7]])283; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]284; CHECK-NEXT: [[TMP11:%.*]] = xor i1 [[TMP3]], true285; CHECK-NEXT: [[TMP12:%.*]] = and i1 [[CMP_N]], [[TMP11]]286; CHECK-NEXT: br i1 [[TMP12]], label %[[EXIT:.*]], label %[[SCALAR_PH]]287; CHECK: [[SCALAR_PH]]:288; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]289; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP8]], %[[MIDDLE_BLOCK]] ], [ -1.000000e+07, %[[ENTRY]] ]290; CHECK-NEXT: br label %[[LOOP:.*]]291; CHECK: [[LOOP]]:292; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]293; CHECK-NEXT: [[MAX:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]294; CHECK-NEXT: [[GEP_SRC1:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[IV1]]295; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC1]], align 4296; CHECK-NEXT: [[MAX_NEXT]] = call float @llvm.minnum.f32(float [[MAX]], float [[L]])297; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1298; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]299; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]300; CHECK: [[EXIT]]:301; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MAX_NEXT]], %[[LOOP]] ], [ [[TMP8]], %[[MIDDLE_BLOCK]] ]302; CHECK-NEXT: ret float [[MAX_NEXT_LCSSA]]303;304entry:305 br label %loop306 307loop:308 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]309 %min = phi float [ -1.000000e+07, %entry ], [ %min.next, %loop ]310 %gep.src = getelementptr inbounds nuw float, ptr %src, i64 %iv311 %l = load float, ptr %gep.src, align 4312 %min.next = call float @llvm.minnum.f32(float %min, float %l)313 %iv.next = add nuw nsw i64 %iv, 1314 %ec = icmp eq i64 %iv.next, %n315 br i1 %ec, label %exit, label %loop316 317exit:318 ret float %min.next319}320 321define float @fmin_select_with_blend(ptr %A, ptr %B) {322; CHECK-LABEL: define float @fmin_select_with_blend(323; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) {324; CHECK-NEXT: [[ENTRY:.*]]:325; CHECK-NEXT: br label %[[LOOP:.*]]326; CHECK: [[LOOP]]:327; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]328; CHECK-NEXT: [[MAX:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[MIN_NEXT:%.*]], %[[LOOP_LATCH]] ]329; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]330; CHECK-NEXT: [[L_A:%.*]] = load i32, ptr [[GEP_A]], align 4331; CHECK-NEXT: [[C_1:%.*]] = icmp eq i32 [[L_A]], 0332; CHECK-NEXT: br i1 [[C_1]], label %[[LOOP_THEN:.*]], label %[[LOOP_LATCH]]333; CHECK: [[LOOP_THEN]]:334; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]335; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP_B]], align 4336; CHECK-NEXT: [[C_2:%.*]] = fcmp olt float [[MAX]], [[L]]337; CHECK-NEXT: [[MAX_SEL:%.*]] = select i1 [[C_2]], float [[MAX]], float [[L]]338; CHECK-NEXT: br label %[[LOOP_LATCH]]339; CHECK: [[LOOP_LATCH]]:340; CHECK-NEXT: [[MIN_NEXT]] = phi float [ [[MAX_SEL]], %[[LOOP_THEN]] ], [ [[MAX]], %[[LOOP]] ]341; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1342; CHECK-NEXT: [[EC:%.*]] = icmp ne i64 [[IV_NEXT]], 1000343; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT:.*]]344; CHECK: [[EXIT]]:345; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MIN_NEXT]], %[[LOOP_LATCH]] ]346; CHECK-NEXT: ret float [[MAX_NEXT_LCSSA]]347;348entry:349 br label %loop350 351loop:352 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]353 %min = phi float [ 0.000000e+00, %entry ], [ %min.next, %loop.latch ]354 %gep.A = getelementptr inbounds i32, ptr %A, i64 %iv355 %l.A = load i32, ptr %gep.A356 %c.1 = icmp eq i32 %l.A, 0357 br i1 %c.1, label %loop.then, label %loop.latch358 359loop.then:360 %gep.B = getelementptr inbounds float, ptr %B, i64 %iv361 %l = load float, ptr %gep.B362 %c.2 = fcmp olt float %min, %l363 %min.sel = select i1 %c.2, float %min, float %l364 br label %loop.latch365 366loop.latch:367 %min.next = phi float [ %min.sel, %loop.then ], [ %min, %loop ]368 %iv.next = add i64 %iv, 1369 %ec = icmp ne i64 %iv.next, 1000370 br i1 %ec, label %loop, label %exit371 372exit:373 ret float %min.next374}375 376define float @fmin_with_select_and_load_store(ptr %src, ptr noalias %dst, i64 %n) {377; CHECK-LABEL: define float @fmin_with_select_and_load_store(378; CHECK-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {379; CHECK-NEXT: [[ENTRY:.*]]:380; CHECK-NEXT: br label %[[LOOP:.*]]381; CHECK: [[LOOP]]:382; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]383; CHECK-NEXT: [[MAX:%.*]] = phi float [ -1.000000e+07, %[[ENTRY]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]384; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[IV]]385; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 4386; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[L]], [[MAX]]387; CHECK-NEXT: [[IV_1:%.*]] = add i64 [[IV]], 1388; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV_1]]389; CHECK-NEXT: [[L_2:%.*]] = load i32, ptr [[GEP_DST_1]], align 4390; CHECK-NEXT: [[GEP_DST_0:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]]391; CHECK-NEXT: store i32 [[L_2]], ptr [[GEP_DST_0]], align 4392; CHECK-NEXT: [[MAX_NEXT]] = select i1 [[CMP]], float [[L]], float [[MAX]]393; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1394; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]395; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]396; CHECK: [[EXIT]]:397; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MAX_NEXT]], %[[LOOP]] ]398; CHECK-NEXT: ret float [[MAX_NEXT_LCSSA]]399;400entry:401 br label %loop402 403loop:404 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]405 %min = phi float [ -1.000000e+07, %entry ], [ %min.next, %loop ]406 %gep.src = getelementptr inbounds nuw float, ptr %src, i64 %iv407 %l = load float, ptr %gep.src, align 4408 %cmp = fcmp olt float %l, %min409 %iv.1 = add i64 %iv, 1410 %gep.dst.1 = getelementptr inbounds i32, ptr %dst, i64 %iv.1411 %l.2 = load i32, ptr %gep.dst.1412 %gep.dst.0 = getelementptr inbounds i32, ptr %dst, i64 %iv413 store i32 %l.2, ptr %gep.dst.0414 %min.next = select i1 %cmp, float %l, float %min415 %iv.next = add nuw nsw i64 %iv, 1416 %ec = icmp eq i64 %iv.next, %n417 br i1 %ec, label %exit, label %loop418 419exit:420 ret float %min.next421}422 423define float @fmin_ugt_with_select_1(ptr %src, i64 %n) {424; CHECK-LABEL: define float @fmin_ugt_with_select_1(425; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {426; CHECK-NEXT: [[ENTRY:.*]]:427; CHECK-NEXT: br label %[[LOOP:.*]]428; CHECK: [[LOOP]]:429; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]430; CHECK-NEXT: [[MAX:%.*]] = phi float [ -1.000000e+07, %[[ENTRY]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]431; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[IV]]432; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 4433; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[L]], [[MAX]]434; CHECK-NEXT: [[MAX_NEXT]] = select i1 [[CMP]], float [[L]], float [[MAX]]435; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1436; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]437; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]438; CHECK: [[EXIT]]:439; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MAX_NEXT]], %[[LOOP]] ]440; CHECK-NEXT: ret float [[MAX_NEXT_LCSSA]]441;442entry:443 br label %loop444 445loop:446 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]447 %min = phi float [ -1.000000e+07, %entry ], [ %min.next, %loop ]448 %gep.src = getelementptr inbounds nuw float, ptr %src, i64 %iv449 %l = load float, ptr %gep.src, align 4450 %cmp = fcmp ugt float %l, %min451 %min.next = select i1 %cmp, float %l, float %min452 %iv.next = add nuw nsw i64 %iv, 1453 %ec = icmp eq i64 %iv.next, %n454 br i1 %ec, label %exit, label %loop455 456exit:457 ret float %min.next458}459 460define float @fmin_oge_with_select_1(ptr %src, i64 %n) {461; CHECK-LABEL: define float @fmin_oge_with_select_1(462; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {463; CHECK-NEXT: [[ENTRY:.*]]:464; CHECK-NEXT: br label %[[LOOP:.*]]465; CHECK: [[LOOP]]:466; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]467; CHECK-NEXT: [[MAX:%.*]] = phi float [ -1.000000e+07, %[[ENTRY]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]468; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[IV]]469; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP_SRC]], align 4470; CHECK-NEXT: [[CMP:%.*]] = fcmp oge float [[L]], [[MAX]]471; CHECK-NEXT: [[MAX_NEXT]] = select i1 [[CMP]], float [[L]], float [[MAX]]472; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1473; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]474; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]475; CHECK: [[EXIT]]:476; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MAX_NEXT]], %[[LOOP]] ]477; CHECK-NEXT: ret float [[MAX_NEXT_LCSSA]]478;479entry:480 br label %loop481 482loop:483 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]484 %min = phi float [ -1.000000e+07, %entry ], [ %min.next, %loop ]485 %gep.src = getelementptr inbounds nuw float, ptr %src, i64 %iv486 %l = load float, ptr %gep.src, align 4487 %cmp = fcmp oge float %l, %min488 %min.next = select i1 %cmp, float %l, float %min489 %iv.next = add nuw nsw i64 %iv, 1490 %ec = icmp eq i64 %iv.next, %n491 br i1 %ec, label %exit, label %loop492 493exit:494 ret float %min.next495}496