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1; REQUIRES: asserts2; RUN: opt < %s -passes=loop-vectorize,instcombine -force-vector-width=4 -force-vector-interleave=1 -debug-only=loop-vectorize -disable-output -print-after=instcombine 2>&1 | FileCheck %s3 4target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"5 6; CHECK-LABEL: more_than_one_use7;8; PR30627. Check that a compare instruction with more than one use is not9; recognized as uniform and is vectorized.10;11; CHECK-NOT: Found uniform instruction: %cond = icmp slt i64 %i.next, %n12; CHECK: vector.body13; CHECK: %[[I:.+]] = add nuw nsw <4 x i64> %vec.ind, splat (i64 1)14; CHECK: icmp slt <4 x i64> %[[I]], %broadcast.splat15; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body16;17define i32 @more_than_one_use(ptr %a, i64 %n) {18entry:19 br label %for.body20 21for.body:22 %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]23 %r = phi i32 [ %tmp3, %for.body ], [ 0, %entry ]24 %i.next = add nuw nsw i64 %i, 125 %cond = icmp slt i64 %i.next, %n26 %tmp0 = select i1 %cond, i64 %i.next, i64 027 %tmp1 = getelementptr inbounds i32, ptr %a, i64 %tmp028 %tmp2 = load i32, ptr %tmp1, align 829 %tmp3 = add i32 %r, %tmp230 br i1 %cond, label %for.body, label %for.end31 32for.end:33 %tmp4 = phi i32 [ %tmp3, %for.body ]34 ret i32 %tmp435}36 37; Check for crash exposed by D76992.38; CHECK-LABEL: 'test'39; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {40; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF41; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF42; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count43; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count44; CHECK-NEXT: Live-in ir<14> = original trip-count45; CHECK-EMPTY:46; CHECK-NEXT: ir-bb<entry>:47; CHECK-NEXT: Successor(s): scalar.ph, vector.ph48; CHECK-EMPTY:49; CHECK-NEXT: vector.ph:50; CHECK-NEXT: Successor(s): vector loop51; CHECK-EMPTY:52; CHECK-NEXT: <x1> vector loop: {53; CHECK-NEXT: vector.body:54; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION55; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]56; CHECK-NEXT: EMIT vp<[[COND:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]>57; CHECK-NEXT: WIDEN ir<%cond0> = icmp ult ir<%iv>, ir<13>58; CHECK-NEXT: WIDEN-SELECT ir<%s> = select ir<%cond0>, ir<10>, ir<20>59; CHECK-NEXT: Successor(s): pred.store60; CHECK-EMPTY:61; CHECK-NEXT: <xVFxUF> pred.store: {62; CHECK-NEXT: pred.store.entry:63; CHECK-NEXT: BRANCH-ON-MASK vp<[[COND]]>64; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue65; CHECK-EMPTY:66; CHECK-NEXT: pred.store.if:67; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>68; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr inbounds ir<%ptr>, vp<[[STEPS]]>69; CHECK-NEXT: REPLICATE store ir<%s>, ir<%gep>70; CHECK-NEXT: Successor(s): pred.store.continue71; CHECK-EMPTY:72; CHECK-NEXT: pred.store.continue:73; CHECK-NEXT: No successors74; CHECK-NEXT: }75; CHECK-NEXT: Successor(s): loop.076; CHECK-EMPTY:77; CHECK-NEXT: loop.0:78; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>79; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]>80; CHECK-NEXT: No successor81; CHECK-NEXT: }82define void @test(ptr %ptr) {83entry:84 br label %loop85 86loop: ; preds = %loop, %entry87 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]88 %cond0 = icmp ult i64 %iv, 1389 %s = select i1 %cond0, i32 10, i32 2090 %gep = getelementptr inbounds i32, ptr %ptr, i64 %iv91 store i32 %s, ptr %gep92 %iv.next = add nuw nsw i64 %iv, 193 %exitcond = icmp eq i64 %iv.next, 1494 br i1 %exitcond, label %exit, label %loop95 96exit:97 ret void98}99