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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -force-vector-width=2 -force-vector-interleave=1 -passes=loop-vectorize,simplifycfg -verify-loop-info -simplifycfg-require-and-preserve-domtree=1 -force-widen-divrem-via-safe-divisor=0 < %s | FileCheck %s3; RUN: opt -S -force-vector-width=1 -force-vector-interleave=2 -passes=loop-vectorize -verify-loop-info -force-widen-divrem-via-safe-divisor=0 < %s | FileCheck %s --check-prefix=UNROLL-NO-VF4 5target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"6 7; Test predication of non-void instructions, specifically (i) that these8; instructions permit vectorization and (ii) the creation of an insertelement9; and a Phi node. We check the full 2-element sequence for all predicate instructions.10define void @test(ptr nocapture %asd, ptr nocapture %aud,11; CHECK-LABEL: @test(12; CHECK-NEXT: entry:13; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ASD:%.*]], i64 51214; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[AUD:%.*]], i64 51215; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[ASR:%.*]], i64 51216; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[AUR:%.*]], i64 51217; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP1]]18; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[AUD]], [[SCEVGEP]]19; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]20; CHECK-NEXT: [[BOUND04:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP2]]21; CHECK-NEXT: [[BOUND15:%.*]] = icmp ult ptr [[ASR]], [[SCEVGEP]]22; CHECK-NEXT: [[FOUND_CONFLICT6:%.*]] = and i1 [[BOUND04]], [[BOUND15]]23; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT6]]24; CHECK-NEXT: [[BOUND07:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP3]]25; CHECK-NEXT: [[BOUND18:%.*]] = icmp ult ptr [[AUR]], [[SCEVGEP]]26; CHECK-NEXT: [[FOUND_CONFLICT9:%.*]] = and i1 [[BOUND07]], [[BOUND18]]27; CHECK-NEXT: [[CONFLICT_RDX10:%.*]] = or i1 [[CONFLICT_RDX]], [[FOUND_CONFLICT9]]28; CHECK-NEXT: [[BOUND011:%.*]] = icmp ult ptr [[AUD]], [[SCEVGEP2]]29; CHECK-NEXT: [[BOUND112:%.*]] = icmp ult ptr [[ASR]], [[SCEVGEP1]]30; CHECK-NEXT: [[FOUND_CONFLICT13:%.*]] = and i1 [[BOUND011]], [[BOUND112]]31; CHECK-NEXT: [[CONFLICT_RDX14:%.*]] = or i1 [[CONFLICT_RDX10]], [[FOUND_CONFLICT13]]32; CHECK-NEXT: [[BOUND015:%.*]] = icmp ult ptr [[AUD]], [[SCEVGEP3]]33; CHECK-NEXT: [[BOUND116:%.*]] = icmp ult ptr [[AUR]], [[SCEVGEP1]]34; CHECK-NEXT: [[FOUND_CONFLICT17:%.*]] = and i1 [[BOUND015]], [[BOUND116]]35; CHECK-NEXT: [[CONFLICT_RDX18:%.*]] = or i1 [[CONFLICT_RDX14]], [[FOUND_CONFLICT17]]36; CHECK-NEXT: [[BOUND019:%.*]] = icmp ult ptr [[ASR]], [[SCEVGEP3]]37; CHECK-NEXT: [[BOUND120:%.*]] = icmp ult ptr [[AUR]], [[SCEVGEP2]]38; CHECK-NEXT: [[FOUND_CONFLICT21:%.*]] = and i1 [[BOUND019]], [[BOUND120]]39; CHECK-NEXT: [[CONFLICT_RDX22:%.*]] = or i1 [[CONFLICT_RDX18]], [[FOUND_CONFLICT21]]40; CHECK-NEXT: br i1 [[CONFLICT_RDX22]], label [[FOR_BODY:%.*]], label [[VECTOR_BODY:%.*]]41; CHECK: vector.body:42; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[PRED_UREM_CONTINUE27:%.*]] ], [ 0, [[ENTRY:%.*]] ]43; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDEX]]44; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[AUD]], i64 [[INDEX]]45; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[ASR]], i64 [[INDEX]]46; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[AUR]], i64 [[INDEX]]47; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4, !alias.scope [[META5:![0-9]+]], !noalias [[META8:![0-9]+]]48; CHECK-NEXT: [[WIDE_LOAD23:%.*]] = load <2 x i32>, ptr [[TMP2]], align 4, !alias.scope [[META12:![0-9]+]], !noalias [[META13:![0-9]+]]49; CHECK-NEXT: [[WIDE_LOAD24:%.*]] = load <2 x i32>, ptr [[TMP3]], align 4, !alias.scope [[META14:![0-9]+]], !noalias [[META15:![0-9]+]]50; CHECK-NEXT: [[WIDE_LOAD25:%.*]] = load <2 x i32>, ptr [[TMP4]], align 4, !alias.scope [[META15]]51; CHECK-NEXT: [[TMP9:%.*]] = add nsw <2 x i32> [[WIDE_LOAD]], splat (i32 23)52; CHECK-NEXT: [[TMP10:%.*]] = add nsw <2 x i32> [[WIDE_LOAD23]], splat (i32 24)53; CHECK-NEXT: [[TMP11:%.*]] = add nsw <2 x i32> [[WIDE_LOAD24]], splat (i32 25)54; CHECK-NEXT: [[TMP12:%.*]] = add nsw <2 x i32> [[WIDE_LOAD25]], splat (i32 26)55; CHECK-NEXT: [[TMP13:%.*]] = icmp slt <2 x i32> [[WIDE_LOAD]], splat (i32 100)56; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP13]], i32 057; CHECK-NEXT: br i1 [[TMP14]], label [[PRED_UREM_IF:%.*]], label [[PRED_UREM_CONTINUE:%.*]]58; CHECK: pred.urem.if:59; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i32> [[TMP9]], i32 060; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 061; CHECK-NEXT: [[TMP17:%.*]] = sdiv i32 [[TMP15]], [[TMP16]]62; CHECK-NEXT: [[TMP18:%.*]] = insertelement <2 x i32> poison, i32 [[TMP17]], i32 063; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i32> [[TMP10]], i32 064; CHECK-NEXT: [[TMP20:%.*]] = extractelement <2 x i32> [[WIDE_LOAD23]], i32 065; CHECK-NEXT: [[TMP21:%.*]] = udiv i32 [[TMP19]], [[TMP20]]66; CHECK-NEXT: [[TMP22:%.*]] = insertelement <2 x i32> poison, i32 [[TMP21]], i32 067; CHECK-NEXT: [[TMP23:%.*]] = extractelement <2 x i32> [[TMP11]], i32 068; CHECK-NEXT: [[TMP24:%.*]] = extractelement <2 x i32> [[WIDE_LOAD24]], i32 069; CHECK-NEXT: [[TMP25:%.*]] = srem i32 [[TMP23]], [[TMP24]]70; CHECK-NEXT: [[TMP26:%.*]] = insertelement <2 x i32> poison, i32 [[TMP25]], i32 071; CHECK-NEXT: [[TMP27:%.*]] = extractelement <2 x i32> [[TMP12]], i32 072; CHECK-NEXT: [[TMP28:%.*]] = extractelement <2 x i32> [[WIDE_LOAD25]], i32 073; CHECK-NEXT: [[TMP29:%.*]] = urem i32 [[TMP27]], [[TMP28]]74; CHECK-NEXT: [[TMP30:%.*]] = insertelement <2 x i32> poison, i32 [[TMP29]], i32 075; CHECK-NEXT: br label [[PRED_UREM_CONTINUE]]76; CHECK: pred.urem.continue:77; CHECK-NEXT: [[TMP31:%.*]] = phi <2 x i32> [ poison, [[VECTOR_BODY]] ], [ [[TMP18]], [[PRED_UREM_IF]] ]78; CHECK-NEXT: [[TMP32:%.*]] = phi <2 x i32> [ poison, [[VECTOR_BODY]] ], [ [[TMP22]], [[PRED_UREM_IF]] ]79; CHECK-NEXT: [[TMP33:%.*]] = phi <2 x i32> [ poison, [[VECTOR_BODY]] ], [ [[TMP26]], [[PRED_UREM_IF]] ]80; CHECK-NEXT: [[TMP34:%.*]] = phi <2 x i32> [ poison, [[VECTOR_BODY]] ], [ [[TMP30]], [[PRED_UREM_IF]] ]81; CHECK-NEXT: [[TMP35:%.*]] = extractelement <2 x i1> [[TMP13]], i32 182; CHECK-NEXT: br i1 [[TMP35]], label [[PRED_UREM_IF26:%.*]], label [[PRED_UREM_CONTINUE27]]83; CHECK: pred.urem.if26:84; CHECK-NEXT: [[TMP36:%.*]] = extractelement <2 x i32> [[TMP9]], i32 185; CHECK-NEXT: [[TMP37:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 186; CHECK-NEXT: [[TMP38:%.*]] = sdiv i32 [[TMP36]], [[TMP37]]87; CHECK-NEXT: [[TMP39:%.*]] = insertelement <2 x i32> [[TMP31]], i32 [[TMP38]], i32 188; CHECK-NEXT: [[TMP40:%.*]] = extractelement <2 x i32> [[TMP10]], i32 189; CHECK-NEXT: [[TMP41:%.*]] = extractelement <2 x i32> [[WIDE_LOAD23]], i32 190; CHECK-NEXT: [[TMP42:%.*]] = udiv i32 [[TMP40]], [[TMP41]]91; CHECK-NEXT: [[TMP43:%.*]] = insertelement <2 x i32> [[TMP32]], i32 [[TMP42]], i32 192; CHECK-NEXT: [[TMP44:%.*]] = extractelement <2 x i32> [[TMP11]], i32 193; CHECK-NEXT: [[TMP45:%.*]] = extractelement <2 x i32> [[WIDE_LOAD24]], i32 194; CHECK-NEXT: [[TMP46:%.*]] = srem i32 [[TMP44]], [[TMP45]]95; CHECK-NEXT: [[TMP47:%.*]] = insertelement <2 x i32> [[TMP33]], i32 [[TMP46]], i32 196; CHECK-NEXT: [[TMP48:%.*]] = extractelement <2 x i32> [[TMP12]], i32 197; CHECK-NEXT: [[TMP49:%.*]] = extractelement <2 x i32> [[WIDE_LOAD25]], i32 198; CHECK-NEXT: [[TMP50:%.*]] = urem i32 [[TMP48]], [[TMP49]]99; CHECK-NEXT: [[TMP51:%.*]] = insertelement <2 x i32> [[TMP34]], i32 [[TMP50]], i32 1100; CHECK-NEXT: br label [[PRED_UREM_CONTINUE27]]101; CHECK: pred.urem.continue27:102; CHECK-NEXT: [[TMP52:%.*]] = phi <2 x i32> [ [[TMP31]], [[PRED_UREM_CONTINUE]] ], [ [[TMP39]], [[PRED_UREM_IF26]] ]103; CHECK-NEXT: [[TMP53:%.*]] = phi <2 x i32> [ [[TMP32]], [[PRED_UREM_CONTINUE]] ], [ [[TMP43]], [[PRED_UREM_IF26]] ]104; CHECK-NEXT: [[TMP54:%.*]] = phi <2 x i32> [ [[TMP33]], [[PRED_UREM_CONTINUE]] ], [ [[TMP47]], [[PRED_UREM_IF26]] ]105; CHECK-NEXT: [[TMP55:%.*]] = phi <2 x i32> [ [[TMP34]], [[PRED_UREM_CONTINUE]] ], [ [[TMP51]], [[PRED_UREM_IF26]] ]106; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP13]], <2 x i32> [[TMP52]], <2 x i32> [[TMP9]]107; CHECK-NEXT: [[PREDPHI28:%.*]] = select <2 x i1> [[TMP13]], <2 x i32> [[TMP53]], <2 x i32> [[TMP10]]108; CHECK-NEXT: [[PREDPHI29:%.*]] = select <2 x i1> [[TMP13]], <2 x i32> [[TMP54]], <2 x i32> [[TMP11]]109; CHECK-NEXT: [[PREDPHI30:%.*]] = select <2 x i1> [[TMP13]], <2 x i32> [[TMP55]], <2 x i32> [[TMP12]]110; CHECK-NEXT: store <2 x i32> [[PREDPHI]], ptr [[TMP1]], align 4, !alias.scope [[META5]], !noalias [[META8]]111; CHECK-NEXT: store <2 x i32> [[PREDPHI28]], ptr [[TMP2]], align 4, !alias.scope [[META12]], !noalias [[META13]]112; CHECK-NEXT: store <2 x i32> [[PREDPHI29]], ptr [[TMP3]], align 4, !alias.scope [[META14]], !noalias [[META15]]113; CHECK-NEXT: store <2 x i32> [[PREDPHI30]], ptr [[TMP4]], align 4, !alias.scope [[META15]]114; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2115; CHECK-NEXT: [[TMP61:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128116; CHECK-NEXT: br i1 [[TMP61]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]117; CHECK: for.cond.cleanup:118; CHECK-NEXT: ret void119; CHECK: for.body:120; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[IF_END:%.*]] ], [ 0, [[ENTRY]] ]121; CHECK-NEXT: [[ISD:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDVARS_IV]]122; CHECK-NEXT: [[IUD:%.*]] = getelementptr inbounds i32, ptr [[AUD]], i64 [[INDVARS_IV]]123; CHECK-NEXT: [[ISR:%.*]] = getelementptr inbounds i32, ptr [[ASR]], i64 [[INDVARS_IV]]124; CHECK-NEXT: [[IUR:%.*]] = getelementptr inbounds i32, ptr [[AUR]], i64 [[INDVARS_IV]]125; CHECK-NEXT: [[LSD:%.*]] = load i32, ptr [[ISD]], align 4126; CHECK-NEXT: [[LUD:%.*]] = load i32, ptr [[IUD]], align 4127; CHECK-NEXT: [[LSR:%.*]] = load i32, ptr [[ISR]], align 4128; CHECK-NEXT: [[LUR:%.*]] = load i32, ptr [[IUR]], align 4129; CHECK-NEXT: [[PSD:%.*]] = add nsw i32 [[LSD]], 23130; CHECK-NEXT: [[PUD:%.*]] = add nsw i32 [[LUD]], 24131; CHECK-NEXT: [[PSR:%.*]] = add nsw i32 [[LSR]], 25132; CHECK-NEXT: [[PUR:%.*]] = add nsw i32 [[LUR]], 26133; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100134; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_END]]135; CHECK: if.then:136; CHECK-NEXT: [[RSD:%.*]] = sdiv i32 [[PSD]], [[LSD]]137; CHECK-NEXT: [[RUD:%.*]] = udiv i32 [[PUD]], [[LUD]]138; CHECK-NEXT: [[RSR:%.*]] = srem i32 [[PSR]], [[LSR]]139; CHECK-NEXT: [[RUR:%.*]] = urem i32 [[PUR]], [[LUR]]140; CHECK-NEXT: br label [[IF_END]]141; CHECK: if.end:142; CHECK-NEXT: [[YSD_0:%.*]] = phi i32 [ [[RSD]], [[IF_THEN]] ], [ [[PSD]], [[FOR_BODY]] ]143; CHECK-NEXT: [[YUD_0:%.*]] = phi i32 [ [[RUD]], [[IF_THEN]] ], [ [[PUD]], [[FOR_BODY]] ]144; CHECK-NEXT: [[YSR_0:%.*]] = phi i32 [ [[RSR]], [[IF_THEN]] ], [ [[PSR]], [[FOR_BODY]] ]145; CHECK-NEXT: [[YUR_0:%.*]] = phi i32 [ [[RUR]], [[IF_THEN]] ], [ [[PUR]], [[FOR_BODY]] ]146; CHECK-NEXT: store i32 [[YSD_0]], ptr [[ISD]], align 4147; CHECK-NEXT: store i32 [[YUD_0]], ptr [[IUD]], align 4148; CHECK-NEXT: store i32 [[YSR_0]], ptr [[ISR]], align 4149; CHECK-NEXT: store i32 [[YUR_0]], ptr [[IUR]], align 4150; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1151; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128152; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]153;154; UNROLL-NO-VF-LABEL: @test(155; UNROLL-NO-VF-NEXT: entry:156; UNROLL-NO-VF-NEXT: br label [[VECTOR_MEMCHECK:%.*]]157; UNROLL-NO-VF: vector.memcheck:158; UNROLL-NO-VF-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ASD:%.*]], i64 512159; UNROLL-NO-VF-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[AUD:%.*]], i64 512160; UNROLL-NO-VF-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[ASR:%.*]], i64 512161; UNROLL-NO-VF-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[AUR:%.*]], i64 512162; UNROLL-NO-VF-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP1]]163; UNROLL-NO-VF-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[AUD]], [[SCEVGEP]]164; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]165; UNROLL-NO-VF-NEXT: [[BOUND04:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP2]]166; UNROLL-NO-VF-NEXT: [[BOUND15:%.*]] = icmp ult ptr [[ASR]], [[SCEVGEP]]167; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT6:%.*]] = and i1 [[BOUND04]], [[BOUND15]]168; UNROLL-NO-VF-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT6]]169; UNROLL-NO-VF-NEXT: [[BOUND07:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP3]]170; UNROLL-NO-VF-NEXT: [[BOUND18:%.*]] = icmp ult ptr [[AUR]], [[SCEVGEP]]171; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT9:%.*]] = and i1 [[BOUND07]], [[BOUND18]]172; UNROLL-NO-VF-NEXT: [[CONFLICT_RDX10:%.*]] = or i1 [[CONFLICT_RDX]], [[FOUND_CONFLICT9]]173; UNROLL-NO-VF-NEXT: [[BOUND011:%.*]] = icmp ult ptr [[AUD]], [[SCEVGEP2]]174; UNROLL-NO-VF-NEXT: [[BOUND112:%.*]] = icmp ult ptr [[ASR]], [[SCEVGEP1]]175; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT13:%.*]] = and i1 [[BOUND011]], [[BOUND112]]176; UNROLL-NO-VF-NEXT: [[CONFLICT_RDX14:%.*]] = or i1 [[CONFLICT_RDX10]], [[FOUND_CONFLICT13]]177; UNROLL-NO-VF-NEXT: [[BOUND015:%.*]] = icmp ult ptr [[AUD]], [[SCEVGEP3]]178; UNROLL-NO-VF-NEXT: [[BOUND116:%.*]] = icmp ult ptr [[AUR]], [[SCEVGEP1]]179; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT17:%.*]] = and i1 [[BOUND015]], [[BOUND116]]180; UNROLL-NO-VF-NEXT: [[CONFLICT_RDX18:%.*]] = or i1 [[CONFLICT_RDX14]], [[FOUND_CONFLICT17]]181; UNROLL-NO-VF-NEXT: [[BOUND019:%.*]] = icmp ult ptr [[ASR]], [[SCEVGEP3]]182; UNROLL-NO-VF-NEXT: [[BOUND120:%.*]] = icmp ult ptr [[AUR]], [[SCEVGEP2]]183; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT21:%.*]] = and i1 [[BOUND019]], [[BOUND120]]184; UNROLL-NO-VF-NEXT: [[CONFLICT_RDX22:%.*]] = or i1 [[CONFLICT_RDX18]], [[FOUND_CONFLICT21]]185; UNROLL-NO-VF-NEXT: br i1 [[CONFLICT_RDX22]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]186; UNROLL-NO-VF: vector.ph:187; UNROLL-NO-VF-NEXT: br label [[VECTOR_BODY:%.*]]188; UNROLL-NO-VF: vector.body:189; UNROLL-NO-VF-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_UREM_CONTINUE24:%.*]] ]190; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1191; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDEX]]192; UNROLL-NO-VF-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[TMP1]]193; UNROLL-NO-VF-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[AUD]], i64 [[INDEX]]194; UNROLL-NO-VF-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[AUD]], i64 [[TMP1]]195; UNROLL-NO-VF-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[ASR]], i64 [[INDEX]]196; UNROLL-NO-VF-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[ASR]], i64 [[TMP1]]197; UNROLL-NO-VF-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[AUR]], i64 [[INDEX]]198; UNROLL-NO-VF-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[AUR]], i64 [[TMP1]]199; UNROLL-NO-VF-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP2]], align 4, !alias.scope [[META5:![0-9]+]], !noalias [[META8:![0-9]+]]200; UNROLL-NO-VF-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP3]], align 4, !alias.scope [[META5]], !noalias [[META8]]201; UNROLL-NO-VF-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP4]], align 4, !alias.scope [[META12:![0-9]+]], !noalias [[META13:![0-9]+]]202; UNROLL-NO-VF-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP5]], align 4, !alias.scope [[META12]], !noalias [[META13]]203; UNROLL-NO-VF-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP6]], align 4, !alias.scope [[META14:![0-9]+]], !noalias [[META15:![0-9]+]]204; UNROLL-NO-VF-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP7]], align 4, !alias.scope [[META14]], !noalias [[META15]]205; UNROLL-NO-VF-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP8]], align 4, !alias.scope [[META15]]206; UNROLL-NO-VF-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP9]], align 4, !alias.scope [[META15]]207; UNROLL-NO-VF-NEXT: [[TMP18:%.*]] = add nsw i32 [[TMP10]], 23208; UNROLL-NO-VF-NEXT: [[TMP19:%.*]] = add nsw i32 [[TMP11]], 23209; UNROLL-NO-VF-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP12]], 24210; UNROLL-NO-VF-NEXT: [[TMP21:%.*]] = add nsw i32 [[TMP13]], 24211; UNROLL-NO-VF-NEXT: [[TMP22:%.*]] = add nsw i32 [[TMP14]], 25212; UNROLL-NO-VF-NEXT: [[TMP23:%.*]] = add nsw i32 [[TMP15]], 25213; UNROLL-NO-VF-NEXT: [[TMP24:%.*]] = add nsw i32 [[TMP16]], 26214; UNROLL-NO-VF-NEXT: [[TMP25:%.*]] = add nsw i32 [[TMP17]], 26215; UNROLL-NO-VF-NEXT: [[TMP26:%.*]] = icmp slt i32 [[TMP10]], 100216; UNROLL-NO-VF-NEXT: [[TMP27:%.*]] = icmp slt i32 [[TMP11]], 100217; UNROLL-NO-VF-NEXT: br i1 [[TMP26]], label [[PRED_UREM_IF:%.*]], label [[PRED_UREM_CONTINUE:%.*]]218; UNROLL-NO-VF: pred.urem.if:219; UNROLL-NO-VF-NEXT: [[TMP28:%.*]] = sdiv i32 [[TMP18]], [[TMP10]]220; UNROLL-NO-VF-NEXT: [[TMP29:%.*]] = udiv i32 [[TMP20]], [[TMP12]]221; UNROLL-NO-VF-NEXT: [[TMP30:%.*]] = srem i32 [[TMP22]], [[TMP14]]222; UNROLL-NO-VF-NEXT: [[TMP31:%.*]] = urem i32 [[TMP24]], [[TMP16]]223; UNROLL-NO-VF-NEXT: br label [[PRED_UREM_CONTINUE]]224; UNROLL-NO-VF: pred.urem.continue:225; UNROLL-NO-VF-NEXT: [[TMP32:%.*]] = phi i32 [ poison, [[VECTOR_BODY]] ], [ [[TMP28]], [[PRED_UREM_IF]] ]226; UNROLL-NO-VF-NEXT: [[TMP33:%.*]] = phi i32 [ poison, [[VECTOR_BODY]] ], [ [[TMP29]], [[PRED_UREM_IF]] ]227; UNROLL-NO-VF-NEXT: [[TMP34:%.*]] = phi i32 [ poison, [[VECTOR_BODY]] ], [ [[TMP30]], [[PRED_UREM_IF]] ]228; UNROLL-NO-VF-NEXT: [[TMP35:%.*]] = phi i32 [ poison, [[VECTOR_BODY]] ], [ [[TMP31]], [[PRED_UREM_IF]] ]229; UNROLL-NO-VF-NEXT: br i1 [[TMP27]], label [[PRED_UREM_IF23:%.*]], label [[PRED_UREM_CONTINUE24]]230; UNROLL-NO-VF: pred.urem.if23:231; UNROLL-NO-VF-NEXT: [[TMP36:%.*]] = sdiv i32 [[TMP19]], [[TMP11]]232; UNROLL-NO-VF-NEXT: [[TMP37:%.*]] = udiv i32 [[TMP21]], [[TMP13]]233; UNROLL-NO-VF-NEXT: [[TMP38:%.*]] = srem i32 [[TMP23]], [[TMP15]]234; UNROLL-NO-VF-NEXT: [[TMP39:%.*]] = urem i32 [[TMP25]], [[TMP17]]235; UNROLL-NO-VF-NEXT: br label [[PRED_UREM_CONTINUE24]]236; UNROLL-NO-VF: pred.urem.continue24:237; UNROLL-NO-VF-NEXT: [[TMP40:%.*]] = phi i32 [ poison, [[PRED_UREM_CONTINUE]] ], [ [[TMP36]], [[PRED_UREM_IF23]] ]238; UNROLL-NO-VF-NEXT: [[TMP41:%.*]] = phi i32 [ poison, [[PRED_UREM_CONTINUE]] ], [ [[TMP37]], [[PRED_UREM_IF23]] ]239; UNROLL-NO-VF-NEXT: [[TMP42:%.*]] = phi i32 [ poison, [[PRED_UREM_CONTINUE]] ], [ [[TMP38]], [[PRED_UREM_IF23]] ]240; UNROLL-NO-VF-NEXT: [[TMP43:%.*]] = phi i32 [ poison, [[PRED_UREM_CONTINUE]] ], [ [[TMP39]], [[PRED_UREM_IF23]] ]241; UNROLL-NO-VF-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP26]], i32 [[TMP32]], i32 [[TMP18]]242; UNROLL-NO-VF-NEXT: [[PREDPHI25:%.*]] = select i1 [[TMP27]], i32 [[TMP40]], i32 [[TMP19]]243; UNROLL-NO-VF-NEXT: [[PREDPHI26:%.*]] = select i1 [[TMP26]], i32 [[TMP33]], i32 [[TMP20]]244; UNROLL-NO-VF-NEXT: [[PREDPHI27:%.*]] = select i1 [[TMP27]], i32 [[TMP41]], i32 [[TMP21]]245; UNROLL-NO-VF-NEXT: [[PREDPHI28:%.*]] = select i1 [[TMP26]], i32 [[TMP34]], i32 [[TMP22]]246; UNROLL-NO-VF-NEXT: [[PREDPHI29:%.*]] = select i1 [[TMP27]], i32 [[TMP42]], i32 [[TMP23]]247; UNROLL-NO-VF-NEXT: [[PREDPHI30:%.*]] = select i1 [[TMP26]], i32 [[TMP35]], i32 [[TMP24]]248; UNROLL-NO-VF-NEXT: [[PREDPHI31:%.*]] = select i1 [[TMP27]], i32 [[TMP43]], i32 [[TMP25]]249; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI]], ptr [[TMP2]], align 4, !alias.scope [[META5]], !noalias [[META8]]250; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI25]], ptr [[TMP3]], align 4, !alias.scope [[META5]], !noalias [[META8]]251; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI26]], ptr [[TMP4]], align 4, !alias.scope [[META12]], !noalias [[META13]]252; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI27]], ptr [[TMP5]], align 4, !alias.scope [[META12]], !noalias [[META13]]253; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI28]], ptr [[TMP6]], align 4, !alias.scope [[META14]], !noalias [[META15]]254; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI29]], ptr [[TMP7]], align 4, !alias.scope [[META14]], !noalias [[META15]]255; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI30]], ptr [[TMP8]], align 4, !alias.scope [[META15]]256; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI31]], ptr [[TMP9]], align 4, !alias.scope [[META15]]257; UNROLL-NO-VF-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2258; UNROLL-NO-VF-NEXT: [[TMP46:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128259; UNROLL-NO-VF-NEXT: br i1 [[TMP46]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]260; UNROLL-NO-VF: middle.block:261; UNROLL-NO-VF-NEXT: br label [[FOR_COND_CLEANUP:%.*]]262; UNROLL-NO-VF: scalar.ph:263; UNROLL-NO-VF-NEXT: br label [[FOR_BODY:%.*]]264; UNROLL-NO-VF: for.cond.cleanup:265; UNROLL-NO-VF-NEXT: ret void266; UNROLL-NO-VF: for.body:267; UNROLL-NO-VF-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[IF_END:%.*]] ]268; UNROLL-NO-VF-NEXT: [[ISD:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDVARS_IV]]269; UNROLL-NO-VF-NEXT: [[IUD:%.*]] = getelementptr inbounds i32, ptr [[AUD]], i64 [[INDVARS_IV]]270; UNROLL-NO-VF-NEXT: [[ISR:%.*]] = getelementptr inbounds i32, ptr [[ASR]], i64 [[INDVARS_IV]]271; UNROLL-NO-VF-NEXT: [[IUR:%.*]] = getelementptr inbounds i32, ptr [[AUR]], i64 [[INDVARS_IV]]272; UNROLL-NO-VF-NEXT: [[LSD:%.*]] = load i32, ptr [[ISD]], align 4273; UNROLL-NO-VF-NEXT: [[LUD:%.*]] = load i32, ptr [[IUD]], align 4274; UNROLL-NO-VF-NEXT: [[LSR:%.*]] = load i32, ptr [[ISR]], align 4275; UNROLL-NO-VF-NEXT: [[LUR:%.*]] = load i32, ptr [[IUR]], align 4276; UNROLL-NO-VF-NEXT: [[PSD:%.*]] = add nsw i32 [[LSD]], 23277; UNROLL-NO-VF-NEXT: [[PUD:%.*]] = add nsw i32 [[LUD]], 24278; UNROLL-NO-VF-NEXT: [[PSR:%.*]] = add nsw i32 [[LSR]], 25279; UNROLL-NO-VF-NEXT: [[PUR:%.*]] = add nsw i32 [[LUR]], 26280; UNROLL-NO-VF-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100281; UNROLL-NO-VF-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_END]]282; UNROLL-NO-VF: if.then:283; UNROLL-NO-VF-NEXT: [[RSD:%.*]] = sdiv i32 [[PSD]], [[LSD]]284; UNROLL-NO-VF-NEXT: [[RUD:%.*]] = udiv i32 [[PUD]], [[LUD]]285; UNROLL-NO-VF-NEXT: [[RSR:%.*]] = srem i32 [[PSR]], [[LSR]]286; UNROLL-NO-VF-NEXT: [[RUR:%.*]] = urem i32 [[PUR]], [[LUR]]287; UNROLL-NO-VF-NEXT: br label [[IF_END]]288; UNROLL-NO-VF: if.end:289; UNROLL-NO-VF-NEXT: [[YSD_0:%.*]] = phi i32 [ [[RSD]], [[IF_THEN]] ], [ [[PSD]], [[FOR_BODY]] ]290; UNROLL-NO-VF-NEXT: [[YUD_0:%.*]] = phi i32 [ [[RUD]], [[IF_THEN]] ], [ [[PUD]], [[FOR_BODY]] ]291; UNROLL-NO-VF-NEXT: [[YSR_0:%.*]] = phi i32 [ [[RSR]], [[IF_THEN]] ], [ [[PSR]], [[FOR_BODY]] ]292; UNROLL-NO-VF-NEXT: [[YUR_0:%.*]] = phi i32 [ [[RUR]], [[IF_THEN]] ], [ [[PUR]], [[FOR_BODY]] ]293; UNROLL-NO-VF-NEXT: store i32 [[YSD_0]], ptr [[ISD]], align 4294; UNROLL-NO-VF-NEXT: store i32 [[YUD_0]], ptr [[IUD]], align 4295; UNROLL-NO-VF-NEXT: store i32 [[YSR_0]], ptr [[ISR]], align 4296; UNROLL-NO-VF-NEXT: store i32 [[YUR_0]], ptr [[IUR]], align 4297; UNROLL-NO-VF-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1298; UNROLL-NO-VF-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128299; UNROLL-NO-VF-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]300;301 ptr nocapture %asr, ptr nocapture %aur) {302entry:303 br label %for.body304 305for.cond.cleanup: ; preds = %if.end306 ret void307 308for.body: ; preds = %if.end, %entry309 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ]310 %isd = getelementptr inbounds i32, ptr %asd, i64 %indvars.iv311 %iud = getelementptr inbounds i32, ptr %aud, i64 %indvars.iv312 %isr = getelementptr inbounds i32, ptr %asr, i64 %indvars.iv313 %iur = getelementptr inbounds i32, ptr %aur, i64 %indvars.iv314 %lsd = load i32, ptr %isd, align 4315 %lud = load i32, ptr %iud, align 4316 %lsr = load i32, ptr %isr, align 4317 %lur = load i32, ptr %iur, align 4318 %psd = add nsw i32 %lsd, 23319 %pud = add nsw i32 %lud, 24320 %psr = add nsw i32 %lsr, 25321 %pur = add nsw i32 %lur, 26322 %cmp1 = icmp slt i32 %lsd, 100323 br i1 %cmp1, label %if.then, label %if.end324 325if.then: ; preds = %for.body326 %rsd = sdiv i32 %psd, %lsd327 %rud = udiv i32 %pud, %lud328 %rsr = srem i32 %psr, %lsr329 %rur = urem i32 %pur, %lur330 br label %if.end331 332if.end: ; preds = %if.then, %for.body333 %ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %for.body ]334 %yud.0 = phi i32 [ %rud, %if.then ], [ %pud, %for.body ]335 %ysr.0 = phi i32 [ %rsr, %if.then ], [ %psr, %for.body ]336 %yur.0 = phi i32 [ %rur, %if.then ], [ %pur, %for.body ]337 store i32 %ysd.0, ptr %isd, align 4338 store i32 %yud.0, ptr %iud, align 4339 store i32 %ysr.0, ptr %isr, align 4340 store i32 %yur.0, ptr %iur, align 4341 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1342 %exitcond = icmp eq i64 %indvars.iv.next, 128343 br i1 %exitcond, label %for.cond.cleanup, label %for.body344}345 346define void @test_scalar2scalar(ptr nocapture %asd, ptr nocapture %bsd) {347; CHECK-LABEL: @test_scalar2scalar(348; CHECK-NEXT: entry:349; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ASD:%.*]], i64 512350; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[BSD:%.*]], i64 512351; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP1]]352; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[BSD]], [[SCEVGEP]]353; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]354; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[FOR_BODY:%.*]], label [[VECTOR_BODY:%.*]]355; CHECK: vector.body:356; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[PRED_SDIV_CONTINUE4:%.*]] ], [ 0, [[ENTRY:%.*]] ]357; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDEX]]358; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4, !alias.scope [[META20:![0-9]+]], !noalias [[META23:![0-9]+]]359; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDEX]]360; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <2 x i32>, ptr [[TMP3]], align 4, !alias.scope [[META23]]361; CHECK-NEXT: [[TMP5:%.*]] = add nsw <2 x i32> [[WIDE_LOAD]], splat (i32 23)362; CHECK-NEXT: [[TMP6:%.*]] = icmp slt <2 x i32> [[WIDE_LOAD]], splat (i32 100)363; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP6]], i32 0364; CHECK-NEXT: br i1 [[TMP7]], label [[PRED_SDIV_IF:%.*]], label [[PRED_SDIV_CONTINUE:%.*]]365; CHECK: pred.sdiv.if:366; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i32> [[TMP5]], i32 0367; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 0368; CHECK-NEXT: [[TMP10:%.*]] = sdiv i32 [[TMP8]], [[TMP9]]369; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i32> [[WIDE_LOAD2]], i32 0370; CHECK-NEXT: [[TMP12:%.*]] = sdiv i32 [[TMP11]], [[TMP10]]371; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x i32> poison, i32 [[TMP12]], i32 0372; CHECK-NEXT: br label [[PRED_SDIV_CONTINUE]]373; CHECK: pred.sdiv.continue:374; CHECK-NEXT: [[TMP15:%.*]] = phi <2 x i32> [ poison, [[VECTOR_BODY]] ], [ [[TMP13]], [[PRED_SDIV_IF]] ]375; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i1> [[TMP6]], i32 1376; CHECK-NEXT: br i1 [[TMP16]], label [[PRED_SDIV_IF3:%.*]], label [[PRED_SDIV_CONTINUE4]]377; CHECK: pred.sdiv.if3:378; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i32> [[TMP5]], i32 1379; CHECK-NEXT: [[TMP18:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 1380; CHECK-NEXT: [[TMP19:%.*]] = sdiv i32 [[TMP17]], [[TMP18]]381; CHECK-NEXT: [[TMP20:%.*]] = extractelement <2 x i32> [[WIDE_LOAD2]], i32 1382; CHECK-NEXT: [[TMP21:%.*]] = sdiv i32 [[TMP20]], [[TMP19]]383; CHECK-NEXT: [[TMP22:%.*]] = insertelement <2 x i32> [[TMP15]], i32 [[TMP21]], i32 1384; CHECK-NEXT: br label [[PRED_SDIV_CONTINUE4]]385; CHECK: pred.sdiv.continue4:386; CHECK-NEXT: [[TMP24:%.*]] = phi <2 x i32> [ [[TMP15]], [[PRED_SDIV_CONTINUE]] ], [ [[TMP22]], [[PRED_SDIV_IF3]] ]387; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP6]], <2 x i32> [[TMP24]], <2 x i32> [[TMP5]]388; CHECK-NEXT: store <2 x i32> [[PREDPHI]], ptr [[TMP1]], align 4, !alias.scope [[META20]], !noalias [[META23]]389; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2390; CHECK-NEXT: [[TMP27:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128391; CHECK-NEXT: br i1 [[TMP27]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP25:![0-9]+]]392; CHECK: for.cond.cleanup:393; CHECK-NEXT: ret void394; CHECK: for.body:395; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[IF_END:%.*]] ], [ 0, [[ENTRY]] ]396; CHECK-NEXT: [[ISD:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDVARS_IV]]397; CHECK-NEXT: [[LSD:%.*]] = load i32, ptr [[ISD]], align 4398; CHECK-NEXT: [[ISD_B:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDVARS_IV]]399; CHECK-NEXT: [[LSD_B:%.*]] = load i32, ptr [[ISD_B]], align 4400; CHECK-NEXT: [[PSD:%.*]] = add nsw i32 [[LSD]], 23401; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100402; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_END]]403; CHECK: if.then:404; CHECK-NEXT: [[SD1:%.*]] = sdiv i32 [[PSD]], [[LSD]]405; CHECK-NEXT: [[RSD:%.*]] = sdiv i32 [[LSD_B]], [[SD1]]406; CHECK-NEXT: br label [[IF_END]]407; CHECK: if.end:408; CHECK-NEXT: [[YSD_0:%.*]] = phi i32 [ [[RSD]], [[IF_THEN]] ], [ [[PSD]], [[FOR_BODY]] ]409; CHECK-NEXT: store i32 [[YSD_0]], ptr [[ISD]], align 4410; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1411; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128412; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP26:![0-9]+]]413;414; UNROLL-NO-VF-LABEL: @test_scalar2scalar(415; UNROLL-NO-VF-NEXT: entry:416; UNROLL-NO-VF-NEXT: br label [[VECTOR_MEMCHECK:%.*]]417; UNROLL-NO-VF: vector.memcheck:418; UNROLL-NO-VF-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ASD:%.*]], i64 512419; UNROLL-NO-VF-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[BSD:%.*]], i64 512420; UNROLL-NO-VF-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP1]]421; UNROLL-NO-VF-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[BSD]], [[SCEVGEP]]422; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]423; UNROLL-NO-VF-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]424; UNROLL-NO-VF: vector.ph:425; UNROLL-NO-VF-NEXT: br label [[VECTOR_BODY:%.*]]426; UNROLL-NO-VF: vector.body:427; UNROLL-NO-VF-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_SDIV_CONTINUE3:%.*]] ]428; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1429; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDEX]]430; UNROLL-NO-VF-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[TMP1]]431; UNROLL-NO-VF-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4, !alias.scope [[META20:![0-9]+]], !noalias [[META23:![0-9]+]]432; UNROLL-NO-VF-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP3]], align 4, !alias.scope [[META20]], !noalias [[META23]]433; UNROLL-NO-VF-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDEX]]434; UNROLL-NO-VF-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[TMP1]]435; UNROLL-NO-VF-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP6]], align 4, !alias.scope [[META23]]436; UNROLL-NO-VF-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4, !alias.scope [[META23]]437; UNROLL-NO-VF-NEXT: [[TMP10:%.*]] = add nsw i32 [[TMP4]], 23438; UNROLL-NO-VF-NEXT: [[TMP11:%.*]] = add nsw i32 [[TMP5]], 23439; UNROLL-NO-VF-NEXT: [[TMP12:%.*]] = icmp slt i32 [[TMP4]], 100440; UNROLL-NO-VF-NEXT: [[TMP13:%.*]] = icmp slt i32 [[TMP5]], 100441; UNROLL-NO-VF-NEXT: br i1 [[TMP12]], label [[PRED_SDIV_IF:%.*]], label [[PRED_SDIV_CONTINUE:%.*]]442; UNROLL-NO-VF: pred.sdiv.if:443; UNROLL-NO-VF-NEXT: [[TMP14:%.*]] = sdiv i32 [[TMP10]], [[TMP4]]444; UNROLL-NO-VF-NEXT: [[TMP15:%.*]] = sdiv i32 [[TMP8]], [[TMP14]]445; UNROLL-NO-VF-NEXT: br label [[PRED_SDIV_CONTINUE]]446; UNROLL-NO-VF: pred.sdiv.continue:447; UNROLL-NO-VF-NEXT: [[TMP17:%.*]] = phi i32 [ poison, [[VECTOR_BODY]] ], [ [[TMP15]], [[PRED_SDIV_IF]] ]448; UNROLL-NO-VF-NEXT: br i1 [[TMP13]], label [[PRED_SDIV_IF2:%.*]], label [[PRED_SDIV_CONTINUE3]]449; UNROLL-NO-VF: pred.sdiv.if2:450; UNROLL-NO-VF-NEXT: [[TMP18:%.*]] = sdiv i32 [[TMP11]], [[TMP5]]451; UNROLL-NO-VF-NEXT: [[TMP19:%.*]] = sdiv i32 [[TMP9]], [[TMP18]]452; UNROLL-NO-VF-NEXT: br label [[PRED_SDIV_CONTINUE3]]453; UNROLL-NO-VF: pred.sdiv.continue3:454; UNROLL-NO-VF-NEXT: [[TMP21:%.*]] = phi i32 [ poison, [[PRED_SDIV_CONTINUE]] ], [ [[TMP19]], [[PRED_SDIV_IF2]] ]455; UNROLL-NO-VF-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP12]], i32 [[TMP17]], i32 [[TMP10]]456; UNROLL-NO-VF-NEXT: [[PREDPHI4:%.*]] = select i1 [[TMP13]], i32 [[TMP21]], i32 [[TMP11]]457; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI]], ptr [[TMP2]], align 4, !alias.scope [[META20]], !noalias [[META23]]458; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI4]], ptr [[TMP3]], align 4, !alias.scope [[META20]], !noalias [[META23]]459; UNROLL-NO-VF-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2460; UNROLL-NO-VF-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128461; UNROLL-NO-VF-NEXT: br i1 [[TMP24]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP25:![0-9]+]]462; UNROLL-NO-VF: middle.block:463; UNROLL-NO-VF-NEXT: br label [[FOR_COND_CLEANUP:%.*]]464; UNROLL-NO-VF: scalar.ph:465; UNROLL-NO-VF-NEXT: br label [[FOR_BODY:%.*]]466; UNROLL-NO-VF: for.cond.cleanup:467; UNROLL-NO-VF-NEXT: ret void468; UNROLL-NO-VF: for.body:469; UNROLL-NO-VF-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[IF_END:%.*]] ]470; UNROLL-NO-VF-NEXT: [[ISD:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDVARS_IV]]471; UNROLL-NO-VF-NEXT: [[LSD:%.*]] = load i32, ptr [[ISD]], align 4472; UNROLL-NO-VF-NEXT: [[ISD_B:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDVARS_IV]]473; UNROLL-NO-VF-NEXT: [[LSD_B:%.*]] = load i32, ptr [[ISD_B]], align 4474; UNROLL-NO-VF-NEXT: [[PSD:%.*]] = add nsw i32 [[LSD]], 23475; UNROLL-NO-VF-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100476; UNROLL-NO-VF-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_END]]477; UNROLL-NO-VF: if.then:478; UNROLL-NO-VF-NEXT: [[SD1:%.*]] = sdiv i32 [[PSD]], [[LSD]]479; UNROLL-NO-VF-NEXT: [[RSD:%.*]] = sdiv i32 [[LSD_B]], [[SD1]]480; UNROLL-NO-VF-NEXT: br label [[IF_END]]481; UNROLL-NO-VF: if.end:482; UNROLL-NO-VF-NEXT: [[YSD_0:%.*]] = phi i32 [ [[RSD]], [[IF_THEN]] ], [ [[PSD]], [[FOR_BODY]] ]483; UNROLL-NO-VF-NEXT: store i32 [[YSD_0]], ptr [[ISD]], align 4484; UNROLL-NO-VF-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1485; UNROLL-NO-VF-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128486; UNROLL-NO-VF-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP26:![0-9]+]]487;488entry:489 br label %for.body490 491for.cond.cleanup: ; preds = %if.end492 ret void493 494 495for.body: ; preds = %if.end, %entry496 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ]497 %isd = getelementptr inbounds i32, ptr %asd, i64 %indvars.iv498 %lsd = load i32, ptr %isd, align 4499 %isd.b = getelementptr inbounds i32, ptr %bsd, i64 %indvars.iv500 %lsd.b = load i32, ptr %isd.b, align 4501 %psd = add nsw i32 %lsd, 23502 %cmp1 = icmp slt i32 %lsd, 100503 br i1 %cmp1, label %if.then, label %if.end504 505if.then: ; preds = %for.body506 %sd1 = sdiv i32 %psd, %lsd507 %rsd = sdiv i32 %lsd.b, %sd1508 br label %if.end509 510if.end: ; preds = %if.then, %for.body511 %ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %for.body ]512 store i32 %ysd.0, ptr %isd, align 4513 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1514 %exitcond = icmp eq i64 %indvars.iv.next, 128515 br i1 %exitcond, label %for.cond.cleanup, label %for.body516}517 518define void @pr30172(ptr nocapture %asd, ptr nocapture %bsd) !dbg !5 {;519; CHECK-LABEL: @pr30172(520; CHECK-NEXT: entry:521; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ASD:%.*]], i64 512522; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[BSD:%.*]], i64 512523; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP1]]524; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[BSD]], [[SCEVGEP]]525; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]526; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[FOR_BODY:%.*]], label [[VECTOR_BODY:%.*]]527; CHECK: vector.body:528; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[PRED_SDIV_CONTINUE4:%.*]] ], [ 0, [[ENTRY:%.*]] ]529; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDEX]]530; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4, !alias.scope [[META29:![0-9]+]], !noalias [[META32:![0-9]+]]531; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDEX]]532; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <2 x i32>, ptr [[TMP3]], align 4, !alias.scope [[META32]]533; CHECK-NEXT: [[TMP5:%.*]] = add nsw <2 x i32> [[WIDE_LOAD]], splat (i32 23)534; CHECK-NEXT: [[TMP6:%.*]] = icmp slt <2 x i32> [[WIDE_LOAD]], splat (i32 100)535; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i1> [[TMP6]], splat (i1 true), !dbg [[DBG34:![0-9]+]]536; CHECK-NEXT: [[TMP8:%.*]] = icmp sge <2 x i32> [[WIDE_LOAD]], splat (i32 200)537; CHECK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP4]], <2 x i1> [[TMP8]], <2 x i1> zeroinitializer, !dbg [[DBG35:![0-9]+]]538; CHECK-NEXT: [[TMP10:%.*]] = or <2 x i1> [[TMP9]], [[TMP6]]539; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP10]], i32 0540; CHECK-NEXT: br i1 [[TMP11]], label [[PRED_SDIV_IF:%.*]], label [[PRED_SDIV_CONTINUE:%.*]]541; CHECK: pred.sdiv.if:542; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i32> [[TMP5]], i32 0543; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 0544; CHECK-NEXT: [[TMP14:%.*]] = sdiv i32 [[TMP12]], [[TMP13]]545; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i32> [[WIDE_LOAD2]], i32 0546; CHECK-NEXT: [[TMP16:%.*]] = sdiv i32 [[TMP15]], [[TMP14]]547; CHECK-NEXT: [[TMP17:%.*]] = insertelement <2 x i32> poison, i32 [[TMP16]], i32 0548; CHECK-NEXT: br label [[PRED_SDIV_CONTINUE]]549; CHECK: pred.sdiv.continue:550; CHECK-NEXT: [[TMP19:%.*]] = phi <2 x i32> [ poison, [[VECTOR_BODY]] ], [ [[TMP17]], [[PRED_SDIV_IF]] ]551; CHECK-NEXT: [[TMP20:%.*]] = extractelement <2 x i1> [[TMP10]], i32 1552; CHECK-NEXT: br i1 [[TMP20]], label [[PRED_SDIV_IF3:%.*]], label [[PRED_SDIV_CONTINUE4]]553; CHECK: pred.sdiv.if3:554; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x i32> [[TMP5]], i32 1555; CHECK-NEXT: [[TMP22:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 1556; CHECK-NEXT: [[TMP23:%.*]] = sdiv i32 [[TMP21]], [[TMP22]]557; CHECK-NEXT: [[TMP24:%.*]] = extractelement <2 x i32> [[WIDE_LOAD2]], i32 1558; CHECK-NEXT: [[TMP25:%.*]] = sdiv i32 [[TMP24]], [[TMP23]]559; CHECK-NEXT: [[TMP26:%.*]] = insertelement <2 x i32> [[TMP19]], i32 [[TMP25]], i32 1560; CHECK-NEXT: br label [[PRED_SDIV_CONTINUE4]]561; CHECK: pred.sdiv.continue4:562; CHECK-NEXT: [[TMP28:%.*]] = phi <2 x i32> [ [[TMP19]], [[PRED_SDIV_CONTINUE]] ], [ [[TMP26]], [[PRED_SDIV_IF3]] ]563; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP10]], <2 x i32> [[TMP28]], <2 x i32> [[TMP5]]564; CHECK-NEXT: store <2 x i32> [[PREDPHI]], ptr [[TMP1]], align 4, !alias.scope [[META29]], !noalias [[META32]]565; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2566; CHECK-NEXT: [[TMP32:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128567; CHECK-NEXT: br i1 [[TMP32]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP36:![0-9]+]]568; CHECK: for.cond.cleanup:569; CHECK-NEXT: ret void570; CHECK: for.body:571; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[IF_END:%.*]] ], [ 0, [[ENTRY]] ]572; CHECK-NEXT: [[ISD:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDVARS_IV]]573; CHECK-NEXT: [[LSD:%.*]] = load i32, ptr [[ISD]], align 4574; CHECK-NEXT: [[ISD_B:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDVARS_IV]]575; CHECK-NEXT: [[LSD_B:%.*]] = load i32, ptr [[ISD_B]], align 4576; CHECK-NEXT: [[PSD:%.*]] = add nsw i32 [[LSD]], 23577; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100578; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i32 [[LSD]], 200579; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP1]], [[CMP2]], !dbg [[DBG34]]580; CHECK-NEXT: br i1 [[OR_COND]], label [[IF_THEN:%.*]], label [[IF_END]], !dbg [[DBG34]]581; CHECK: if.then:582; CHECK-NEXT: [[SD1:%.*]] = sdiv i32 [[PSD]], [[LSD]]583; CHECK-NEXT: [[RSD:%.*]] = sdiv i32 [[LSD_B]], [[SD1]]584; CHECK-NEXT: br label [[IF_END]]585; CHECK: if.end:586; CHECK-NEXT: [[YSD_0:%.*]] = phi i32 [ [[RSD]], [[IF_THEN]] ], [ [[PSD]], [[FOR_BODY]] ]587; CHECK-NEXT: store i32 [[YSD_0]], ptr [[ISD]], align 4588; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1589; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128590; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP37:![0-9]+]]591;592; UNROLL-NO-VF-LABEL: @pr30172(593; UNROLL-NO-VF-NEXT: entry:594; UNROLL-NO-VF-NEXT: br label [[VECTOR_MEMCHECK:%.*]]595; UNROLL-NO-VF: vector.memcheck:596; UNROLL-NO-VF-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ASD:%.*]], i64 512597; UNROLL-NO-VF-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[BSD:%.*]], i64 512598; UNROLL-NO-VF-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP1]]599; UNROLL-NO-VF-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[BSD]], [[SCEVGEP]]600; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]601; UNROLL-NO-VF-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]602; UNROLL-NO-VF: vector.ph:603; UNROLL-NO-VF-NEXT: br label [[VECTOR_BODY:%.*]]604; UNROLL-NO-VF: vector.body:605; UNROLL-NO-VF-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_SDIV_CONTINUE3:%.*]] ]606; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1607; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDEX]]608; UNROLL-NO-VF-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[TMP1]]609; UNROLL-NO-VF-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4, !alias.scope [[META29:![0-9]+]], !noalias [[META32:![0-9]+]]610; UNROLL-NO-VF-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP3]], align 4, !alias.scope [[META29]], !noalias [[META32]]611; UNROLL-NO-VF-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDEX]]612; UNROLL-NO-VF-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[TMP1]]613; UNROLL-NO-VF-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP6]], align 4, !alias.scope [[META32]]614; UNROLL-NO-VF-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4, !alias.scope [[META32]]615; UNROLL-NO-VF-NEXT: [[TMP10:%.*]] = add nsw i32 [[TMP4]], 23616; UNROLL-NO-VF-NEXT: [[TMP11:%.*]] = add nsw i32 [[TMP5]], 23617; UNROLL-NO-VF-NEXT: [[TMP12:%.*]] = icmp slt i32 [[TMP4]], 100618; UNROLL-NO-VF-NEXT: [[TMP13:%.*]] = icmp slt i32 [[TMP5]], 100619; UNROLL-NO-VF-NEXT: [[TMP17:%.*]] = xor i1 [[TMP12]], true, !dbg [[DBG34:![0-9]+]]620; UNROLL-NO-VF-NEXT: [[TMP14:%.*]] = xor i1 [[TMP13]], true, !dbg [[DBG34]]621; UNROLL-NO-VF-NEXT: [[TMP15:%.*]] = icmp sge i32 [[TMP4]], 200622; UNROLL-NO-VF-NEXT: [[TMP16:%.*]] = icmp sge i32 [[TMP5]], 200623; UNROLL-NO-VF-NEXT: [[TMP18:%.*]] = select i1 [[TMP17]], i1 [[TMP15]], i1 false, !dbg [[DBG35:![0-9]+]]624; UNROLL-NO-VF-NEXT: [[TMP19:%.*]] = select i1 [[TMP14]], i1 [[TMP16]], i1 false, !dbg [[DBG35]]625; UNROLL-NO-VF-NEXT: [[TMP20:%.*]] = or i1 [[TMP18]], [[TMP12]]626; UNROLL-NO-VF-NEXT: [[TMP21:%.*]] = or i1 [[TMP19]], [[TMP13]]627; UNROLL-NO-VF-NEXT: br i1 [[TMP20]], label [[PRED_SDIV_IF:%.*]], label [[PRED_SDIV_CONTINUE:%.*]]628; UNROLL-NO-VF: pred.sdiv.if:629; UNROLL-NO-VF-NEXT: [[TMP22:%.*]] = sdiv i32 [[TMP10]], [[TMP4]]630; UNROLL-NO-VF-NEXT: [[TMP23:%.*]] = sdiv i32 [[TMP8]], [[TMP22]]631; UNROLL-NO-VF-NEXT: br label [[PRED_SDIV_CONTINUE]]632; UNROLL-NO-VF: pred.sdiv.continue:633; UNROLL-NO-VF-NEXT: [[TMP25:%.*]] = phi i32 [ poison, [[VECTOR_BODY]] ], [ [[TMP23]], [[PRED_SDIV_IF]] ]634; UNROLL-NO-VF-NEXT: br i1 [[TMP21]], label [[PRED_SDIV_IF2:%.*]], label [[PRED_SDIV_CONTINUE3]]635; UNROLL-NO-VF: pred.sdiv.if2:636; UNROLL-NO-VF-NEXT: [[TMP26:%.*]] = sdiv i32 [[TMP11]], [[TMP5]]637; UNROLL-NO-VF-NEXT: [[TMP27:%.*]] = sdiv i32 [[TMP9]], [[TMP26]]638; UNROLL-NO-VF-NEXT: br label [[PRED_SDIV_CONTINUE3]]639; UNROLL-NO-VF: pred.sdiv.continue3:640; UNROLL-NO-VF-NEXT: [[TMP29:%.*]] = phi i32 [ poison, [[PRED_SDIV_CONTINUE]] ], [ [[TMP27]], [[PRED_SDIV_IF2]] ]641; UNROLL-NO-VF-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP20]], i32 [[TMP25]], i32 [[TMP10]]642; UNROLL-NO-VF-NEXT: [[PREDPHI4:%.*]] = select i1 [[TMP21]], i32 [[TMP29]], i32 [[TMP11]]643; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI]], ptr [[TMP2]], align 4, !alias.scope [[META29]], !noalias [[META32]]644; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI4]], ptr [[TMP3]], align 4, !alias.scope [[META29]], !noalias [[META32]]645; UNROLL-NO-VF-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2646; UNROLL-NO-VF-NEXT: [[TMP34:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128647; UNROLL-NO-VF-NEXT: br i1 [[TMP34]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP36:![0-9]+]]648; UNROLL-NO-VF: middle.block:649; UNROLL-NO-VF-NEXT: br label [[FOR_COND_CLEANUP:%.*]]650; UNROLL-NO-VF: scalar.ph:651; UNROLL-NO-VF-NEXT: br label [[FOR_BODY:%.*]]652; UNROLL-NO-VF: for.cond.cleanup:653; UNROLL-NO-VF-NEXT: ret void654; UNROLL-NO-VF: for.body:655; UNROLL-NO-VF-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[IF_END:%.*]] ]656; UNROLL-NO-VF-NEXT: [[ISD:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDVARS_IV]]657; UNROLL-NO-VF-NEXT: [[LSD:%.*]] = load i32, ptr [[ISD]], align 4658; UNROLL-NO-VF-NEXT: [[ISD_B:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDVARS_IV]]659; UNROLL-NO-VF-NEXT: [[LSD_B:%.*]] = load i32, ptr [[ISD_B]], align 4660; UNROLL-NO-VF-NEXT: [[PSD:%.*]] = add nsw i32 [[LSD]], 23661; UNROLL-NO-VF-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100662; UNROLL-NO-VF-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[CHECKBB:%.*]], !dbg [[DBG34]]663; UNROLL-NO-VF: checkbb:664; UNROLL-NO-VF-NEXT: [[CMP2:%.*]] = icmp sge i32 [[LSD]], 200665; UNROLL-NO-VF-NEXT: br i1 [[CMP2]], label [[IF_THEN]], label [[IF_END]], !dbg [[DBG35]]666; UNROLL-NO-VF: if.then:667; UNROLL-NO-VF-NEXT: [[SD1:%.*]] = sdiv i32 [[PSD]], [[LSD]]668; UNROLL-NO-VF-NEXT: [[RSD:%.*]] = sdiv i32 [[LSD_B]], [[SD1]]669; UNROLL-NO-VF-NEXT: br label [[IF_END]]670; UNROLL-NO-VF: if.end:671; UNROLL-NO-VF-NEXT: [[YSD_0:%.*]] = phi i32 [ [[RSD]], [[IF_THEN]] ], [ [[PSD]], [[CHECKBB]] ]672; UNROLL-NO-VF-NEXT: store i32 [[YSD_0]], ptr [[ISD]], align 4673; UNROLL-NO-VF-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1674; UNROLL-NO-VF-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128675; UNROLL-NO-VF-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP37:![0-9]+]]676;677entry:678 br label %for.body679 680for.cond.cleanup: ; preds = %if.end681 ret void682 683for.body: ; preds = %if.end, %entry684 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ]685 %isd = getelementptr inbounds i32, ptr %asd, i64 %indvars.iv686 %lsd = load i32, ptr %isd, align 4687 %isd.b = getelementptr inbounds i32, ptr %bsd, i64 %indvars.iv688 %lsd.b = load i32, ptr %isd.b, align 4689 %psd = add nsw i32 %lsd, 23690 %cmp1 = icmp slt i32 %lsd, 100691 br i1 %cmp1, label %if.then, label %checkbb, !dbg !7692 693checkbb: ; preds = %for.body694 %cmp2 = icmp sge i32 %lsd, 200695 br i1 %cmp2, label %if.then, label %if.end, !dbg !8696 697if.then: ; preds = %checkbb, %for.body698 %sd1 = sdiv i32 %psd, %lsd699 %rsd = sdiv i32 %lsd.b, %sd1700 br label %if.end701 702if.end: ; preds = %if.then, %checkbb703 %ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %checkbb ]704 store i32 %ysd.0, ptr %isd, align 4705 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1706 %exitcond = icmp eq i64 %indvars.iv.next, 128707 br i1 %exitcond, label %for.cond.cleanup, label %for.body708}709 710define i32 @predicated_udiv_scalarized_operand(ptr %a, i1 %c, i32 %x, i64 %n) {711; CHECK-LABEL: @predicated_udiv_scalarized_operand(712; CHECK-NEXT: entry:713; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N:%.*]], i64 1)714; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[SMAX]], 2715; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]716; CHECK: vector.ph:717; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[SMAX]], 2718; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[SMAX]], [[N_MOD_VF]]719; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]720; CHECK: vector.body:721; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_UDIV_CONTINUE2:%.*]] ]722; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP18:%.*]], [[PRED_UDIV_CONTINUE2]] ]723; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDEX]]724; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4725; CHECK-NEXT: br i1 [[C:%.*]], label [[PRED_UDIV_IF:%.*]], label [[PRED_UDIV_CONTINUE:%.*]]726; CHECK: pred.udiv.if:727; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 0728; CHECK-NEXT: [[TMP5:%.*]] = add nsw i32 [[TMP4]], [[X:%.*]]729; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 0730; CHECK-NEXT: [[TMP7:%.*]] = udiv i32 [[TMP6]], [[TMP5]]731; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> poison, i32 [[TMP7]], i32 0732; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE]]733; CHECK: pred.udiv.continue:734; CHECK-NEXT: [[TMP9:%.*]] = phi <2 x i32> [ poison, [[VECTOR_BODY]] ], [ [[TMP8]], [[PRED_UDIV_IF]] ]735; CHECK-NEXT: br i1 [[C]], label [[PRED_UDIV_IF1:%.*]], label [[PRED_UDIV_CONTINUE2]]736; CHECK: pred.udiv.if1:737; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 1738; CHECK-NEXT: [[TMP12:%.*]] = add nsw i32 [[TMP11]], [[X]]739; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 1740; CHECK-NEXT: [[TMP14:%.*]] = udiv i32 [[TMP13]], [[TMP12]]741; CHECK-NEXT: [[TMP15:%.*]] = insertelement <2 x i32> [[TMP9]], i32 [[TMP14]], i32 1742; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE2]]743; CHECK: pred.udiv.continue2:744; CHECK-NEXT: [[TMP16:%.*]] = phi <2 x i32> [ [[TMP9]], [[PRED_UDIV_CONTINUE]] ], [ [[TMP15]], [[PRED_UDIV_IF1]] ]745; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[C]], <2 x i32> [[TMP16]], <2 x i32> [[WIDE_LOAD]]746; CHECK-NEXT: [[TMP18]] = add <2 x i32> [[VEC_PHI]], [[PREDPHI]]747; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2748; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]749; CHECK-NEXT: br i1 [[TMP19]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP38:![0-9]+]]750; CHECK: middle.block:751; CHECK-NEXT: [[TMP20:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[TMP18]])752; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[SMAX]], [[N_VEC]]753; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]754; CHECK: scalar.ph:755; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]756; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP20]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]757; CHECK-NEXT: br label [[FOR_BODY:%.*]]758; CHECK: for.body:759; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[FOR_INC:%.*]] ]760; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[T6:%.*]], [[FOR_INC]] ]761; CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]]762; CHECK-NEXT: [[T2:%.*]] = load i32, ptr [[T0]], align 4763; CHECK-NEXT: br i1 [[C]], label [[IF_THEN:%.*]], label [[FOR_INC]]764; CHECK: if.then:765; CHECK-NEXT: [[T3:%.*]] = add nsw i32 [[T2]], [[X]]766; CHECK-NEXT: [[T4:%.*]] = udiv i32 [[T2]], [[T3]]767; CHECK-NEXT: br label [[FOR_INC]]768; CHECK: for.inc:769; CHECK-NEXT: [[T5:%.*]] = phi i32 [ [[T2]], [[FOR_BODY]] ], [ [[T4]], [[IF_THEN]] ]770; CHECK-NEXT: [[T6]] = add i32 [[R]], [[T5]]771; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i64 [[I]], 1772; CHECK-NEXT: [[COND:%.*]] = icmp slt i64 [[I_NEXT]], [[N]]773; CHECK-NEXT: br i1 [[COND]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop [[LOOP39:![0-9]+]]774; CHECK: for.end:775; CHECK-NEXT: [[T7:%.*]] = phi i32 [ [[T6]], [[FOR_INC]] ], [ [[TMP20]], [[MIDDLE_BLOCK]] ]776; CHECK-NEXT: ret i32 [[T7]]777;778; UNROLL-NO-VF-LABEL: @predicated_udiv_scalarized_operand(779; UNROLL-NO-VF-NEXT: entry:780; UNROLL-NO-VF-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N:%.*]], i64 1)781; UNROLL-NO-VF-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[SMAX]], 2782; UNROLL-NO-VF-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]783; UNROLL-NO-VF: vector.ph:784; UNROLL-NO-VF-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[SMAX]], 2785; UNROLL-NO-VF-NEXT: [[N_VEC:%.*]] = sub i64 [[SMAX]], [[N_MOD_VF]]786; UNROLL-NO-VF-NEXT: br label [[VECTOR_BODY:%.*]]787; UNROLL-NO-VF: vector.body:788; UNROLL-NO-VF-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_UDIV_CONTINUE3:%.*]] ]789; UNROLL-NO-VF-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP14:%.*]], [[PRED_UDIV_CONTINUE3]] ]790; UNROLL-NO-VF-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP15:%.*]], [[PRED_UDIV_CONTINUE3]] ]791; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1792; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDEX]]793; UNROLL-NO-VF-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP1]]794; UNROLL-NO-VF-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4795; UNROLL-NO-VF-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP3]], align 4796; UNROLL-NO-VF-NEXT: br i1 [[C:%.*]], label [[PRED_UDIV_IF:%.*]], label [[PRED_UDIV_CONTINUE:%.*]]797; UNROLL-NO-VF: pred.udiv.if:798; UNROLL-NO-VF-NEXT: [[TMP6:%.*]] = add nsw i32 [[TMP4]], [[X:%.*]]799; UNROLL-NO-VF-NEXT: [[TMP7:%.*]] = udiv i32 [[TMP4]], [[TMP6]]800; UNROLL-NO-VF-NEXT: br label [[PRED_UDIV_CONTINUE]]801; UNROLL-NO-VF: pred.udiv.continue:802; UNROLL-NO-VF-NEXT: [[TMP8:%.*]] = phi i32 [ poison, [[VECTOR_BODY]] ], [ [[TMP7]], [[PRED_UDIV_IF]] ]803; UNROLL-NO-VF-NEXT: br i1 [[C]], label [[PRED_UDIV_IF2:%.*]], label [[PRED_UDIV_CONTINUE3]]804; UNROLL-NO-VF: pred.udiv.if2:805; UNROLL-NO-VF-NEXT: [[TMP9:%.*]] = add nsw i32 [[TMP5]], [[X]]806; UNROLL-NO-VF-NEXT: [[TMP10:%.*]] = udiv i32 [[TMP5]], [[TMP9]]807; UNROLL-NO-VF-NEXT: br label [[PRED_UDIV_CONTINUE3]]808; UNROLL-NO-VF: pred.udiv.continue3:809; UNROLL-NO-VF-NEXT: [[TMP11:%.*]] = phi i32 [ poison, [[PRED_UDIV_CONTINUE]] ], [ [[TMP10]], [[PRED_UDIV_IF2]] ]810; UNROLL-NO-VF-NEXT: [[PREDPHI:%.*]] = select i1 [[C]], i32 [[TMP8]], i32 [[TMP4]]811; UNROLL-NO-VF-NEXT: [[PREDPHI4:%.*]] = select i1 [[C]], i32 [[TMP11]], i32 [[TMP5]]812; UNROLL-NO-VF-NEXT: [[TMP14]] = add i32 [[VEC_PHI]], [[PREDPHI]]813; UNROLL-NO-VF-NEXT: [[TMP15]] = add i32 [[VEC_PHI1]], [[PREDPHI4]]814; UNROLL-NO-VF-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2815; UNROLL-NO-VF-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]816; UNROLL-NO-VF-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP38:![0-9]+]]817; UNROLL-NO-VF: middle.block:818; UNROLL-NO-VF-NEXT: [[BIN_RDX:%.*]] = add i32 [[TMP15]], [[TMP14]]819; UNROLL-NO-VF-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[SMAX]], [[N_VEC]]820; UNROLL-NO-VF-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]821; UNROLL-NO-VF: scalar.ph:822; UNROLL-NO-VF-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]823; UNROLL-NO-VF-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[BIN_RDX]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]824; UNROLL-NO-VF-NEXT: br label [[FOR_BODY:%.*]]825; UNROLL-NO-VF: for.body:826; UNROLL-NO-VF-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[FOR_INC:%.*]] ]827; UNROLL-NO-VF-NEXT: [[R:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[T6:%.*]], [[FOR_INC]] ]828; UNROLL-NO-VF-NEXT: [[T0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]]829; UNROLL-NO-VF-NEXT: [[T2:%.*]] = load i32, ptr [[T0]], align 4830; UNROLL-NO-VF-NEXT: br i1 [[C]], label [[IF_THEN:%.*]], label [[FOR_INC]]831; UNROLL-NO-VF: if.then:832; UNROLL-NO-VF-NEXT: [[T3:%.*]] = add nsw i32 [[T2]], [[X]]833; UNROLL-NO-VF-NEXT: [[T4:%.*]] = udiv i32 [[T2]], [[T3]]834; UNROLL-NO-VF-NEXT: br label [[FOR_INC]]835; UNROLL-NO-VF: for.inc:836; UNROLL-NO-VF-NEXT: [[T5:%.*]] = phi i32 [ [[T2]], [[FOR_BODY]] ], [ [[T4]], [[IF_THEN]] ]837; UNROLL-NO-VF-NEXT: [[T6]] = add i32 [[R]], [[T5]]838; UNROLL-NO-VF-NEXT: [[I_NEXT]] = add nuw nsw i64 [[I]], 1839; UNROLL-NO-VF-NEXT: [[COND:%.*]] = icmp slt i64 [[I_NEXT]], [[N]]840; UNROLL-NO-VF-NEXT: br i1 [[COND]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop [[LOOP39:![0-9]+]]841; UNROLL-NO-VF: for.end:842; UNROLL-NO-VF-NEXT: [[T7:%.*]] = phi i32 [ [[T6]], [[FOR_INC]] ], [ [[BIN_RDX]], [[MIDDLE_BLOCK]] ]843; UNROLL-NO-VF-NEXT: ret i32 [[T7]]844;845entry:846 br label %for.body847 848 849; Test predicating an instruction that feeds a vectorizable use, when unrolled850; but not vectorized. Derived from pr34248 reproducer.851for.body:852 %i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ]853 %r = phi i32 [ 0, %entry ], [ %t6, %for.inc ]854 %t0 = getelementptr inbounds i32, ptr %a, i64 %i855 %t2 = load i32, ptr %t0, align 4856 br i1 %c, label %if.then, label %for.inc857 858if.then:859 %t3 = add nsw i32 %t2, %x860 %t4 = udiv i32 %t2, %t3861 br label %for.inc862 863for.inc:864 %t5 = phi i32 [ %t2, %for.body ], [ %t4, %if.then]865 %t6 = add i32 %r, %t5866 %i.next = add nuw nsw i64 %i, 1867 %cond = icmp slt i64 %i.next, %n868 br i1 %cond, label %for.body, label %for.end869 870for.end:871 %t7 = phi i32 [ %t6, %for.inc ]872 ret i32 %t7873}874 875!llvm.dbg.cu = !{!0}876!llvm.module.flags = !{!3, !4}877 878!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: NoDebug, enums: !2)879!1 = !DIFile(filename: "/tmp/s.c", directory: "/tmp")880!2 = !{}881!3 = !{i32 2, !"Debug Info Version", i32 3}882!4 = !{i32 7, !"PIC Level", i32 2}883!5 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 4, type: !6, scopeLine: 4, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2)884!6 = !DISubroutineType(types: !2)885!7 = !DILocation(line: 5, column: 21, scope: !5)886!8 = !DILocation(line: 5, column: 3, scope: !5)887 888 889