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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -force-vector-width=4 -enable-interleaved-mem-accesses=true -S %s | FileCheck %s3 4target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128-Fn32"5 6define void @gep_for_first_member_does_not_dominate_insert_point(ptr %str, ptr noalias %dst) {7; CHECK-LABEL: define void @gep_for_first_member_does_not_dominate_insert_point(8; CHECK-SAME: ptr [[STR:%.*]], ptr noalias [[DST:%.*]]) {9; CHECK-NEXT: [[ENTRY:.*:]]10; CHECK-NEXT: br label %[[VECTOR_PH:.*]]11; CHECK: [[VECTOR_PH]]:12; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]13; CHECK: [[VECTOR_BODY]]:14; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]15; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 216; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i64 [[OFFSET_IDX]], 117; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[STR]], i64 [[TMP2]]18; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[TMP3]], i32 -119; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <8 x i8>, ptr [[TMP4]], align 120; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x i8> [[WIDE_VEC]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>21; CHECK-NEXT: [[STRIDED_VEC2:%.*]] = shufflevector <8 x i8> [[WIDE_VEC]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>22; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i8> [[STRIDED_VEC2]], [[STRIDED_VEC]]23; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[INDEX]]24; CHECK-NEXT: store <4 x i8> [[TMP5]], ptr [[TMP6]], align 125; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 426; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10027; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]28; CHECK: [[MIDDLE_BLOCK]]:29; CHECK-NEXT: br label %[[EXIT:.*]]30; CHECK: [[EXIT]]:31; CHECK-NEXT: ret void32;33entry:34 br label %loop35 36loop: ; preds = %loop, %entry37 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]38 %iv2 = phi i64 [ 0, %entry ], [ %iv2.next, %loop ]39 %or.1 = or disjoint i64 %iv2, 140 %gep1 = getelementptr i8, ptr %str, i64 %or.141 %1 = load i8, ptr %gep1, align 142 %gep0 = getelementptr i8, ptr %str, i64 %iv243 %2 = load i8, ptr %gep0, align 144 %add = add i8 %1, %245 %gep.dst = getelementptr inbounds i8, ptr %dst, i64 %iv46 store i8 %add, ptr %gep.dst, align 147 %iv2.next = add i64 %iv2, 248 %iv.next = add i64 %iv, 149 %ec = icmp eq i64 %iv.next, 10050 br i1 %ec, label %exit, label %loop51 52exit:53 ret void54}55 56define void @test_ig_insert_pos_at_end_of_vpbb(ptr noalias %dst, ptr noalias %src, i16 %x, i64 %N) {57; CHECK-LABEL: define void @test_ig_insert_pos_at_end_of_vpbb(58; CHECK-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]], i16 [[X:%.*]], i64 [[N:%.*]]) {59; CHECK-NEXT: [[ENTRY:.*]]:60; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 161; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP0]], 462; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]63; CHECK: [[VECTOR_PH]]:64; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 465; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[N_MOD_VF]], 066; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i64 4, i64 [[N_MOD_VF]]67; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP2]]68; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]69; CHECK: [[VECTOR_BODY]]:70; CHECK-NEXT: [[TMP3:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]71; CHECK-NEXT: [[TMP4:%.*]] = getelementptr nusw { i16, i16, i16, i16 }, ptr [[SRC]], i64 [[TMP3]], i32 272; CHECK-NEXT: [[TMP5:%.*]] = getelementptr nusw i8, ptr [[TMP4]], i32 -473; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <16 x i16>, ptr [[TMP5]], align 274; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <16 x i16> [[WIDE_VEC]], <16 x i16> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>75; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <16 x i16> [[WIDE_VEC]], <16 x i16> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14>76; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i16> [[STRIDED_VEC]], i32 377; CHECK-NEXT: store i16 [[TMP6]], ptr [[DST]], align 278; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP3]], 479; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]80; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]81; CHECK: [[MIDDLE_BLOCK]]:82; CHECK-NEXT: br label %[[SCALAR_PH]]83; CHECK: [[SCALAR_PH]]:84; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]85; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]86; CHECK: [[LOOP_HEADER]]:87; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]88; CHECK-NEXT: [[GEP_2:%.*]] = getelementptr nusw { i16, i16, i16, i16 }, ptr [[SRC]], i64 [[IV]], i32 289; CHECK-NEXT: [[L_1:%.*]] = load i16, ptr [[GEP_2]], align 290; CHECK-NEXT: switch i16 [[L_1]], label %[[THEN:.*]] [91; CHECK-NEXT: i16 0, label %[[LOOP_LATCH]]92; CHECK-NEXT: i16 1, label %[[LOOP_LATCH]]93; CHECK-NEXT: ]94; CHECK: [[THEN]]:95; CHECK-NEXT: br label %[[LOOP_LATCH]]96; CHECK: [[LOOP_LATCH]]:97; CHECK-NEXT: [[P:%.*]] = phi i16 [ [[X]], %[[THEN]] ], [ 0, %[[LOOP_HEADER]] ], [ 0, %[[LOOP_HEADER]] ]98; CHECK-NEXT: [[GEP_0:%.*]] = getelementptr { i16, i16, i16, i16 }, ptr [[SRC]], i64 [[IV]]99; CHECK-NEXT: [[L_2:%.*]] = load i16, ptr [[GEP_0]], align 2100; CHECK-NEXT: store i16 [[L_2]], ptr [[DST]], align 2101; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1102; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]103; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP4:![0-9]+]]104; CHECK: [[EXIT]]:105; CHECK-NEXT: ret void106;107entry:108 br label %loop.header109 110loop.header: ; preds = %loop.latch, %entry111 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]112 %gep.2 = getelementptr nusw { i16, i16, i16, i16 }, ptr %src, i64 %iv, i32 2113 %l.1 = load i16, ptr %gep.2, align 2114 switch i16 %l.1, label %then [115 i16 0, label %loop.latch116 i16 1, label %loop.latch117 ]118 119then:120 br label %loop.latch121 122loop.latch:123 %p = phi i16 [ %x, %then ], [ 0, %loop.header ], [ 0, %loop.header ]124 %gep.0 = getelementptr { i16, i16, i16, i16 }, ptr %src, i64 %iv125 %l.2 = load i16, ptr %gep.0, align 2126 store i16 %l.2, ptr %dst, align 2127 %iv.next = add nsw i64 %iv, 1128 %ec = icmp eq i64 %iv, %N129 br i1 %ec, label %exit, label %loop.header130 131exit:132 ret void133}134 135; FIXME: Currently the start address of the interleav group is computed136; incorrectly.137define i64 @interleave_group_load_pointer_type(ptr %start, ptr %end) {138; CHECK-LABEL: define i64 @interleave_group_load_pointer_type(139; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {140; CHECK-NEXT: [[ENTRY:.*]]:141; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64142; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64143; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[END1]], [[START2]]144; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[TMP0]], 24145; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1146; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP2]], 4147; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]148; CHECK: [[VECTOR_PH]]:149; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 4150; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[N_MOD_VF]], 0151; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i64 4, i64 [[N_MOD_VF]]152; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[TMP4]]153; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[N_VEC]], 24154; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]155; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]156; CHECK: [[VECTOR_BODY]]:157; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]158; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ]159; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 24160; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]]161; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 16162; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP7]], i32 -8163; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <12 x ptr>, ptr [[TMP8]], align 8164; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <12 x ptr> [[WIDE_VEC]], <12 x ptr> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>165; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <12 x ptr> [[WIDE_VEC]], <12 x ptr> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>166; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint <4 x ptr> [[STRIDED_VEC3]] to <4 x i64>167; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint <4 x ptr> [[STRIDED_VEC]] to <4 x i64>168; CHECK-NEXT: [[TMP11:%.*]] = or <4 x i64> [[TMP9]], [[TMP10]]169; CHECK-NEXT: [[TMP12]] = or <4 x i64> [[TMP11]], [[VEC_PHI]]170; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4171; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]172; CHECK-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]173; CHECK: [[MIDDLE_BLOCK]]:174; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> [[TMP12]])175; CHECK-NEXT: br label %[[SCALAR_PH]]176; CHECK: [[SCALAR_PH]]:177; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]178; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP14]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]179; CHECK-NEXT: br label %[[LOOP:.*]]180; CHECK: [[LOOP]]:181; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ]182; CHECK-NEXT: [[RED:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[RED_NEXT:%.*]], %[[LOOP]] ]183; CHECK-NEXT: [[GEP_16:%.*]] = getelementptr i8, ptr [[PTR_IV]], i64 16184; CHECK-NEXT: [[L_16:%.*]] = load ptr, ptr [[GEP_16]], align 8185; CHECK-NEXT: [[P_16:%.*]] = ptrtoint ptr [[L_16]] to i64186; CHECK-NEXT: [[GEP_8:%.*]] = getelementptr i8, ptr [[PTR_IV]], i64 8187; CHECK-NEXT: [[L_8:%.*]] = load ptr, ptr [[GEP_8]], align 8188; CHECK-NEXT: [[P_8:%.*]] = ptrtoint ptr [[L_8]] to i64189; CHECK-NEXT: [[OR_1:%.*]] = or i64 [[P_16]], [[P_8]]190; CHECK-NEXT: [[RED_NEXT]] = or i64 [[OR_1]], [[RED]]191; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr nusw i8, ptr [[PTR_IV]], i64 24192; CHECK-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV]], [[END]]193; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]194; CHECK: [[EXIT]]:195; CHECK-NEXT: [[RED_NEXT_LCSSA:%.*]] = phi i64 [ [[RED_NEXT]], %[[LOOP]] ]196; CHECK-NEXT: ret i64 [[RED_NEXT_LCSSA]]197;198entry:199 br label %loop200 201loop:202 %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop ]203 %red = phi i64 [ 0, %entry ], [ %red.next, %loop ]204 %gep.16 = getelementptr i8, ptr %ptr.iv, i64 16205 %l.16 = load ptr, ptr %gep.16, align 8206 %p.16 = ptrtoint ptr %l.16 to i64207 %gep.8 = getelementptr i8, ptr %ptr.iv, i64 8208 %l.8 = load ptr, ptr %gep.8, align 8209 %p.8 = ptrtoint ptr %l.8 to i64210 %or.1 = or i64 %p.16, %p.8211 %red.next = or i64 %or.1, %red212 %ptr.iv.next = getelementptr nusw i8, ptr %ptr.iv, i64 24213 %ec = icmp eq ptr %ptr.iv, %end214 br i1 %ec, label %exit, label %loop215 216exit:217 ret i64 %red.next218}219;.220; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}221; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}222; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}223; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}224; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META2]], [[META1]]}225; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]}226; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META2]], [[META1]]}227;.228