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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -enable-interleaved-mem-accesses=true < %s | FileCheck %s3 4; When merging two stores with interleaved access vectorization, make sure we5; propagate the alias information from all scalar stores to form the most6; generic alias info.7 8target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"9 10%struct.Vec4r = type { double, double, double, double }11%struct.Vec2r = type { double, double }12 13; The new store for the interleave group should alias any double rather than one of the fields of Vec2r.14define void @merge_tbaa_interleave_group(ptr nocapture readonly %p, ptr noalias %cp, i32 %i)15; CHECK-LABEL: define void @merge_tbaa_interleave_group(16; CHECK-SAME: ptr readonly captures(none) [[P:%.*]], ptr noalias [[CP:%.*]], i32 [[I:%.*]]) {17; CHECK-NEXT: [[ENTRY:.*:]]18; CHECK-NEXT: br label %[[VECTOR_PH:.*]]19; CHECK: [[VECTOR_PH]]:20; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]21; CHECK: [[VECTOR_BODY]]:22; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]23; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 024; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 125; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_VEC4R:%.*]], ptr [[P]], i64 [[TMP0]], i32 026; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_VEC4R]], ptr [[P]], i64 [[TMP1]], i32 027; CHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP2]], align 8, !tbaa [[TBAA0:![0-9]+]]28; CHECK-NEXT: [[TMP5:%.*]] = load double, ptr [[TMP3]], align 8, !tbaa [[TBAA0]]29; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> poison, double [[TMP4]], i32 030; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x double> [[TMP6]], double [[TMP5]], i32 131; CHECK-NEXT: [[TMP8:%.*]] = fmul <2 x double> [[TMP7]], splat (double 2.000000e+00)32; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [20 x %struct.Vec2r], ptr [[CP]], i64 0, i64 [[TMP0]], i32 033; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_VEC4R]], ptr [[P]], i64 [[TMP0]], i32 134; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_VEC4R]], ptr [[P]], i64 [[TMP1]], i32 135; CHECK-NEXT: [[TMP12:%.*]] = load double, ptr [[TMP10]], align 8, !tbaa [[TBAA5:![0-9]+]]36; CHECK-NEXT: [[TMP13:%.*]] = load double, ptr [[TMP11]], align 8, !tbaa [[TBAA5]]37; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x double> poison, double [[TMP12]], i32 038; CHECK-NEXT: [[TMP15:%.*]] = insertelement <2 x double> [[TMP14]], double [[TMP13]], i32 139; CHECK-NEXT: [[TMP16:%.*]] = fmul <2 x double> [[TMP15]], splat (double 3.000000e+00)40; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <2 x double> [[TMP8]], <2 x double> [[TMP16]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>41; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP17]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>42; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP9]], align 8, !tbaa [[TBAA6:![0-9]+]]43; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 244; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 445; CHECK-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]46; CHECK: [[MIDDLE_BLOCK]]:47; CHECK-NEXT: br label %[[EXIT:.*]]48; CHECK: [[EXIT]]:49; CHECK-NEXT: ret void50;51{52entry:53 br label %loop54 55loop: ; preds = %loop, %entry56 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]57 %x = getelementptr inbounds %struct.Vec4r, ptr %p, i64 %iv, i32 058 %0 = load double, ptr %x, align 8, !tbaa !359 %mul = fmul double %0, 2.000000e+0060 %x4 = getelementptr inbounds [20 x %struct.Vec2r], ptr %cp, i64 0, i64 %iv, i32 061 store double %mul, ptr %x4, align 8, !tbaa !862 %y = getelementptr inbounds %struct.Vec4r, ptr %p, i64 %iv, i32 163 %1 = load double, ptr %y, align 8, !tbaa !1064 %mul7 = fmul double %1, 3.000000e+0065 %y10 = getelementptr inbounds [20 x %struct.Vec2r], ptr %cp, i64 0, i64 %iv, i32 166 store double %mul7, ptr %y10, align 8, !tbaa !1167 %iv.next = add nuw nsw i64 %iv, 168 %ec = icmp eq i64 %iv.next, 469 br i1 %ec, label %exit, label %loop70 71exit:72 ret void73}74 75; Make sure no !tbaa is added to neither the interleave group load nor the store.76define void @ir_tbaa_different(ptr %base, ptr %end, ptr %src) {77; CHECK-LABEL: define void @ir_tbaa_different(78; CHECK-SAME: ptr [[BASE:%.*]], ptr [[END:%.*]], ptr [[SRC:%.*]]) {79; CHECK-NEXT: [[ENTRY:.*]]:80; CHECK-NEXT: [[BASE2:%.*]] = ptrtoint ptr [[BASE]] to i6481; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i6482; CHECK-NEXT: [[BASE3:%.*]] = ptrtoint ptr [[BASE]] to i6483; CHECK-NEXT: [[END2:%.*]] = ptrtoint ptr [[END]] to i6484; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -885; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[BASE2]]86; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 387; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 188; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 289; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]90; CHECK: [[VECTOR_MEMCHECK]]:91; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[END2]], -892; CHECK-NEXT: [[TMP12:%.*]] = sub i64 [[TMP10]], [[BASE3]]93; CHECK-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP12]], 394; CHECK-NEXT: [[TMP14:%.*]] = shl nuw i64 [[TMP13]], 395; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP14]], 896; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP15]]97; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[SRC]], i64 498; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[BASE]], [[SCEVGEP3]]99; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SRC]], [[SCEVGEP]]100; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]101; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]102; CHECK: [[VECTOR_PH]]:103; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 2104; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]105; CHECK-NEXT: [[TMP11:%.*]] = load float, ptr [[SRC]], align 4, !alias.scope [[META10:![0-9]+]]106; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x float> poison, float [[TMP11]], i64 0107; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x float> [[BROADCAST_SPLATINSERT]], <2 x float> poison, <2 x i32> zeroinitializer108; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 8109; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP4]]110; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]111; CHECK: [[VECTOR_BODY]]:112; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]113; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8114; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[OFFSET_IDX]]115; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <4 x float>, ptr [[NEXT_GEP]], align 4, !alias.scope [[META13:![0-9]+]], !noalias [[META10]]116; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x float> [[WIDE_VEC]], <4 x float> poison, <2 x i32> <i32 0, i32 2>117; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <4 x float> [[WIDE_VEC]], <4 x float> poison, <2 x i32> <i32 1, i32 3>118; CHECK-NEXT: [[TMP6:%.*]] = fmul <2 x float> [[STRIDED_VEC]], [[BROADCAST_SPLAT]]119; CHECK-NEXT: [[TMP7:%.*]] = fmul <2 x float> [[STRIDED_VEC3]], [[BROADCAST_SPLAT]]120; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> [[TMP7]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>121; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x float> [[TMP8]], <4 x float> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>122; CHECK-NEXT: store <4 x float> [[INTERLEAVED_VEC]], ptr [[NEXT_GEP]], align 4, !alias.scope [[META13]], !noalias [[META10]]123; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2124; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]125; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]126; CHECK: [[MIDDLE_BLOCK]]:127; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]128; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]129; CHECK: [[SCALAR_PH]]:130; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ [[BASE]], %[[ENTRY]] ], [ [[BASE]], %[[VECTOR_MEMCHECK]] ]131; CHECK-NEXT: br label %[[LOOP:.*]]132; CHECK: [[LOOP]]:133; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ]134; CHECK-NEXT: [[L_INVAR:%.*]] = load float, ptr [[SRC]], align 4135; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds nuw i8, ptr [[PTR_IV]], i64 8136; CHECK-NEXT: [[L_1:%.*]] = load float, ptr [[PTR_IV]], align 4137; CHECK-NEXT: [[MUL_1:%.*]] = fmul float [[L_1]], [[L_INVAR]]138; CHECK-NEXT: store float [[MUL_1]], ptr [[PTR_IV]], align 4, !tbaa [[TBAA16:![0-9]+]]139; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr inbounds nuw i8, ptr [[PTR_IV]], i64 4140; CHECK-NEXT: [[L_2:%.*]] = load float, ptr [[GEP_1]], align 4, !tbaa [[TBAA18:![0-9]+]]141; CHECK-NEXT: [[MUL_2:%.*]] = fmul float [[L_2]], [[L_INVAR]]142; CHECK-NEXT: store float [[MUL_2]], ptr [[GEP_1]], align 4143; CHECK-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]144; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP19:![0-9]+]]145; CHECK: [[EXIT]]:146; CHECK-NEXT: ret void147;148entry:149 br label %loop150 151loop:152 %ptr.iv = phi ptr [ %base, %entry ], [ %ptr.iv.next, %loop ]153 %l.invar = load float, ptr %src154 %ptr.iv.next = getelementptr inbounds nuw i8, ptr %ptr.iv, i64 8155 %l.0 = load float, ptr %ptr.iv, align 4156 %mul.0 = fmul float %l.0, %l.invar157 store float %mul.0, ptr %ptr.iv, align 4, !tbaa !8158 %gep.1 = getelementptr inbounds nuw i8, ptr %ptr.iv, i64 4159 %l.1 = load float, ptr %gep.1, align 4, !tbaa !11160 %mul.1 = fmul float %l.1, %l.invar161 store float %mul.1, ptr %gep.1, align 4162 %ec = icmp eq ptr %ptr.iv.next, %end163 br i1 %ec, label %exit, label %loop164 165exit:166 ret void167}168 169 170define void @noalias_metadata_from_versioning(ptr %base, ptr %end, ptr %src) {171; CHECK-LABEL: define void @noalias_metadata_from_versioning(172; CHECK-SAME: ptr [[BASE:%.*]], ptr [[END:%.*]], ptr [[SRC:%.*]]) {173; CHECK-NEXT: [[ENTRY:.*]]:174; CHECK-NEXT: [[BASE2:%.*]] = ptrtoint ptr [[BASE]] to i64175; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64176; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8177; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[BASE2]]178; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3179; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1180; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2181; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]182; CHECK: [[VECTOR_PH]]:183; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 2184; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]185; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 8186; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP4]]187; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]188; CHECK: [[VECTOR_BODY]]:189; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]190; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8191; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[OFFSET_IDX]]192; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <4 x float>, ptr [[NEXT_GEP]], align 4193; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x float> [[WIDE_VEC]], <4 x float> poison, <2 x i32> <i32 0, i32 2>194; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <4 x float> [[WIDE_VEC]], <4 x float> poison, <2 x i32> <i32 1, i32 3>195; CHECK-NEXT: [[TMP6:%.*]] = fmul <2 x float> [[STRIDED_VEC]], splat (float 1.000000e+01)196; CHECK-NEXT: [[TMP7:%.*]] = fmul <2 x float> [[STRIDED_VEC3]], splat (float 1.000000e+01)197; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> [[TMP7]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>198; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x float> [[TMP8]], <4 x float> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>199; CHECK-NEXT: store <4 x float> [[INTERLEAVED_VEC]], ptr [[NEXT_GEP]], align 4200; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2201; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]202; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]203; CHECK: [[MIDDLE_BLOCK]]:204; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]205; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]206; CHECK: [[SCALAR_PH]]:207; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ [[BASE]], %[[ENTRY]] ]208; CHECK-NEXT: br label %[[LOOP:.*]]209; CHECK: [[LOOP]]:210; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ]211; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds nuw i8, ptr [[PTR_IV]], i64 8212; CHECK-NEXT: [[L_0:%.*]] = load float, ptr [[PTR_IV]], align 4213; CHECK-NEXT: [[MUL_0:%.*]] = fmul float [[L_0]], 1.000000e+01214; CHECK-NEXT: store float [[MUL_0]], ptr [[PTR_IV]], align 4215; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr inbounds nuw i8, ptr [[PTR_IV]], i64 4216; CHECK-NEXT: [[L_1:%.*]] = load float, ptr [[GEP_1]], align 4217; CHECK-NEXT: [[MUL_1:%.*]] = fmul float [[L_1]], 1.000000e+01218; CHECK-NEXT: store float [[MUL_1]], ptr [[GEP_1]], align 4219; CHECK-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]220; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP21:![0-9]+]]221; CHECK: [[EXIT]]:222; CHECK-NEXT: ret void223;224entry:225 br label %loop226 227loop:228 %ptr.iv = phi ptr [ %base, %entry ], [ %ptr.iv.next, %loop ]229 %ptr.iv.next = getelementptr inbounds nuw i8, ptr %ptr.iv, i64 8230 %l.0 = load float, ptr %ptr.iv, align 4231 %mul.0 = fmul float %l.0, 10.0232 store float %mul.0, ptr %ptr.iv, align 4233 %gep.1 = getelementptr inbounds nuw i8, ptr %ptr.iv, i64 4234 %l.1 = load float, ptr %gep.1, align 4235 %mul.1 = fmul float %l.1, 10.0236 store float %mul.1, ptr %gep.1, align 4237 %ec = icmp eq ptr %ptr.iv.next, %end238 br i1 %ec, label %exit, label %loop239 240exit:241 ret void242}243 244!3 = !{!4, !5, i64 0}245!4 = !{!"Vec4r", !5, i64 0, !5, i64 8, !5, i64 16, !5, i64 24}246!5 = !{!"double", !6, i64 0}247!6 = !{!"omnipotent char", !7, i64 0}248!7 = !{!"Simple C/C++ TBAA"}249!8 = !{!9, !5, i64 0}250!9 = !{!"Vec2r", !5, i64 0, !5, i64 8}251!10 = !{!4, !5, i64 8}252!11 = !{!9, !5, i64 8}253;.254; CHECK: [[TBAA0]] = !{[[META1:![0-9]+]], [[META2:![0-9]+]], i64 0}255; CHECK: [[META1]] = !{!"Vec4r", [[META2]], i64 0, [[META2]], i64 8, [[META2]], i64 16, [[META2]], i64 24}256; CHECK: [[META2]] = !{!"double", [[META3:![0-9]+]], i64 0}257; CHECK: [[META3]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0}258; CHECK: [[META4]] = !{!"Simple C/C++ TBAA"}259; CHECK: [[TBAA5]] = !{[[META1]], [[META2]], i64 8}260; CHECK: [[TBAA6]] = !{[[META2]], [[META2]], i64 0}261; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META8:![0-9]+]], [[META9:![0-9]+]]}262; CHECK: [[META8]] = !{!"llvm.loop.isvectorized", i32 1}263; CHECK: [[META9]] = !{!"llvm.loop.unroll.runtime.disable"}264; CHECK: [[META10]] = !{[[META11:![0-9]+]]}265; CHECK: [[META11]] = distinct !{[[META11]], [[META12:![0-9]+]]}266; CHECK: [[META12]] = distinct !{[[META12]], !"LVerDomain"}267; CHECK: [[META13]] = !{[[META14:![0-9]+]]}268; CHECK: [[META14]] = distinct !{[[META14]], [[META12]]}269; CHECK: [[LOOP15]] = distinct !{[[LOOP15]], [[META8]], [[META9]]}270; CHECK: [[TBAA16]] = !{[[META17:![0-9]+]], [[META2]], i64 0}271; CHECK: [[META17]] = !{!"Vec2r", [[META2]], i64 0, [[META2]], i64 8}272; CHECK: [[TBAA18]] = !{[[META17]], [[META2]], i64 8}273; CHECK: [[LOOP19]] = distinct !{[[LOOP19]], [[META8]]}274; CHECK: [[LOOP20]] = distinct !{[[LOOP20]], [[META8]], [[META9]]}275; CHECK: [[LOOP21]] = distinct !{[[LOOP21]], [[META9]], [[META8]]}276;.277