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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -passes='print<scalar-evolution>,loop-vectorize' -force-vector-width=4 -scalar-evolution-classify-expressions=false -S %s | FileCheck %s3 4; Test case for https://github.com/llvm/llvm-project/issues/119665.5 6; %loop.2's backedge-taken-count depends on %add.1 from %loop.1 via its7; corresponding SCEV at the scope of %loop.2. After vectorizing %loop.1, %add.18; isn't available at the entry of %loop.2 anymore and %add.1 at %loop.2's scope9; must be invalidated, as well as %loop.2's backedge-taken count.10define void @test_invalidate_scevs_at_scope(ptr %p) {11; CHECK-LABEL: define void @test_invalidate_scevs_at_scope(12; CHECK-SAME: ptr [[P:%.*]]) {13; CHECK-NEXT: [[ENTRY:.*:]]14; CHECK-NEXT: br label %[[VECTOR_PH:.*]]15; CHECK: [[VECTOR_PH]]:16; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]17; CHECK: [[VECTOR_BODY]]:18; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]19; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 420; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], 10021; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]22; CHECK: [[MIDDLE_BLOCK]]:23; CHECK-NEXT: br label %[[SCALAR_PH:.*]]24; CHECK: [[SCALAR_PH]]:25; CHECK-NEXT: br label %[[LOOP_1:.*]]26; CHECK: [[LOOP_1]]:27; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ 100, %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP_1]] ]28; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[P]], align 429; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[TMP4]], [[IV_1]]30; CHECK-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 131; CHECK-NEXT: [[C_1:%.*]] = icmp eq i32 [[IV_1]], 10032; CHECK-NEXT: br i1 [[C_1]], label %[[EXIT_1:.*]], label %[[LOOP_1]], !llvm.loop [[LOOP3:![0-9]+]]33; CHECK: [[EXIT_1]]:34; CHECK-NEXT: [[ADD_LCSSA1:%.*]] = phi i32 [ [[ADD_1]], %[[LOOP_1]] ]35; CHECK-NEXT: [[ADD_LCSSA:%.*]] = add i32 [[TMP4]], 10036; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[ADD_LCSSA]], i32 100)37; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[SMAX]], -10038; CHECK-NEXT: [[TMP5:%.*]] = sub i32 [[TMP3]], [[TMP4]]39; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i6440; CHECK-NEXT: [[TMP7:%.*]] = add nuw nsw i64 [[TMP6]], 141; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP7]], 442; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH1:.*]], label %[[VECTOR_PH2:.*]]43; CHECK: [[VECTOR_PH2]]:44; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP7]], 445; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP7]], [[N_MOD_VF]]46; CHECK-NEXT: br label %[[VECTOR_BODY3:.*]]47; CHECK: [[VECTOR_BODY3]]:48; CHECK-NEXT: [[INDEX5:%.*]] = phi i64 [ 0, %[[VECTOR_PH2]] ], [ [[INDEX_NEXT8:%.*]], %[[VECTOR_BODY3]] ]49; CHECK-NEXT: [[VEC_IND6:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH2]] ], [ [[VEC_IND_NEXT7:%.*]], %[[VECTOR_BODY3]] ]50; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[P]], i64 [[INDEX5]]51; CHECK-NEXT: store <4 x i64> [[VEC_IND6]], ptr [[TMP9]], align 452; CHECK-NEXT: [[INDEX_NEXT8]] = add nuw i64 [[INDEX5]], 453; CHECK-NEXT: [[VEC_IND_NEXT7]] = add <4 x i64> [[VEC_IND6]], splat (i64 4)54; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT8]], [[N_VEC]]55; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK6:.*]], label %[[VECTOR_BODY3]], !llvm.loop [[LOOP4:![0-9]+]]56; CHECK: [[MIDDLE_BLOCK6]]:57; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP7]], [[N_VEC]]58; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT_2:.*]], label %[[SCALAR_PH1]]59; CHECK: [[SCALAR_PH1]]:60; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK6]] ], [ 0, %[[EXIT_1]] ]61; CHECK-NEXT: br label %[[LOOP_2:.*]]62; CHECK: [[LOOP_2]]:63; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH1]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP_2]] ]64; CHECK-NEXT: [[IV_2_TRUNC:%.*]] = trunc i64 [[IV_2]] to i3265; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], 166; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[P]], i64 [[IV_2]]67; CHECK-NEXT: store i64 [[IV_2]], ptr [[GEP]], align 468; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[ADD_LCSSA1]], [[IV_2_TRUNC]]69; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[ADD_2]], 10070; CHECK-NEXT: br i1 [[C_2]], label %[[LOOP_2]], label %[[EXIT_2]], !llvm.loop [[LOOP5:![0-9]+]]71; CHECK: [[EXIT_2]]:72; CHECK-NEXT: ret void73;74entry:75 br label %loop.176 77loop.1:78 %iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop.1 ]79 %1 = load i32, ptr %p, align 480 %add.1 = add i32 %1, %iv.181 %iv.1.next = add i32 %iv.1, 182 %c.1 = icmp eq i32 %iv.1, 10083 br i1 %c.1, label %exit.1, label %loop.184 85exit.1:86 %add.lcssa = phi i32 [ %add.1, %loop.1 ]87 br label %loop.288 89loop.2:90 %iv.2 = phi i64 [ 0, %exit.1 ], [ %iv.2.next, %loop.2 ]91 %iv.2.trunc = trunc i64 %iv.2 to i3292 %iv.2.next = add i64 %iv.2, 193 %gep = getelementptr inbounds i64, ptr %p, i64 %iv.294 store i64 %iv.2, ptr %gep95 %add.2 = add i32 %add.lcssa, %iv.2.trunc96 %c.2 = icmp slt i32 %add.2, 10097 br i1 %c.2, label %loop.2, label %exit.298 99exit.2:100 ret void101}102 103;.104; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}105; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}106; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}107; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}108; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}109; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}110;.111