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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -S < %s | FileCheck %s --check-prefix=CHECK-VF4IC13; RUN: opt -passes=loop-vectorize -force-vector-interleave=4 -force-vector-width=4 -S < %s | FileCheck %s --check-prefix=CHECK-VF4IC44; RUN: opt -passes=loop-vectorize -force-vector-interleave=4 -force-vector-width=1 -S < %s | FileCheck %s --check-prefix=CHECK-VF1IC45 6; This should be an AnyOf reduction instead of FindLastIV reduction.7; The reason is the outer induction variable is invariant for inner loop.8define i64 @select_iv_def_from_outer_loop(ptr %a, i64 %start, i64 %n) {9; CHECK-VF4IC1-LABEL: define i64 @select_iv_def_from_outer_loop(10; CHECK-VF4IC1-SAME: ptr [[A:%.*]], i64 [[START:%.*]], i64 [[N:%.*]]) {11; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]:12; CHECK-VF4IC1-NEXT: br label %[[OUTER_LOOP:.*]]13; CHECK-VF4IC1: [[OUTER_LOOP]]:14; CHECK-VF4IC1-NEXT: [[RDX_OUTER:%.*]] = phi i64 [ [[START]], %[[ENTRY]] ], [ [[SELECT_LCSSA:%.*]], %[[OUTER_LOOP_EXIT:.*]] ]15; CHECK-VF4IC1-NEXT: [[IV_OUTER:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_OUTER_NEXT:%.*]], %[[OUTER_LOOP_EXIT]] ]16; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[IV_OUTER]]17; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 818; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 419; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]20; CHECK-VF4IC1: [[VECTOR_PH]]:21; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 422; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]23; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]]24; CHECK-VF4IC1: [[VECTOR_BODY]]:25; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]26; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]27; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[INDEX]]28; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP2]], align 829; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 3)30; CHECK-VF4IC1-NEXT: [[TMP5]] = or <4 x i1> [[VEC_PHI]], [[TMP4]]31; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 432; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]33; CHECK-VF4IC1-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]34; CHECK-VF4IC1: [[MIDDLE_BLOCK]]:35; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP5]])36; CHECK-VF4IC1-NEXT: [[TMP8:%.*]] = freeze i1 [[TMP7]]37; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[TMP8]], i64 [[IV_OUTER]], i64 [[RDX_OUTER]]38; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]39; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[OUTER_LOOP_EXIT]], label %[[SCALAR_PH]]40; CHECK-VF4IC1: [[SCALAR_PH]]:41; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_OUTER]], %[[OUTER_LOOP]] ]42; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[OUTER_LOOP]] ]43; CHECK-VF4IC1-NEXT: br label %[[INNER_LOOP:.*]]44; CHECK-VF4IC1: [[INNER_LOOP]]:45; CHECK-VF4IC1-NEXT: [[RDX_INNER:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SELECT:%.*]], %[[INNER_LOOP]] ]46; CHECK-VF4IC1-NEXT: [[IV_INNER:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_INNER_NEXT:%.*]], %[[INNER_LOOP]] ]47; CHECK-VF4IC1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[IV_INNER]]48; CHECK-VF4IC1-NEXT: [[TMP9:%.*]] = load i64, ptr [[ARRAYIDX2]], align 849; CHECK-VF4IC1-NEXT: [[CMP:%.*]] = icmp eq i64 [[TMP9]], 350; CHECK-VF4IC1-NEXT: [[SELECT]] = select i1 [[CMP]], i64 [[IV_OUTER]], i64 [[RDX_INNER]]51; CHECK-VF4IC1-NEXT: [[IV_INNER_NEXT]] = add nuw nsw i64 [[IV_INNER]], 152; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT_INNER:%.*]] = icmp eq i64 [[IV_INNER_NEXT]], [[N]]53; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT_INNER]], label %[[OUTER_LOOP_EXIT]], label %[[INNER_LOOP]], !llvm.loop [[LOOP3:![0-9]+]]54; CHECK-VF4IC1: [[OUTER_LOOP_EXIT]]:55; CHECK-VF4IC1-NEXT: [[SELECT_LCSSA]] = phi i64 [ [[SELECT]], %[[INNER_LOOP]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ]56; CHECK-VF4IC1-NEXT: [[IV_OUTER_NEXT]] = add nuw nsw i64 [[IV_OUTER]], 157; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_OUTER_NEXT]], [[N]]58; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[OUTER_LOOP]]59; CHECK-VF4IC1: [[EXIT]]:60; CHECK-VF4IC1-NEXT: [[SELECT_LCSSA_LCSSA:%.*]] = phi i64 [ [[SELECT_LCSSA]], %[[OUTER_LOOP_EXIT]] ]61; CHECK-VF4IC1-NEXT: ret i64 [[SELECT_LCSSA_LCSSA]]62;63; CHECK-VF4IC4-LABEL: define i64 @select_iv_def_from_outer_loop(64; CHECK-VF4IC4-SAME: ptr [[A:%.*]], i64 [[START:%.*]], i64 [[N:%.*]]) {65; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]:66; CHECK-VF4IC4-NEXT: br label %[[OUTER_LOOP:.*]]67; CHECK-VF4IC4: [[OUTER_LOOP]]:68; CHECK-VF4IC4-NEXT: [[RDX_OUTER:%.*]] = phi i64 [ [[START]], %[[ENTRY]] ], [ [[SELECT_LCSSA:%.*]], %[[OUTER_LOOP_EXIT:.*]] ]69; CHECK-VF4IC4-NEXT: [[IV_OUTER:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_OUTER_NEXT:%.*]], %[[OUTER_LOOP_EXIT]] ]70; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[IV_OUTER]]71; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 872; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 1673; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]74; CHECK-VF4IC4: [[VECTOR_PH]]:75; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 1676; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]77; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]]78; CHECK-VF4IC4: [[VECTOR_BODY]]:79; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]80; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]81; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ]82; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]83; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ]84; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[TMP1]]85; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i64 486; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i64 887; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i64 1288; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP2]], align 889; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP4]], align 890; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i64>, ptr [[TMP5]], align 891; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i64>, ptr [[TMP6]], align 892; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 3)93; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 3)94; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD5]], splat (i64 3)95; CHECK-VF4IC4-NEXT: [[TMP10:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD6]], splat (i64 3)96; CHECK-VF4IC4-NEXT: [[TMP11]] = or <4 x i1> [[VEC_PHI]], [[TMP7]]97; CHECK-VF4IC4-NEXT: [[TMP12]] = or <4 x i1> [[VEC_PHI1]], [[TMP8]]98; CHECK-VF4IC4-NEXT: [[TMP13]] = or <4 x i1> [[VEC_PHI2]], [[TMP9]]99; CHECK-VF4IC4-NEXT: [[TMP14]] = or <4 x i1> [[VEC_PHI3]], [[TMP10]]100; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP1]], 16101; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]102; CHECK-VF4IC4-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]103; CHECK-VF4IC4: [[MIDDLE_BLOCK]]:104; CHECK-VF4IC4-NEXT: [[BIN_RDX:%.*]] = or <4 x i1> [[TMP12]], [[TMP11]]105; CHECK-VF4IC4-NEXT: [[BIN_RDX7:%.*]] = or <4 x i1> [[TMP13]], [[BIN_RDX]]106; CHECK-VF4IC4-NEXT: [[BIN_RDX8:%.*]] = or <4 x i1> [[TMP14]], [[BIN_RDX7]]107; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[BIN_RDX8]])108; CHECK-VF4IC4-NEXT: [[TMP17:%.*]] = freeze i1 [[TMP16]]109; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[TMP17]], i64 [[IV_OUTER]], i64 [[RDX_OUTER]]110; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]111; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[OUTER_LOOP_EXIT]], label %[[SCALAR_PH]]112; CHECK-VF4IC4: [[SCALAR_PH]]:113; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_OUTER]], %[[OUTER_LOOP]] ]114; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[OUTER_LOOP]] ]115; CHECK-VF4IC4-NEXT: br label %[[INNER_LOOP:.*]]116; CHECK-VF4IC4: [[INNER_LOOP]]:117; CHECK-VF4IC4-NEXT: [[RDX_INNER:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SELECT:%.*]], %[[INNER_LOOP]] ]118; CHECK-VF4IC4-NEXT: [[IV_INNER:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_INNER_NEXT:%.*]], %[[INNER_LOOP]] ]119; CHECK-VF4IC4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[IV_INNER]]120; CHECK-VF4IC4-NEXT: [[TMP18:%.*]] = load i64, ptr [[ARRAYIDX2]], align 8121; CHECK-VF4IC4-NEXT: [[CMP:%.*]] = icmp eq i64 [[TMP18]], 3122; CHECK-VF4IC4-NEXT: [[SELECT]] = select i1 [[CMP]], i64 [[IV_OUTER]], i64 [[RDX_INNER]]123; CHECK-VF4IC4-NEXT: [[IV_INNER_NEXT]] = add nuw nsw i64 [[IV_INNER]], 1124; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT_INNER:%.*]] = icmp eq i64 [[IV_INNER_NEXT]], [[N]]125; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT_INNER]], label %[[OUTER_LOOP_EXIT]], label %[[INNER_LOOP]], !llvm.loop [[LOOP3:![0-9]+]]126; CHECK-VF4IC4: [[OUTER_LOOP_EXIT]]:127; CHECK-VF4IC4-NEXT: [[SELECT_LCSSA]] = phi i64 [ [[SELECT]], %[[INNER_LOOP]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ]128; CHECK-VF4IC4-NEXT: [[IV_OUTER_NEXT]] = add nuw nsw i64 [[IV_OUTER]], 1129; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_OUTER_NEXT]], [[N]]130; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[OUTER_LOOP]]131; CHECK-VF4IC4: [[EXIT]]:132; CHECK-VF4IC4-NEXT: [[SELECT_LCSSA_LCSSA:%.*]] = phi i64 [ [[SELECT_LCSSA]], %[[OUTER_LOOP_EXIT]] ]133; CHECK-VF4IC4-NEXT: ret i64 [[SELECT_LCSSA_LCSSA]]134;135; CHECK-VF1IC4-LABEL: define i64 @select_iv_def_from_outer_loop(136; CHECK-VF1IC4-SAME: ptr [[A:%.*]], i64 [[START:%.*]], i64 [[N:%.*]]) {137; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]:138; CHECK-VF1IC4-NEXT: br label %[[OUTER_LOOP:.*]]139; CHECK-VF1IC4: [[OUTER_LOOP]]:140; CHECK-VF1IC4-NEXT: [[RDX_OUTER:%.*]] = phi i64 [ [[START]], %[[ENTRY]] ], [ [[SELECT_LCSSA:%.*]], %[[OUTER_LOOP_EXIT:.*]] ]141; CHECK-VF1IC4-NEXT: [[IV_OUTER:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_OUTER_NEXT:%.*]], %[[OUTER_LOOP_EXIT]] ]142; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[IV_OUTER]]143; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8144; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4145; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]146; CHECK-VF1IC4: [[VECTOR_PH]]:147; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4148; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]149; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]]150; CHECK-VF1IC4: [[VECTOR_BODY]]:151; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]152; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ]153; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ]154; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ]155; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ]156; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 1157; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 2158; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 3159; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[INDEX]]160; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[TMP2]]161; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[TMP3]]162; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[TMP4]]163; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP5]], align 8164; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP6]], align 8165; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP7]], align 8166; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP8]], align 8167; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = icmp eq i64 [[TMP9]], 3168; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP10]], 3169; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = icmp eq i64 [[TMP11]], 3170; CHECK-VF1IC4-NEXT: [[TMP16:%.*]] = icmp eq i64 [[TMP12]], 3171; CHECK-VF1IC4-NEXT: [[TMP17]] = or i1 [[VEC_PHI]], [[TMP13]]172; CHECK-VF1IC4-NEXT: [[TMP18]] = or i1 [[VEC_PHI1]], [[TMP14]]173; CHECK-VF1IC4-NEXT: [[TMP19]] = or i1 [[VEC_PHI2]], [[TMP15]]174; CHECK-VF1IC4-NEXT: [[TMP20]] = or i1 [[VEC_PHI3]], [[TMP16]]175; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4176; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]177; CHECK-VF1IC4-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]178; CHECK-VF1IC4: [[MIDDLE_BLOCK]]:179; CHECK-VF1IC4-NEXT: [[BIN_RDX:%.*]] = or i1 [[TMP18]], [[TMP17]]180; CHECK-VF1IC4-NEXT: [[BIN_RDX4:%.*]] = or i1 [[TMP19]], [[BIN_RDX]]181; CHECK-VF1IC4-NEXT: [[BIN_RDX5:%.*]] = or i1 [[TMP20]], [[BIN_RDX4]]182; CHECK-VF1IC4-NEXT: [[TMP22:%.*]] = freeze i1 [[BIN_RDX5]]183; CHECK-VF1IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[TMP22]], i64 [[IV_OUTER]], i64 [[RDX_OUTER]]184; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]185; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[OUTER_LOOP_EXIT]], label %[[SCALAR_PH]]186; CHECK-VF1IC4: [[SCALAR_PH]]:187; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_OUTER]], %[[OUTER_LOOP]] ]188; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[OUTER_LOOP]] ]189; CHECK-VF1IC4-NEXT: br label %[[INNER_LOOP:.*]]190; CHECK-VF1IC4: [[INNER_LOOP]]:191; CHECK-VF1IC4-NEXT: [[RDX_INNER:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SELECT:%.*]], %[[INNER_LOOP]] ]192; CHECK-VF1IC4-NEXT: [[IV_INNER:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_INNER_NEXT:%.*]], %[[INNER_LOOP]] ]193; CHECK-VF1IC4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[IV_INNER]]194; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = load i64, ptr [[ARRAYIDX2]], align 8195; CHECK-VF1IC4-NEXT: [[CMP:%.*]] = icmp eq i64 [[TMP23]], 3196; CHECK-VF1IC4-NEXT: [[SELECT]] = select i1 [[CMP]], i64 [[IV_OUTER]], i64 [[RDX_INNER]]197; CHECK-VF1IC4-NEXT: [[IV_INNER_NEXT]] = add nuw nsw i64 [[IV_INNER]], 1198; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT_INNER:%.*]] = icmp eq i64 [[IV_INNER_NEXT]], [[N]]199; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT_INNER]], label %[[OUTER_LOOP_EXIT]], label %[[INNER_LOOP]], !llvm.loop [[LOOP3:![0-9]+]]200; CHECK-VF1IC4: [[OUTER_LOOP_EXIT]]:201; CHECK-VF1IC4-NEXT: [[SELECT_LCSSA]] = phi i64 [ [[SELECT]], %[[INNER_LOOP]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ]202; CHECK-VF1IC4-NEXT: [[IV_OUTER_NEXT]] = add nuw nsw i64 [[IV_OUTER]], 1203; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_OUTER_NEXT]], [[N]]204; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[OUTER_LOOP]]205; CHECK-VF1IC4: [[EXIT]]:206; CHECK-VF1IC4-NEXT: [[SELECT_LCSSA_LCSSA:%.*]] = phi i64 [ [[SELECT_LCSSA]], %[[OUTER_LOOP_EXIT]] ]207; CHECK-VF1IC4-NEXT: ret i64 [[SELECT_LCSSA_LCSSA]]208;209entry:210 br label %outer.loop211 212outer.loop:213 %rdx.outer = phi i64 [ %start, %entry ], [ %select, %outer.loop.exit ]214 %iv.outer = phi i64 [ 0, %entry ], [ %iv.outer.next, %outer.loop.exit ]215 %arrayidx = getelementptr inbounds ptr, ptr %a, i64 %iv.outer216 %0 = load ptr, ptr %arrayidx, align 8217 br label %inner.loop218 219inner.loop:220 %rdx.inner = phi i64 [ %rdx.outer, %outer.loop ], [ %select, %inner.loop ]221 %iv.inner = phi i64 [ 0, %outer.loop ], [ %iv.inner.next, %inner.loop ]222 %arrayidx2 = getelementptr inbounds i64, ptr %0, i64 %iv.inner223 %1 = load i64, ptr %arrayidx2, align 8224 %cmp = icmp eq i64 %1, 3225 %select = select i1 %cmp, i64 %iv.outer, i64 %rdx.inner226 %iv.inner.next = add nuw nsw i64 %iv.inner, 1227 %exitcond.not.inner = icmp eq i64 %iv.inner.next, %n228 br i1 %exitcond.not.inner, label %outer.loop.exit, label %inner.loop229 230outer.loop.exit:231 %iv.outer.next = add nuw nsw i64 %iv.outer, 1232 %exitcond.not = icmp eq i64 %iv.outer.next, %n233 br i1 %exitcond.not, label %exit, label %outer.loop234 235exit:236 ret i64 %select237}238;.239; CHECK-VF4IC1: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}240; CHECK-VF4IC1: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}241; CHECK-VF4IC1: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}242; CHECK-VF4IC1: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}243;.244; CHECK-VF4IC4: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}245; CHECK-VF4IC4: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}246; CHECK-VF4IC4: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}247; CHECK-VF4IC4: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}248;.249; CHECK-VF1IC4: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}250; CHECK-VF1IC4: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}251; CHECK-VF1IC4: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}252; CHECK-VF1IC4: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}253;.254