405 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=2 -scev-verify-ir -S %s | FileCheck %s3 4; Make sure SCEV is not queried while the IR is temporarily invalid.5 6define void @pr49538() {7; CHECK-LABEL: define void @pr49538() {8; CHECK-NEXT: [[ENTRY:.*]]:9; CHECK-NEXT: br label %[[LOOP_0:.*]]10; CHECK: [[LOOP_0]]:11; CHECK-NEXT: [[IV_0:%.*]] = phi i16 [ -1, %[[ENTRY]] ], [ [[IV_0_NEXT:%.*]], %[[LOOP_0_LATCH:.*]] ]12; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[IV_0]] to i3213; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[TMP0]], 114; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 415; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]16; CHECK: [[VECTOR_PH]]:17; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 418; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]]19; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i32 [[N_VEC]] to i1620; CHECK-NEXT: [[TMP2:%.*]] = add i16 -1, [[DOTCAST]]21; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]22; CHECK: [[VECTOR_BODY]]:23; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]24; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 425; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]26; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]27; CHECK: [[MIDDLE_BLOCK]]:28; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]]29; CHECK-NEXT: br i1 [[CMP_N]], label %[[LOOP_0_LATCH]], label %[[SCALAR_PH]]30; CHECK: [[SCALAR_PH]]:31; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ -1, %[[LOOP_0]] ]32; CHECK-NEXT: br label %[[LOOP_1:.*]]33; CHECK: [[LOOP_1]]:34; CHECK-NEXT: [[IV_1:%.*]] = phi i16 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP_1]] ]35; CHECK-NEXT: [[IV_1_NEXT]] = add nsw i16 [[IV_1]], 136; CHECK-NEXT: [[I6:%.*]] = icmp eq i16 [[IV_1_NEXT]], [[IV_0]]37; CHECK-NEXT: br i1 [[I6]], label %[[LOOP_0_LATCH]], label %[[LOOP_1]], !llvm.loop [[LOOP3:![0-9]+]]38; CHECK: [[LOOP_0_LATCH]]:39; CHECK-NEXT: [[I8:%.*]] = phi i16 [ 1, %[[LOOP_1]] ], [ 1, %[[MIDDLE_BLOCK]] ]40; CHECK-NEXT: [[IV_0_NEXT]] = add nsw i16 [[IV_0]], 141; CHECK-NEXT: [[EC_0:%.*]] = icmp eq i16 [[IV_0_NEXT]], [[I8]]42; CHECK-NEXT: br i1 [[EC_0]], label %[[EXIT:.*]], label %[[LOOP_0]]43; CHECK: [[EXIT]]:44; CHECK-NEXT: ret void45;46entry:47 br label %loop.048 49loop.0:50 %iv.0 = phi i16 [ -1, %entry ], [ %iv.0.next, %loop.0.latch ]51 br label %loop.152 53loop.1:54 %iv.1 = phi i16 [ -1, %loop.0 ], [ %iv.1.next, %loop.1 ]55 %iv.1.next = add nsw i16 %iv.1, 156 %i6 = icmp eq i16 %iv.1.next, %iv.057 br i1 %i6, label %loop.0.latch, label %loop.158 59loop.0.latch:60 %i8 = phi i16 [ 1, %loop.1 ]61 %iv.0.next = add nsw i16 %iv.0, 162 %ec.0 = icmp eq i16 %iv.0.next, %i863 br i1 %ec.0, label %exit, label %loop.064 65exit:66 ret void67}68 69define void @pr49900(i32 %x, ptr %ptr) {70; CHECK-LABEL: define void @pr49900(71; CHECK-SAME: i32 [[X:%.*]], ptr [[PTR:%.*]]) {72; CHECK-NEXT: [[ENTRY:.*:]]73; CHECK-NEXT: br label %[[LOOP_0:.*]]74; CHECK: [[LOOP_0]]:75; CHECK-NEXT: [[EC_0:%.*]] = icmp slt i32 [[X]], 076; CHECK-NEXT: br i1 [[EC_0]], label %[[LOOP_0]], label %[[LOOP_1_PH:.*]]77; CHECK: [[LOOP_1_PH]]:78; CHECK-NEXT: br label %[[LOOP_1:.*]]79; CHECK: [[LOOP_1]]:80; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ 0, %[[LOOP_1_PH]] ], [ [[IV_3_NEXT_LCSSA:%.*]], %[[LOOP_1_LATCH:.*]] ]81; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[IV_1]], 1282; CHECK-NEXT: [[SMAX2:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP0]], i32 65537)83; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[SMAX2]], -1284; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], [[IV_1]]85; CHECK-NEXT: [[UMIN3:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP2]], i32 1)86; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[UMIN3]], 187; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[UMIN3]]88; CHECK-NEXT: [[TMP5:%.*]] = udiv i32 [[TMP4]], 1389; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP3]], [[TMP5]]90; CHECK-NEXT: [[MIN_ITERS_CHECK5:%.*]] = icmp ult i32 [[TMP6]], 491; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK5]], label %[[SCALAR_PH4:.*]], label %[[VECTOR_PH6:.*]]92; CHECK: [[VECTOR_PH6]]:93; CHECK-NEXT: [[N_MOD_VF7:%.*]] = urem i32 [[TMP6]], 494; CHECK-NEXT: [[N_VEC8:%.*]] = sub i32 [[TMP6]], [[N_MOD_VF7]]95; CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[N_VEC8]], 1396; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[IV_1]], [[TMP7]]97; CHECK-NEXT: br label %[[VECTOR_BODY9:.*]]98; CHECK: [[VECTOR_BODY9]]:99; CHECK-NEXT: [[INDEX10:%.*]] = phi i32 [ 0, %[[VECTOR_PH6]] ], [ [[INDEX_NEXT11:%.*]], %[[VECTOR_BODY9]] ]100; CHECK-NEXT: [[INDEX_NEXT11]] = add nuw i32 [[INDEX10]], 4101; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[INDEX_NEXT11]], [[N_VEC8]]102; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK12:.*]], label %[[VECTOR_BODY9]], !llvm.loop [[LOOP4:![0-9]+]]103; CHECK: [[MIDDLE_BLOCK12]]:104; CHECK-NEXT: [[CMP_N13:%.*]] = icmp eq i32 [[TMP6]], [[N_VEC8]]105; CHECK-NEXT: br i1 [[CMP_N13]], label %[[LOOP_3_PH:.*]], label %[[SCALAR_PH4]]106; CHECK: [[SCALAR_PH4]]:107; CHECK-NEXT: [[BC_RESUME_VAL14:%.*]] = phi i32 [ [[TMP8]], %[[MIDDLE_BLOCK12]] ], [ [[IV_1]], %[[LOOP_1]] ]108; CHECK-NEXT: br label %[[LOOP_2:.*]]109; CHECK: [[LOOP_2]]:110; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL14]], %[[SCALAR_PH4]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP_2]] ]111; CHECK-NEXT: [[TMP54:%.*]] = add i32 [[IV_2]], 12112; CHECK-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 13113; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[IV_2_NEXT]] to i64114; CHECK-NEXT: [[TMP56:%.*]] = add nuw nsw i64 [[EXT]], 1115; CHECK-NEXT: [[C6:%.*]] = icmp sle i32 [[TMP54]], 65536116; CHECK-NEXT: br i1 [[C6]], label %[[LOOP_2]], label %[[LOOP_3_PH]], !llvm.loop [[LOOP5:![0-9]+]]117; CHECK: [[LOOP_3_PH]]:118; CHECK-NEXT: [[IV_2_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_2_NEXT]], %[[LOOP_2]] ], [ [[TMP8]], %[[MIDDLE_BLOCK12]] ]119; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[IV_1]], 26120; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[IV_1]], 12121; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP11]], i32 65537)122; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[SMAX]], -12123; CHECK-NEXT: [[TMP13:%.*]] = sub i32 [[TMP12]], [[IV_1]]124; CHECK-NEXT: [[UMIN:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP13]], i32 1)125; CHECK-NEXT: [[TMP14:%.*]] = sub i32 [[TMP13]], [[UMIN]]126; CHECK-NEXT: [[TMP15:%.*]] = udiv i32 [[TMP14]], 13127; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[UMIN]], [[TMP15]]128; CHECK-NEXT: [[TMP17:%.*]] = mul i32 [[TMP16]], 13129; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP10]], [[TMP17]]130; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP18]], i32 65536)131; CHECK-NEXT: [[TMP19:%.*]] = add i32 [[UMAX]], -26132; CHECK-NEXT: [[TMP20:%.*]] = sub i32 [[TMP19]], [[IV_1]]133; CHECK-NEXT: [[TMP21:%.*]] = sub i32 [[TMP20]], [[TMP17]]134; CHECK-NEXT: [[UMIN1:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP21]], i32 1)135; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[UMIN1]], 1136; CHECK-NEXT: [[TMP23:%.*]] = sub i32 [[TMP20]], [[UMIN1]]137; CHECK-NEXT: [[TMP24:%.*]] = sub i32 [[TMP23]], [[TMP17]]138; CHECK-NEXT: [[TMP25:%.*]] = udiv i32 [[TMP24]], 13139; CHECK-NEXT: [[TMP26:%.*]] = add i32 [[TMP22]], [[TMP25]]140; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP26]], 4141; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]142; CHECK: [[VECTOR_PH]]:143; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP26]], 4144; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP26]], [[N_MOD_VF]]145; CHECK-NEXT: [[TMP27:%.*]] = mul i32 [[N_VEC]], 13146; CHECK-NEXT: [[TMP28:%.*]] = add i32 [[IV_2_NEXT_LCSSA]], [[TMP27]]147; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]148; CHECK: [[VECTOR_BODY]]:149; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]150; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4151; CHECK-NEXT: [[TMP29:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]152; CHECK-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]153; CHECK: [[MIDDLE_BLOCK]]:154; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP26]], [[N_VEC]]155; CHECK-NEXT: br i1 [[CMP_N]], label %[[LOOP_1_LATCH]], label %[[SCALAR_PH]]156; CHECK: [[SCALAR_PH]]:157; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP28]], %[[MIDDLE_BLOCK]] ], [ [[IV_2_NEXT_LCSSA]], %[[LOOP_3_PH]] ]158; CHECK-NEXT: br label %[[LOOP_3:.*]]159; CHECK: [[LOOP_3]]:160; CHECK-NEXT: [[IV_3:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_3_NEXT:%.*]], %[[LOOP_3]] ]161; CHECK-NEXT: [[IV_3_NEXT]] = add i32 [[IV_3]], 13162; CHECK-NEXT: [[C1:%.*]] = icmp ult i32 [[IV_3_NEXT]], 65536163; CHECK-NEXT: br i1 [[C1]], label %[[LOOP_3]], label %[[LOOP_1_LATCH]], !llvm.loop [[LOOP7:![0-9]+]]164; CHECK: [[LOOP_1_LATCH]]:165; CHECK-NEXT: [[IV_3_NEXT_LCSSA]] = phi i32 [ [[IV_3_NEXT]], %[[LOOP_3]] ], [ [[TMP28]], %[[MIDDLE_BLOCK]] ]166; CHECK-NEXT: [[EC:%.*]] = icmp ne i32 [[IV_1]], 9999167; CHECK-NEXT: br i1 [[EC]], label %[[LOOP_1]], label %[[EXIT:.*]]168; CHECK: [[EXIT]]:169; CHECK-NEXT: ret void170;171entry:172 br label %loop.0173 174loop.0: ; preds = %bb2, %bb175 %ec.0 = icmp slt i32 %x, 0176 br i1 %ec.0, label %loop.0, label %loop.1.ph177 178loop.1.ph: ; preds = %bb2179 br label %loop.1180 181loop.1: ; preds = %bb33, %bb5182 %iv.1 = phi i32 [ 0, %loop.1.ph ], [ %iv.3.next, %loop.1.latch ]183 br label %loop.2184 185loop.2:186 %iv.2 = phi i32 [ %iv.1, %loop.1 ], [ %iv.2.next, %loop.2 ]187 %tmp54 = add i32 %iv.2, 12188 %iv.2.next = add i32 %iv.2, 13189 %ext = zext i32 %iv.2.next to i64190 %tmp56 = add nuw nsw i64 %ext, 1191 %C6 = icmp sle i32 %tmp54, 65536192 br i1 %C6, label %loop.2, label %loop.3.ph193 194loop.3.ph:195 br label %loop.3196 197loop.3:198 %iv.3 = phi i32 [ %iv.2.next, %loop.3.ph ], [ %iv.3.next, %loop.3 ]199 %iv.3.next = add i32 %iv.3 , 13200 %C1 = icmp ult i32 %iv.3.next, 65536201 br i1 %C1, label %loop.3, label %loop.1.latch202 203loop.1.latch:204 %ec = icmp ne i32 %iv.1, 9999205 br i1 %ec, label %loop.1, label %exit206 207exit:208 ret void209}210 211define void @pr52024(ptr %dst, i16 %N) {212; CHECK-LABEL: define void @pr52024(213; CHECK-SAME: ptr [[DST:%.*]], i16 [[N:%.*]]) {214; CHECK-NEXT: [[ENTRY:.*]]:215; CHECK-NEXT: br label %[[LOOP_1:.*]]216; CHECK: [[LOOP_1]]:217; CHECK-NEXT: [[IV_1:%.*]] = phi i16 [ 1, %[[ENTRY]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP_1_LATCH:.*]] ]218; CHECK-NEXT: [[IV_1_NEXT]] = mul i16 [[IV_1]], 3219; CHECK-NEXT: [[EXITCOND_1:%.*]] = icmp uge i16 [[IV_1_NEXT]], 99220; CHECK-NEXT: br i1 [[EXITCOND_1]], label %[[LOOP_1_LATCH]], label %[[EXIT_LOOPEXIT1:.*]]221; CHECK: [[LOOP_1_LATCH]]:222; CHECK-NEXT: [[EXITCOND_2:%.*]] = icmp eq i16 [[IV_1_NEXT]], [[N]]223; CHECK-NEXT: br i1 [[EXITCOND_2]], label %[[LOOP_2_PH:.*]], label %[[LOOP_1]]224; CHECK: [[LOOP_2_PH]]:225; CHECK-NEXT: [[IV_1_NEXT_LCSSA:%.*]] = phi i16 [ [[IV_1_NEXT]], %[[LOOP_1_LATCH]] ]226; CHECK-NEXT: [[IV_1_NEXT_EXT:%.*]] = sext i16 [[IV_1_NEXT_LCSSA]] to i64227; CHECK-NEXT: [[TMP0:%.*]] = mul i16 [[IV_1]], 3228; CHECK-NEXT: br label %[[LOOP_2_HEADER:.*]]229; CHECK: [[LOOP_2_HEADER]]:230; CHECK-NEXT: [[IV_1_REM:%.*]] = urem i64 100, [[IV_1_NEXT_EXT]]231; CHECK-NEXT: [[REM_TRUNC:%.*]] = trunc i64 [[IV_1_REM]] to i16232; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 100, [[IV_1_NEXT_EXT]]233; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i16234; CHECK-NEXT: [[TMP3:%.*]] = mul i16 [[TMP0]], [[TMP2]]235; CHECK-NEXT: [[TMP4:%.*]] = add i16 [[TMP3]], -100236; CHECK-NEXT: br label %[[VECTOR_PH:.*]]237; CHECK: [[VECTOR_PH]]:238; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[TMP4]], i64 0239; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT]], <2 x i16> poison, <2 x i32> zeroinitializer240; CHECK-NEXT: [[TMP5:%.*]] = mul i16 24, [[TMP4]]241; CHECK-NEXT: [[TMP6:%.*]] = mul <2 x i16> splat (i16 2), [[BROADCAST_SPLAT]]242; CHECK-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement <2 x i16> poison, i16 [[REM_TRUNC]], i64 0243; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT5]], <2 x i16> poison, <2 x i32> zeroinitializer244; CHECK-NEXT: [[TMP7:%.*]] = mul <2 x i16> <i16 0, i16 1>, [[BROADCAST_SPLAT]]245; CHECK-NEXT: [[INDUCTION:%.*]] = add <2 x i16> zeroinitializer, [[TMP7]]246; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]247; CHECK: [[VECTOR_BODY]]:248; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]249; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i16> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]250; CHECK-NEXT: [[STEP_ADD:%.*]] = add <2 x i16> [[VEC_IND]], [[TMP6]]251; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i32 8, [[INDEX]]252; CHECK-NEXT: [[TMP8:%.*]] = sub <2 x i16> [[VEC_IND]], [[BROADCAST_SPLAT6]]253; CHECK-NEXT: [[TMP9:%.*]] = sub <2 x i16> [[STEP_ADD]], [[BROADCAST_SPLAT6]]254; CHECK-NEXT: [[TMP10:%.*]] = zext <2 x i16> [[TMP8]] to <2 x i32>255; CHECK-NEXT: [[TMP11:%.*]] = zext <2 x i16> [[TMP9]] to <2 x i32>256; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[DST]], i32 [[OFFSET_IDX]]257; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP12]], i64 2258; CHECK-NEXT: store <2 x i32> [[TMP10]], ptr [[TMP12]], align 4259; CHECK-NEXT: store <2 x i32> [[TMP11]], ptr [[TMP13]], align 4260; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4261; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i16> [[STEP_ADD]], [[TMP6]]262; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT]], 24263; CHECK-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]264; CHECK: [[MIDDLE_BLOCK]]:265; CHECK-NEXT: br label %[[SCALAR_PH:.*]]266; CHECK: [[SCALAR_PH]]:267; CHECK-NEXT: br label %[[LOOP_3:.*]]268; CHECK: [[LOOP_3]]:269; CHECK-NEXT: [[IV_3:%.*]] = phi i32 [ 32, %[[SCALAR_PH]] ], [ [[IV_3_NEXT:%.*]], %[[LOOP_3]] ]270; CHECK-NEXT: [[SUB_PHI:%.*]] = phi i16 [ [[TMP5]], %[[SCALAR_PH]] ], [ [[SUB:%.*]], %[[LOOP_3]] ]271; CHECK-NEXT: [[SUB]] = sub i16 [[SUB_PHI]], [[REM_TRUNC]]272; CHECK-NEXT: [[SUB_EXT:%.*]] = zext i16 [[SUB]] to i32273; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i32, ptr [[DST]], i32 [[IV_3]]274; CHECK-NEXT: store i32 [[SUB_EXT]], ptr [[GEP_DST]], align 4275; CHECK-NEXT: [[IV_3_NEXT]] = add nuw nsw i32 [[IV_3]], 1276; CHECK-NEXT: [[EXITCOND_3:%.*]] = icmp eq i32 [[IV_3_NEXT]], 34277; CHECK-NEXT: br i1 [[EXITCOND_3]], label %[[LOOP_2_LATCH:.*]], label %[[LOOP_3]], !llvm.loop [[LOOP9:![0-9]+]]278; CHECK: [[LOOP_2_LATCH]]:279; CHECK-NEXT: [[SUB_LCSSA:%.*]] = phi i16 [ [[SUB]], %[[LOOP_3]] ]280; CHECK-NEXT: [[EXITCOND:%.*]] = icmp uge i16 [[SUB_LCSSA]], 200281; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT_LOOPEXIT:.*]], label %[[LOOP_2_HEADER]]282; CHECK: [[EXIT_LOOPEXIT]]:283; CHECK-NEXT: br label %[[EXIT:.*]]284; CHECK: [[EXIT_LOOPEXIT1]]:285; CHECK-NEXT: br label %[[EXIT]]286; CHECK: [[EXIT]]:287; CHECK-NEXT: ret void288;289entry:290 br label %loop.1291 292loop.1:293 %iv.1 = phi i16 [ 1, %entry ], [ %iv.1.next, %loop.1.latch ]294 %iv.1.next = mul i16 %iv.1, 3295 %exitcond.1 = icmp uge i16 %iv.1.next, 99296 br i1 %exitcond.1, label %loop.1.latch, label %exit297 298loop.1.latch:299 %exitcond.2 = icmp eq i16 %iv.1.next, %N300 br i1 %exitcond.2, label %loop.2.ph, label %loop.1301 302loop.2.ph:303 %iv.1.next.lcssa = phi i16 [ %iv.1.next, %loop.1.latch ]304 %iv.1.next.ext = sext i16 %iv.1.next.lcssa to i64305 br label %loop.2.header306 307loop.2.header:308 %iv.1.rem = urem i64 100, %iv.1.next.ext309 %rem.trunc = trunc i64 %iv.1.rem to i16310 br label %loop.3311 312loop.3:313 %iv.3 = phi i32 [ 8, %loop.2.header ], [ %iv.3.next, %loop.3 ]314 %sub.phi = phi i16 [ 0, %loop.2.header ], [ %sub, %loop.3 ]315 %sub = sub i16 %sub.phi, %rem.trunc316 %sub.ext = zext i16 %sub to i32317 %gep.dst = getelementptr i32, ptr %dst, i32 %iv.3318 store i32 %sub.ext, ptr %gep.dst319 %iv.3.next= add nuw nsw i32 %iv.3, 1320 %exitcond.3 = icmp eq i32 %iv.3.next, 34321 br i1 %exitcond.3, label %loop.2.latch, label %loop.3322 323loop.2.latch:324 %sub.lcssa = phi i16 [ %sub, %loop.3 ]325 %exitcond = icmp uge i16 %sub.lcssa, 200326 br i1 %exitcond, label %exit, label %loop.2.header327 328exit:329 ret void330}331 332define void @test_expand_secv_in_entry_before_gep(ptr %dst) {333; CHECK-LABEL: define void @test_expand_secv_in_entry_before_gep(334; CHECK-SAME: ptr [[DST:%.*]]) {335; CHECK-NEXT: [[ENTRY:.*]]:336; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]337; CHECK: [[OUTER_HEADER]]:338; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[OUTER_IV_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]339; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[OUTER_IV]], -1340; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 112341; CHECK-NEXT: [[GEP_M:%.*]] = getelementptr [36 x [36 x double]], ptr [[DST]], i64 0, i64 [[OUTER_IV]]342; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4343; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]344; CHECK: [[VECTOR_PH]]:345; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 4346; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]]347; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OUTER_IV]], [[N_VEC]]348; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]349; CHECK: [[VECTOR_BODY]]:350; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]351; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[OUTER_IV]], [[INDEX]]352; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, ptr [[GEP_M]], i64 [[OFFSET_IDX]]353; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 2354; CHECK-NEXT: store <2 x double> zeroinitializer, ptr [[TMP3]], align 8355; CHECK-NEXT: store <2 x double> zeroinitializer, ptr [[TMP4]], align 8356; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4357; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]358; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]359; CHECK: [[MIDDLE_BLOCK]]:360; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]]361; CHECK-NEXT: br i1 [[CMP_N]], label %[[OUTER_LATCH]], label %[[SCALAR_PH]]362; CHECK: [[SCALAR_PH]]:363; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[OUTER_IV]], %[[OUTER_HEADER]] ]364; CHECK-NEXT: br label %[[INNER:.*]]365; CHECK: [[INNER]]:366; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[INNER]] ]367; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds double, ptr [[GEP_M]], i64 [[IV]]368; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP]], align 8369; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1370; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 111371; CHECK-NEXT: br i1 [[EC]], label %[[OUTER_LATCH]], label %[[INNER]], !llvm.loop [[LOOP11:![0-9]+]]372; CHECK: [[OUTER_LATCH]]:373; CHECK-NEXT: [[OUTER_IV_NEXT]] = add i64 [[OUTER_IV]], 1374; CHECK-NEXT: [[C:%.*]] = call i1 @cond()375; CHECK-NEXT: br i1 [[C]], label %[[OUTER_HEADER]], label %[[EXIT:.*]]376; CHECK: [[EXIT]]:377; CHECK-NEXT: ret void378;379entry:380 br label %outer.header381 382outer.header:383 %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]384 %gep.m = getelementptr [36 x [36 x double]], ptr %dst, i64 0, i64 %outer.iv385 br label %inner386 387inner:388 %iv = phi i64 [ %outer.iv, %outer.header ], [ %iv.next, %inner ]389 %gep = getelementptr inbounds double, ptr %gep.m, i64 %iv390 store double 0.00, ptr %gep, align 8391 %iv.next = add i64 %iv, 1392 %ec = icmp eq i64 %iv, 111393 br i1 %ec, label %outer.latch, label %inner394 395outer.latch:396 %outer.iv.next = add i64 %outer.iv, 1397 %c = call i1 @cond()398 br i1 %c, label %outer.header, label %exit399 400exit:401 ret void402}403 404declare void @cond()405