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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt < %s -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S | FileCheck %s3 4 5; The vectorizer should refuse to fold the tail by masking because6; %conv is used outside of the loop. Test for this by checking that7; %n.vec, the vector trip count, is rounded down to the next multiple of8; 4. If folding the tail, it would have been rounded up instead.9; Test case for #76069(https://github.com/llvm/llvm-project/issues/76069).10define i32 @test(ptr %arr, i64 %n) {11; CHECK-LABEL: define i32 @test(12; CHECK-SAME: ptr [[ARR:%.*]], i64 [[N:%.*]]) {13; CHECK-NEXT: entry:14; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i64 [[N]], 115; CHECK-NEXT: br i1 [[CMP1]], label [[PREHEADER:%.*]], label [[DONE:%.*]]16; CHECK: preheader:17; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -118; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 419; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]20; CHECK: vector.scevcheck:21; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[N]], -222; CHECK-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP1]] to i823; CHECK-NEXT: [[TMP8:%.*]] = add i8 2, [[TMP7]]24; CHECK-NEXT: [[TMP9:%.*]] = icmp ult i8 [[TMP8]], 225; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[TMP1]], 25526; CHECK-NEXT: [[TMP12:%.*]] = or i1 [[TMP9]], [[TMP10]]27; CHECK-NEXT: br i1 [[TMP12]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]28; CHECK: vector.ph:29; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 430; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]31; CHECK-NEXT: [[IND_END:%.*]] = add i64 1, [[N_VEC]]32; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[N_VEC]] to i833; CHECK-NEXT: [[IND_END1:%.*]] = add i8 1, [[DOTCAST]]34; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]35; CHECK: vector.body:36; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]37; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]]38; CHECK-NEXT: [[TMP17:%.*]] = add nsw i64 [[OFFSET_IDX]], -139; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP17]]40; CHECK-NEXT: store <4 x i32> splat (i32 65), ptr [[TMP18]], align 441; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 442; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]43; CHECK-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]44; CHECK: middle.block:45; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]46; CHECK-NEXT: [[IND_ESCAPE:%.*]] = sub i64 [[IND_END]], 147; CHECK-NEXT: br i1 [[CMP_N]], label [[LOAD_VAL:%.*]], label [[SCALAR_PH]]48; CHECK: scalar.ph:49; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 1, [[PREHEADER]] ], [ 1, [[VECTOR_SCEVCHECK]] ]50; CHECK-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i8 [ [[IND_END1]], [[MIDDLE_BLOCK]] ], [ 1, [[PREHEADER]] ], [ 1, [[VECTOR_SCEVCHECK]] ]51; CHECK-NEXT: br label [[LOOP:%.*]]52; CHECK: loop:53; CHECK-NEXT: [[CONV:%.*]] = phi i64 [ [[CONV2:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]54; CHECK-NEXT: [[I:%.*]] = phi i8 [ [[INC:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ]55; CHECK-NEXT: [[SUB:%.*]] = add nsw i64 [[CONV]], -156; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[SUB]]57; CHECK-NEXT: store i32 65, ptr [[PTR]], align 458; CHECK-NEXT: [[INC]] = add i8 [[I]], 159; CHECK-NEXT: [[CONV2]] = zext i8 [[INC]] to i6460; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[CONV2]], [[N]]61; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP]], label [[LOAD_VAL]], !llvm.loop [[LOOP4:![0-9]+]]62; CHECK: load_val:63; CHECK-NEXT: [[FINAL:%.*]] = phi i64 [ [[CONV]], [[LOOP]] ], [ [[IND_ESCAPE]], [[MIDDLE_BLOCK]] ]64; CHECK-NEXT: [[PTR2:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[FINAL]]65; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[PTR2]], align 466; CHECK-NEXT: br label [[DONE]]67; CHECK: done:68; CHECK-NEXT: [[VALUE:%.*]] = phi i32 [ [[VAL]], [[LOAD_VAL]] ], [ 0, [[ENTRY:%.*]] ]69; CHECK-NEXT: ret i32 [[VALUE]]70;71entry:72 %cmp1 = icmp ugt i64 %n, 173 br i1 %cmp1, label %preheader, label %done74 75preheader:76 br label %loop77 78loop:79 %conv = phi i64 [ %conv2, %loop ], [ 1, %preheader ]80 %i = phi i8 [ %inc, %loop ], [ 1, %preheader ]81 %sub = add nsw i64 %conv, -182 %ptr = getelementptr inbounds i32, ptr %arr, i64 %sub83 store i32 65, ptr %ptr, align 484 %inc = add i8 %i, 185 %conv2 = zext i8 %inc to i6486 %cmp2 = icmp ult i64 %conv2, %n87 br i1 %cmp2, label %loop, label %load_val, !llvm.loop !088 89load_val:90 %final = phi i64 [ %conv, %loop ]91 %ptr2 = getelementptr inbounds i32, ptr %arr, i64 %final92 %val = load i32, ptr %ptr2, align 493 br label %done94 95done:96 %value = phi i32 [ %val, %load_val ], [ 0, %entry ]97 ret i32 %value98 99}100 101!0 = distinct !{!0, !1, !2, !3}102!1 = !{!"llvm.loop.unroll.disable"}103!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}104!3 = !{!"llvm.loop.vectorize.enable", i1 true}105;.106; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]], [[META3:![0-9]+]]}107; CHECK: [[META1]] = !{!"llvm.loop.unroll.disable"}108; CHECK: [[META2]] = !{!"llvm.loop.isvectorized", i32 1}109; CHECK: [[META3]] = !{!"llvm.loop.unroll.runtime.disable"}110; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}111;.112