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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -passes=loop-vectorize -enable-vplan-native-path -S %s | FileCheck %s3 4@A = common global [1024 x i64] zeroinitializer, align 165@B = common global [1024 x i64] zeroinitializer, align 166 7define void @inner_latch_header_first_successor(i64 %N, i32 %c, i64 %M) {8; CHECK-LABEL: define void @inner_latch_header_first_successor(9; CHECK-SAME: i64 [[N:%.*]], i32 [[C:%.*]], i64 [[M:%.*]]) {10; CHECK-NEXT: [[ENTRY:.*]]:11; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[M]], 412; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]13; CHECK: [[VECTOR_PH]]:14; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[M]], 415; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[M]], [[N_MOD_VF]]16; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[C]], i64 017; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer18; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> poison, i64 [[N]], i64 019; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> poison, <4 x i32> zeroinitializer20; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]21; CHECK: [[VECTOR_BODY]]:22; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_LATCH:.*]] ]23; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_LATCH]] ]24; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1024 x i64], ptr @A, i64 0, <4 x i64> [[VEC_IND]]25; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> align 4 [[TMP0]], <4 x i1> splat (i1 true), <4 x i64> poison)26; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> [[BROADCAST_SPLAT]], <4 x ptr> align 4 [[TMP0]], <4 x i1> splat (i1 true))27; CHECK-NEXT: br label %[[INNER3:.*]]28; CHECK: [[INNER3]]:29; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ zeroinitializer, %[[VECTOR_BODY]] ], [ [[TMP4:%.*]], %[[INNER3]] ]30; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i64> [ [[WIDE_MASKED_GATHER]], %[[VECTOR_BODY]] ], [ [[TMP3:%.*]], %[[INNER3]] ]31; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1024 x i64], ptr @B, i64 0, <4 x i64> [[VEC_PHI]]32; CHECK-NEXT: [[WIDE_MASKED_GATHER5:%.*]] = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> align 4 [[TMP1]], <4 x i1> splat (i1 true), <4 x i64> poison)33; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i64> [[WIDE_MASKED_GATHER5]], [[VEC_PHI4]]34; CHECK-NEXT: [[TMP3]] = add nsw <4 x i64> [[TMP2]], [[VEC_PHI4]]35; CHECK-NEXT: [[TMP4]] = add nuw nsw <4 x i64> [[VEC_PHI]], splat (i64 1)36; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <4 x i64> [[TMP4]], [[BROADCAST_SPLAT2]]37; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP6]], i32 038; CHECK-NEXT: br i1 [[TMP9]], label %[[VECTOR_LATCH]], label %[[INNER3]]39; CHECK: [[VECTOR_LATCH]]:40; CHECK-NEXT: [[TMP10:%.*]] = phi <4 x i64> [ [[TMP3]], %[[INNER3]] ]41; CHECK-NEXT: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> [[TMP10]], <4 x ptr> align 4 [[TMP0]], <4 x i1> splat (i1 true))42; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 443; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)44; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]45; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]46; CHECK: [[MIDDLE_BLOCK]]:47; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[M]], [[N_VEC]]48; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]49; CHECK: [[SCALAR_PH]]:50; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]51; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]52; CHECK: [[OUTER_HEADER]]:53; CHECK-NEXT: [[IV_OUTER:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_OUTER_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]54; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds [1024 x i64], ptr @A, i64 0, i64 [[IV_OUTER]]55; CHECK-NEXT: [[RED_START:%.*]] = load i64, ptr [[GEP_A]], align 456; CHECK-NEXT: store i32 [[C]], ptr [[GEP_A]], align 457; CHECK-NEXT: br label %[[INNER:.*]]58; CHECK: [[INNER]]:59; CHECK-NEXT: [[IV_INNER:%.*]] = phi i64 [ 0, %[[OUTER_HEADER]] ], [ [[IV_INNER_NEXT:%.*]], %[[INNER]] ]60; CHECK-NEXT: [[RED:%.*]] = phi i64 [ [[RED_START]], %[[OUTER_HEADER]] ], [ [[RED_NEXT:%.*]], %[[INNER]] ]61; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds [1024 x i64], ptr @B, i64 0, i64 [[IV_INNER]]62; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[GEP_B]], align 463; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[RED]]64; CHECK-NEXT: [[RED_NEXT]] = add nsw i64 [[ADD]], [[RED]]65; CHECK-NEXT: [[IV_INNER_NEXT]] = add nuw nsw i64 [[IV_INNER]], 166; CHECK-NEXT: [[INNER_EC:%.*]] = icmp ne i64 [[IV_INNER_NEXT]], [[N]]67; CHECK-NEXT: br i1 [[INNER_EC]], label %[[INNER]], label %[[OUTER_LATCH]]68; CHECK: [[OUTER_LATCH]]:69; CHECK-NEXT: [[RED_NEXT_LCSSA:%.*]] = phi i64 [ [[RED_NEXT]], %[[INNER]] ]70; CHECK-NEXT: store i64 [[RED_NEXT_LCSSA]], ptr [[GEP_A]], align 471; CHECK-NEXT: [[IV_OUTER_NEXT]] = add nuw nsw i64 [[IV_OUTER]], 172; CHECK-NEXT: [[OUTER_EC:%.*]] = icmp eq i64 [[IV_OUTER_NEXT]], [[M]]73; CHECK-NEXT: br i1 [[OUTER_EC]], label %[[EXIT]], label %[[OUTER_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]74; CHECK: [[EXIT]]:75; CHECK-NEXT: ret void76;77entry:78 br label %outer.header79 80outer.header:81 %iv.outer = phi i64 [ 0, %entry ], [ %iv.outer.next, %outer.latch ]82 %gep.A = getelementptr inbounds [1024 x i64], ptr @A, i64 0, i64 %iv.outer83 %red.start = load i64 , ptr %gep.A, align 484 store i32 %c, ptr %gep.A, align 485 br label %inner86 87inner:88 %iv.inner = phi i64 [ 0, %outer.header ], [ %iv.inner.next, %inner ]89 %red = phi i64 [ %red.start, %outer.header ], [ %red.next, %inner ]90 %gep.B = getelementptr inbounds [1024 x i64], ptr @B, i64 0, i64 %iv.inner91 %2 = load i64, ptr %gep.B, align 492 %add = add nsw i64 %2, %red93 %red.next = add nsw i64 %add, %red94 %iv.inner.next = add nuw nsw i64 %iv.inner, 195 %inner.ec = icmp ne i64 %iv.inner.next, %N96 br i1 %inner.ec, label %inner, label %outer.latch97 98outer.latch:99 store i64 %red.next, ptr %gep.A, align 4100 %iv.outer.next = add nuw nsw i64 %iv.outer, 1101 %outer.ec = icmp eq i64 %iv.outer.next, %M102 br i1 %outer.ec, label %exit, label %outer.header, !llvm.loop !1103 104exit:105 ret void106}107 108 109define void @inner_latch_header_second_successor(i64 %N, i32 %c, i64 %M) {110; CHECK-LABEL: define void @inner_latch_header_second_successor(111; CHECK-SAME: i64 [[N:%.*]], i32 [[C:%.*]], i64 [[M:%.*]]) {112; CHECK-NEXT: [[ENTRY:.*]]:113; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[M]], 4114; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]115; CHECK: [[VECTOR_PH]]:116; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[M]], 4117; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[M]], [[N_MOD_VF]]118; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[C]], i64 0119; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer120; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> poison, i64 [[N]], i64 0121; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> poison, <4 x i32> zeroinitializer122; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]123; CHECK: [[VECTOR_BODY]]:124; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_LATCH:.*]] ]125; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_LATCH]] ]126; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1024 x i64], ptr @A, i64 0, <4 x i64> [[VEC_IND]]127; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> align 4 [[TMP0]], <4 x i1> splat (i1 true), <4 x i64> poison)128; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> [[BROADCAST_SPLAT]], <4 x ptr> align 4 [[TMP0]], <4 x i1> splat (i1 true))129; CHECK-NEXT: br label %[[INNER3:.*]]130; CHECK: [[INNER3]]:131; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ zeroinitializer, %[[VECTOR_BODY]] ], [ [[TMP4:%.*]], %[[INNER3]] ]132; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i64> [ [[WIDE_MASKED_GATHER]], %[[VECTOR_BODY]] ], [ [[TMP3:%.*]], %[[INNER3]] ]133; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1024 x i64], ptr @B, i64 0, <4 x i64> [[VEC_PHI]]134; CHECK-NEXT: [[WIDE_MASKED_GATHER5:%.*]] = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> align 4 [[TMP1]], <4 x i1> splat (i1 true), <4 x i64> poison)135; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i64> [[WIDE_MASKED_GATHER5]], [[VEC_PHI4]]136; CHECK-NEXT: [[TMP3]] = add nsw <4 x i64> [[TMP2]], [[VEC_PHI4]]137; CHECK-NEXT: [[TMP4]] = add nuw nsw <4 x i64> [[VEC_PHI]], splat (i64 1)138; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <4 x i64> [[TMP4]], [[BROADCAST_SPLAT2]]139; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i1> [[TMP5]], i32 0140; CHECK-NEXT: br i1 [[TMP6]], label %[[VECTOR_LATCH]], label %[[INNER3]]141; CHECK: [[VECTOR_LATCH]]:142; CHECK-NEXT: [[TMP9:%.*]] = phi <4 x i64> [ [[TMP3]], %[[INNER3]] ]143; CHECK-NEXT: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> [[TMP9]], <4 x ptr> align 4 [[TMP0]], <4 x i1> splat (i1 true))144; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4145; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)146; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]147; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]148; CHECK: [[MIDDLE_BLOCK]]:149; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[M]], [[N_VEC]]150; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]151; CHECK: [[SCALAR_PH]]:152; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]153; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]154; CHECK: [[OUTER_HEADER]]:155; CHECK-NEXT: [[IV_OUTER:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_OUTER_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]156; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds [1024 x i64], ptr @A, i64 0, i64 [[IV_OUTER]]157; CHECK-NEXT: [[RED_START:%.*]] = load i64, ptr [[GEP_A]], align 4158; CHECK-NEXT: store i32 [[C]], ptr [[GEP_A]], align 4159; CHECK-NEXT: br label %[[INNER:.*]]160; CHECK: [[INNER]]:161; CHECK-NEXT: [[IV_INNER:%.*]] = phi i64 [ 0, %[[OUTER_HEADER]] ], [ [[IV_INNER_NEXT:%.*]], %[[INNER]] ]162; CHECK-NEXT: [[RED:%.*]] = phi i64 [ [[RED_START]], %[[OUTER_HEADER]] ], [ [[RED_NEXT:%.*]], %[[INNER]] ]163; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds [1024 x i64], ptr @B, i64 0, i64 [[IV_INNER]]164; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[GEP_B]], align 4165; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[RED]]166; CHECK-NEXT: [[RED_NEXT]] = add nsw i64 [[ADD]], [[RED]]167; CHECK-NEXT: [[IV_INNER_NEXT]] = add nuw nsw i64 [[IV_INNER]], 1168; CHECK-NEXT: [[INNER_EC:%.*]] = icmp eq i64 [[IV_INNER_NEXT]], [[N]]169; CHECK-NEXT: br i1 [[INNER_EC]], label %[[OUTER_LATCH]], label %[[INNER]]170; CHECK: [[OUTER_LATCH]]:171; CHECK-NEXT: [[RED_NEXT_LCSSA:%.*]] = phi i64 [ [[RED_NEXT]], %[[INNER]] ]172; CHECK-NEXT: store i64 [[RED_NEXT_LCSSA]], ptr [[GEP_A]], align 4173; CHECK-NEXT: [[IV_OUTER_NEXT]] = add nuw nsw i64 [[IV_OUTER]], 1174; CHECK-NEXT: [[OUTER_EC:%.*]] = icmp eq i64 [[IV_OUTER_NEXT]], [[M]]175; CHECK-NEXT: br i1 [[OUTER_EC]], label %[[EXIT]], label %[[OUTER_HEADER]], !llvm.loop [[LOOP5:![0-9]+]]176; CHECK: [[EXIT]]:177; CHECK-NEXT: ret void178;179entry:180 br label %outer.header181 182outer.header:183 %iv.outer = phi i64 [ 0, %entry ], [ %iv.outer.next, %outer.latch ]184 %gep.A = getelementptr inbounds [1024 x i64], ptr @A, i64 0, i64 %iv.outer185 %red.start = load i64 , ptr %gep.A, align 4186 store i32 %c, ptr %gep.A, align 4187 br label %inner188 189inner:190 %iv.inner = phi i64 [ 0, %outer.header ], [ %iv.inner.next, %inner ]191 %red = phi i64 [ %red.start, %outer.header ], [ %red.next, %inner ]192 %gep.B = getelementptr inbounds [1024 x i64], ptr @B, i64 0, i64 %iv.inner193 %2 = load i64, ptr %gep.B, align 4194 %add = add nsw i64 %2, %red195 %red.next = add nsw i64 %add, %red196 %iv.inner.next = add nuw nsw i64 %iv.inner, 1197 %inner.ec = icmp eq i64 %iv.inner.next, %N198 br i1 %inner.ec, label %outer.latch, label %inner199 200outer.latch:201 store i64 %red.next, ptr %gep.A, align 4202 %iv.outer.next = add nuw nsw i64 %iv.outer, 1203 %outer.ec = icmp eq i64 %iv.outer.next, %M204 br i1 %outer.ec, label %exit, label %outer.header, !llvm.loop !1205 206exit:207 ret void208}209 210!1 = distinct !{!1, !2, !3}211!2 = !{!"llvm.loop.vectorize.width", i32 4}212!3 = !{!"llvm.loop.vectorize.enable", i1 true}213