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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -enable-vplan-native-path -passes=loop-vectorize -S %s | FileCheck %s3 4; Make sure phi nodes are generated correctly, even if the use list order of5; the predecessors in the scalar code does not match the order in the generated6; vector blocks.7 8; Test from PR45958.9 10define void @test(ptr %src, i64 %n) {11; CHECK-LABEL: @test(12; CHECK-NEXT: entry:13; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N:%.*]], 414; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]15; CHECK: vector.ph:16; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 417; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]18; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[N]], i64 019; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer20; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]21; CHECK: vector.body:22; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[LOOP_1_LATCH5:%.*]] ]23; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[LOOP_1_LATCH5]] ]24; CHECK-NEXT: br label [[LOOP_2_HEADER1:%.*]]25; CHECK: loop.2.header1:26; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ zeroinitializer, [[VECTOR_BODY]] ], [ [[TMP5:%.*]], [[LOOP_2_LATCH4:%.*]] ]27; CHECK-NEXT: br label [[LOOP_32:%.*]]28; CHECK: loop.32:29; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i64> [ zeroinitializer, [[LOOP_2_HEADER1]] ], [ [[TMP2:%.*]], [[LOOP_32]] ]30; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [2000 x i32], ptr [[SRC:%.*]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI3]]31; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> align 4 [[TMP0]], <4 x i1> splat (i1 true), <4 x i32> poison)32; CHECK-NEXT: [[TMP1:%.*]] = mul nsw <4 x i32> [[WIDE_MASKED_GATHER]], splat (i32 10)33; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> [[TMP1]], <4 x ptr> align 4 [[TMP0]], <4 x i1> splat (i1 true))34; CHECK-NEXT: [[TMP2]] = add nuw nsw <4 x i64> [[VEC_PHI3]], splat (i64 1)35; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <4 x i64> [[TMP2]], [[BROADCAST_SPLAT]]36; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[TMP3]], i32 037; CHECK-NEXT: br i1 [[TMP4]], label [[LOOP_2_LATCH4]], label [[LOOP_32]]38; CHECK: loop.2.latch3:39; CHECK-NEXT: [[TMP5]] = add nuw nsw <4 x i64> [[VEC_PHI]], splat (i64 1)40; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <4 x i64> [[TMP5]], [[BROADCAST_SPLAT]]41; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i1> [[TMP6]], i32 042; CHECK-NEXT: br i1 [[TMP7]], label [[LOOP_1_LATCH5]], label [[LOOP_2_HEADER1]]43; CHECK: vector.latch:44; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 445; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)46; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]47; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]48; CHECK: middle.block:49; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]50; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]51; CHECK: scalar.ph:52; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]53; CHECK-NEXT: br label [[LOOP_1_HEADER:%.*]]54; CHECK: loop.1.header:55; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP_1_LATCH:%.*]] ]56; CHECK-NEXT: br label [[LOOP_2_HEADER:%.*]]57; CHECK: loop.2.header:58; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ 0, [[LOOP_1_HEADER]] ], [ [[IV_2_NEXT:%.*]], [[LOOP_2_LATCH:%.*]] ]59; CHECK-NEXT: br label [[LOOP_3:%.*]]60; CHECK: loop.3:61; CHECK-NEXT: [[IV_3:%.*]] = phi i64 [ 0, [[LOOP_2_HEADER]] ], [ [[IV_3_NEXT:%.*]], [[LOOP_3]] ]62; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds [2000 x i32], ptr [[SRC]], i64 [[IV_1]], i64 [[IV_3]]63; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_SRC]], align 464; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[L1]], 1065; CHECK-NEXT: store i32 [[MUL]], ptr [[GEP_SRC]], align 466; CHECK-NEXT: [[IV_3_NEXT]] = add nuw nsw i64 [[IV_3]], 167; CHECK-NEXT: [[EC_3:%.*]] = icmp eq i64 [[IV_3_NEXT]], [[N]]68; CHECK-NEXT: br i1 [[EC_3]], label [[LOOP_2_LATCH]], label [[LOOP_3]]69; CHECK: loop.2.latch:70; CHECK-NEXT: [[IV_2_NEXT]] = add nuw nsw i64 [[IV_2]], 171; CHECK-NEXT: [[EC_2:%.*]] = icmp eq i64 [[IV_2_NEXT]], [[N]]72; CHECK-NEXT: br i1 [[EC_2]], label [[LOOP_1_LATCH]], label [[LOOP_2_HEADER]]73; CHECK: loop.1.latch:74; CHECK-NEXT: [[IV_1_NEXT]] = add nuw nsw i64 [[IV_1]], 175; CHECK-NEXT: [[EC_1:%.*]] = icmp eq i64 [[IV_1_NEXT]], [[N]]76; CHECK-NEXT: br i1 [[EC_1]], label [[EXIT]], label [[LOOP_1_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]77; CHECK: exit:78; CHECK-NEXT: ret void79;80entry:81 br label %loop.1.header82 83loop.1.header:84 %iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop.1.latch ]85 br label %loop.2.header86 87loop.2.header:88 %iv.2 = phi i64 [ 0, %loop.1.header ], [ %iv.2.next, %loop.2.latch ]89 br label %loop.390 91loop.3:92 %iv.3 = phi i64 [ 0, %loop.2.header ], [ %iv.3.next, %loop.3 ]93 %gep.src = getelementptr inbounds [2000 x i32], ptr %src, i64 %iv.1, i64 %iv.394 %l1 = load i32, ptr %gep.src, align 495 %mul = mul nsw i32 %l1, 1096 store i32 %mul, ptr %gep.src, align 497 %iv.3.next = add nuw nsw i64 %iv.3, 198 %ec.3 = icmp eq i64 %iv.3.next, %n99 br i1 %ec.3, label %loop.2.latch, label %loop.3100 101loop.2.latch:102 %iv.2.next = add nuw nsw i64 %iv.2, 1103 %ec.2 = icmp eq i64 %iv.2.next, %n104 br i1 %ec.2, label %loop.1.latch, label %loop.2.header105 106loop.1.latch:107 %iv.1.next = add nuw nsw i64 %iv.1, 1108 %ec.1 = icmp eq i64 %iv.1.next, %n109 br i1 %ec.1, label %exit, label %loop.1.header, !llvm.loop !0110 111exit: ; preds = %loop.1.latch112 ret void113 114; uselistorder directives115 uselistorder label %loop.3, { 1, 0 }116 uselistorder label %loop.2.header, { 1, 0 }117}118 119!0 = distinct !{!0, !1, !2}120!1 = !{!"llvm.loop.vectorize.width", i32 4}121!2 = !{!"llvm.loop.vectorize.enable", i1 true}122