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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -force-vector-width=4 -S %s | FileCheck %s3 4target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"5 6; Test case where the pointer index with is 32 bits, but the main IV is 64 bit.7; Make sure VFxUF is adjusted accordingly.8define void @wide_ptr_induction_index_width_smaller_than_iv_width(ptr noalias %src, ptr noalias %dst.0, ptr noalias %dst.1) {9; CHECK-LABEL: define void @wide_ptr_induction_index_width_smaller_than_iv_width(10; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST_0:%.*]], ptr noalias [[DST_1:%.*]]) {11; CHECK-NEXT: [[ENTRY:.*:]]12; CHECK-NEXT: br label %[[VECTOR_PH:.*]]13; CHECK: [[VECTOR_PH]]:14; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[SRC]], i32 80015; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]16; CHECK: [[VECTOR_BODY]]:17; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]18; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 019; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 120; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 221; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 322; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[INDEX]] to i3223; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i32 [[DOTCAST]], 824; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[OFFSET_IDX]], 025; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[OFFSET_IDX]], 826; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[OFFSET_IDX]], 1627; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[OFFSET_IDX]], 2428; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[SRC]], i32 [[TMP11]]29; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[SRC]], i32 [[TMP6]]30; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[SRC]], i32 [[TMP16]]31; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[SRC]], i32 [[TMP17]]32; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP5]], align 133; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[DST_0]], i64 [[TMP1]]34; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[DST_0]], i64 [[TMP2]]35; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[DST_0]], i64 [[TMP3]]36; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[DST_0]], i64 [[TMP4]]37; CHECK-NEXT: store <4 x i64> [[WIDE_LOAD]], ptr [[TMP7]], align 838; CHECK-NEXT: store ptr [[TMP5]], ptr [[TMP7]], align 839; CHECK-NEXT: store ptr [[TMP12]], ptr [[TMP8]], align 840; CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP9]], align 841; CHECK-NEXT: store ptr [[TMP14]], ptr [[TMP10]], align 842; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 443; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10044; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]45; CHECK: [[MIDDLE_BLOCK]]:46; CHECK-NEXT: br label %[[SCALAR_PH:.*]]47; CHECK: [[SCALAR_PH]]:48; CHECK-NEXT: br label %[[LOOP:.*]]49; CHECK: [[LOOP]]:50; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 100, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]51; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[TMP0]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ]52; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 153; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds i64, ptr [[DST_0]], i64 [[IV]]54; CHECK-NEXT: store i64 [[L]], ptr [[GEP_DST_1]], align 855; CHECK-NEXT: [[GEP_DST_0:%.*]] = getelementptr inbounds ptr, ptr [[DST_1]], i64 [[IV]]56; CHECK-NEXT: store ptr [[PTR_IV]], ptr [[GEP_DST_1]], align 857; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 158; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i32 859; CHECK-NEXT: [[EC:%.*]] = icmp ult i64 [[IV]], 10060; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT:.*]], !llvm.loop [[LOOP3:![0-9]+]]61; CHECK: [[EXIT]]:62; CHECK-NEXT: ret void63;64entry:65 br label %loop66 67loop:68 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]69 %ptr.iv = phi ptr [ %src, %entry ], [ %ptr.iv.next, %loop ]70 %l = load i64, ptr %ptr.iv, align 171 %gep.dst.1 = getelementptr inbounds i64, ptr %dst.0, i64 %iv72 store i64 %l, ptr %gep.dst.1, align 873 %gep.dst.0 = getelementptr inbounds ptr, ptr %dst.1, i64 %iv74 store ptr %ptr.iv, ptr %gep.dst.1, align 875 %iv.next = add i64 %iv, 176 %ptr.iv.next = getelementptr i8, ptr %ptr.iv, i32 877 %ec = icmp ult i64 %iv, 10078 br i1 %ec, label %loop, label %exit79 80exit:81 ret void82}83;.84; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}85; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}86; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}87; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}88;.89