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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "scalar.ph:" --version 52; RUN: opt -passes='loop-vectorize' -force-vector-width=2 -S < %s | FileCheck %s3;4; Forcing VF=2 to trigger vector code gen5;6; This is a test case that let's vectorizer's code gen to generate7; more than one BasicBlocks in the loop body (emulated masked scatter)8; for those targets that do not support masked scatter. Broadcast9; code generation was previously dependent on loop body being10; a single basic block and this test case exposed incorrect code gen11; resulting in an assert in IL verification.12;13@a = external global [2 x i16], align 114 15define void @f1(ptr noalias %b, i1 %c, i32 %start) {16; CHECK-LABEL: define void @f1(17; CHECK-SAME: ptr noalias [[B:%.*]], i1 [[C:%.*]], i32 [[START:%.*]]) {18; CHECK-NEXT: [[ENTRY:.*:]]19; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[START]], 120; CHECK-NEXT: [[SMIN1:%.*]] = call i32 @llvm.smin.i32(i32 [[START]], i32 1)21; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[SMIN1]]22; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 223; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]24; CHECK: [[VECTOR_SCEVCHECK]]:25; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[START]], i32 1)26; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[START]], [[SMIN]]27; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[START]] to i1628; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP2]] to i1629; CHECK-NEXT: [[TMP5:%.*]] = sub i16 [[TMP3]], [[TMP4]]30; CHECK-NEXT: [[TMP6:%.*]] = icmp sgt i16 [[TMP5]], [[TMP3]]31; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i32 [[TMP2]], 6553532; CHECK-NEXT: [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP8]]33; CHECK-NEXT: br i1 [[TMP9]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]34; CHECK: [[VECTOR_PH]]:35; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 236; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]]37; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i1> poison, i1 [[C]], i64 038; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i1> [[BROADCAST_SPLATINSERT]], <2 x i1> poison, <2 x i32> zeroinitializer39; CHECK-NEXT: [[TMP10:%.*]] = sub i32 [[START]], [[N_VEC]]40; CHECK-NEXT: [[TMP11:%.*]] = xor <2 x i1> [[BROADCAST_SPLAT]], splat (i1 true)41; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]42; CHECK: [[VECTOR_BODY]]:43; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE3:.*]] ]44; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i32 [[START]], [[INDEX]]45; CHECK-NEXT: [[TMP12:%.*]] = trunc i32 [[OFFSET_IDX]] to i1646; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i1> [[TMP11]], i32 047; CHECK-NEXT: br i1 [[TMP13]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]48; CHECK: [[PRED_STORE_IF]]:49; CHECK-NEXT: store i32 10, ptr [[B]], align 150; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]51; CHECK: [[PRED_STORE_CONTINUE]]:52; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP11]], i32 153; CHECK-NEXT: br i1 [[TMP14]], label %[[PRED_STORE_IF2:.*]], label %[[PRED_STORE_CONTINUE3]]54; CHECK: [[PRED_STORE_IF2]]:55; CHECK-NEXT: store i32 10, ptr [[B]], align 156; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE3]]57; CHECK: [[PRED_STORE_CONTINUE3]]:58; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i16], ptr @a, i16 0, i16 [[TMP12]]59; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i16, ptr [[TMP15]], i64 060; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i16, ptr [[TMP16]], i64 -161; CHECK-NEXT: store <2 x i16> zeroinitializer, ptr [[TMP17]], align 162; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 263; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]64; CHECK-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]65; CHECK: [[MIDDLE_BLOCK]]:66; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]]67; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]68; CHECK: [[SCALAR_PH]]:69;70entry:71 br label %loop.header72 73loop.header:74 %iv = phi i32 [ %start, %entry ], [ %iv.next, %loop.latch ]75 br i1 %c, label %loop.latch, label %else76 77else:78 store i32 10, ptr %b, align 179 br label %loop.latch80 81loop.latch:82 %t = trunc i32 %iv to i1683 %arrayidx = getelementptr inbounds [2 x i16], ptr @a, i16 0, i16 %t84 store i16 0, ptr %arrayidx, align 185 %iv.next = add nsw i32 %iv, -186 %cmp = icmp sgt i32 %iv, 187 br i1 %cmp, label %loop.header, label %exit88 89exit:90 ret void91}92 93define void @f2(ptr noalias %b, i1 %c, i32 %start) {94; CHECK-LABEL: define void @f2(95; CHECK-SAME: ptr noalias [[B:%.*]], i1 [[C:%.*]], i32 [[START:%.*]]) {96; CHECK-NEXT: [[ENTRY:.*:]]97; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[START]], 198; CHECK-NEXT: [[SMIN1:%.*]] = call i32 @llvm.smin.i32(i32 [[START]], i32 1)99; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[SMIN1]]100; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 2101; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]102; CHECK: [[VECTOR_SCEVCHECK]]:103; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[START]], i32 1)104; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[START]], [[SMIN]]105; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[START]] to i16106; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP2]] to i16107; CHECK-NEXT: [[TMP5:%.*]] = sub i16 [[TMP3]], [[TMP4]]108; CHECK-NEXT: [[TMP6:%.*]] = icmp sgt i16 [[TMP5]], [[TMP3]]109; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i32 [[TMP2]], 65535110; CHECK-NEXT: [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP8]]111; CHECK-NEXT: br i1 [[TMP9]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]112; CHECK: [[VECTOR_PH]]:113; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 2114; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]]115; CHECK-NEXT: [[TMP10:%.*]] = sub i32 [[START]], [[N_VEC]]116; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]117; CHECK: [[VECTOR_BODY]]:118; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]119; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i32 [[START]], [[INDEX]]120; CHECK-NEXT: [[TMP11:%.*]] = trunc i32 [[OFFSET_IDX]] to i16121; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i16], ptr @a, i16 0, i16 [[TMP11]]122; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i16, ptr [[TMP12]], i64 0123; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i16, ptr [[TMP13]], i64 -1124; CHECK-NEXT: store <2 x i16> zeroinitializer, ptr [[TMP14]], align 1125; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2126; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]127; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]128; CHECK: [[MIDDLE_BLOCK]]:129; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]]130; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]131; CHECK: [[SCALAR_PH]]:132;133entry:134 br label %loop.header135 136loop.header:137 %iv = phi i32 [ %start, %entry ], [ %iv.next, %loop.latch ]138 br i1 %c, label %loop.latch, label %else139 140else:141 %1 = load i32, ptr %b, align 1142 br label %loop.latch143 144loop.latch:145 %2 = trunc i32 %iv to i16146 %arrayidx = getelementptr inbounds [2 x i16], ptr @a, i16 0, i16 %2147 store i16 0, ptr %arrayidx, align 1148 %iv.next = add nsw i32 %iv, -1149 %cmp = icmp sgt i32 %iv, 1150 br i1 %cmp, label %loop.header, label %exit151 152exit:153 ret void154}155