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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -force-vector-width=2 -force-vector-interleave=1 -force-widen-divrem-via-safe-divisor=0 -passes=loop-vectorize -S | FileCheck %s3 4; Test case for PR44488. Checks that the correct predicates are created for5; branches where true and false successors are equal. See the checks involving6; CMP1 and CMP2.7 8@v_38 = global i16 12061, align 19@v_39 = global i16 11333, align 110 11define i16 @test_true_and_false_branch_equal() {12; CHECK-LABEL: @test_true_and_false_branch_equal(13; CHECK-NEXT: entry:14; CHECK-NEXT: br label [[VECTOR_PH:%.*]]15; CHECK: vector.ph:16; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]17; CHECK: vector.body:18; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_SREM_CONTINUE2:%.*]] ]19; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr @v_38, align 120; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[TMP0]], i64 021; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT]], <2 x i16> poison, <2 x i32> zeroinitializer22; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i16> [[BROADCAST_SPLAT]], zeroinitializer23; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 024; CHECK-NEXT: br i1 [[TMP3]], label [[PRED_SREM_IF:%.*]], label [[PRED_SREM_CONTINUE:%.*]]25; CHECK: pred.srem.if:26; CHECK-NEXT: [[TMP4:%.*]] = srem i16 5786, [[TMP0]]27; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i16> poison, i16 [[TMP4]], i32 028; CHECK-NEXT: br label [[PRED_SREM_CONTINUE]]29; CHECK: pred.srem.continue:30; CHECK-NEXT: [[TMP6:%.*]] = phi <2 x i16> [ poison, [[VECTOR_BODY]] ], [ [[TMP5]], [[PRED_SREM_IF]] ]31; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP2]], i32 132; CHECK-NEXT: br i1 [[TMP7]], label [[PRED_SREM_IF1:%.*]], label [[PRED_SREM_CONTINUE2]]33; CHECK: pred.srem.if1:34; CHECK-NEXT: [[TMP8:%.*]] = srem i16 5786, [[TMP0]]35; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i16> [[TMP6]], i16 [[TMP8]], i32 136; CHECK-NEXT: br label [[PRED_SREM_CONTINUE2]]37; CHECK: pred.srem.continue2:38; CHECK-NEXT: [[TMP10:%.*]] = phi <2 x i16> [ [[TMP6]], [[PRED_SREM_CONTINUE]] ], [ [[TMP9]], [[PRED_SREM_IF1]] ]39; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i1> [[TMP2]], i32 040; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP13]], <2 x i16> [[TMP10]], <2 x i16> splat (i16 5786)41; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i16> [[PREDPHI]], i32 142; CHECK-NEXT: store i16 [[TMP11]], ptr @v_39, align 143; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 244; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1245; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]46; CHECK: middle.block:47; CHECK-NEXT: br label [[FOR_LATCH:%.*]]48; CHECK: exit:49; CHECK-NEXT: [[RV:%.*]] = load i16, ptr @v_39, align 150; CHECK-NEXT: ret i16 [[RV]]51;52entry:53 br label %for.body54 55for.body: ; preds = %entry, %for.latch56 %i.07 = phi i16 [ 99, %entry ], [ %inc7, %for.latch ]57 %lv = load i16, ptr @v_38, align 158 %cmp1 = icmp eq i16 %lv, 3276759 br i1 %cmp1, label %cond.end, label %cond.end60 61cond.end: ; preds = %for.body, %for.body62 %cmp2 = icmp eq i16 %lv, 063 br i1 %cmp2, label %for.latch, label %cond.false464 65cond.false4: ; preds = %cond.end66 %rem = srem i16 5786, %lv67 br label %for.latch68 69for.latch: ; preds = %cond.end, %cond.false470 %cond6 = phi i16 [ %rem, %cond.false4 ], [ 5786, %cond.end ]71 store i16 %cond6, ptr @v_39, align 172 %inc7 = add nsw i16 %i.07, 173 %cmp = icmp slt i16 %inc7, 11174 br i1 %cmp, label %for.body, label %exit75 76exit: ; preds = %for.latch77 %rv = load i16, ptr @v_39, align 178 ret i16 %rv79}80