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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=loop-vectorize -force-vector-width=2 -S -prefer-predicate-over-epilogue=predicate-dont-vectorize %s | FileCheck %s3 4 5; Test case for PR46525. There are two candidates to pick for6; `udiv i64 %y, %add` when expanding SCEV expressions. Make sure we pick %div,7; which dominates the vector loop.8 9define void @test(i16 %x, i64 %y, ptr %ptr) {10; CHECK-LABEL: @test(11; CHECK-NEXT: entry:12; CHECK-NEXT: [[CONV19:%.*]] = sext i16 [[X:%.*]] to i6413; CHECK-NEXT: [[ADD:%.*]] = add i64 [[CONV19]], 49280276883081406714; CHECK-NEXT: br label [[LOOP_PREHEADER:%.*]]15; CHECK: loop.preheader:16; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[Y:%.*]], [[ADD]]17; CHECK-NEXT: [[INC:%.*]] = add i64 [[DIV]], 118; CHECK-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[DIV]], 419; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[TMP0]], [[INC]]20; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 121; CHECK-NEXT: br label [[VECTOR_PH:%.*]]22; CHECK: vector.ph:23; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP2]], 124; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 225; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]26; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]27; CHECK: vector.body:28; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]29; CHECK-NEXT: store i32 0, ptr [[PTR:%.*]], align 430; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 231; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]32; CHECK-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]33; CHECK: middle.block:34; CHECK-NEXT: br label [[LOOP:%.*]]35; CHECK: loop.exit:36; CHECK-NEXT: [[DIV_1:%.*]] = udiv i64 [[Y]], [[ADD]]37; CHECK-NEXT: [[V1:%.*]] = add i64 [[DIV_1]], 138; CHECK-NEXT: br label [[LOOP_2:%.*]]39; CHECK: loop.2:40; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ [[IV_NEXT_1:%.*]], [[LOOP_2]] ], [ 0, [[LOOP]] ]41; CHECK-NEXT: [[IV_NEXT_1]] = add i64 [[IV_1]], [[V1]]42; CHECK-NEXT: call void @use(i64 [[IV_NEXT_1]])43; CHECK-NEXT: [[EC:%.*]] = icmp ult i64 [[IV_NEXT_1]], 20044; CHECK-NEXT: br i1 [[EC]], label [[LOOP_2]], label [[LOOP_2_EXIT:%.*]]45; CHECK: loop.2.exit:46; CHECK-NEXT: [[C:%.*]] = call i1 @cond()47; CHECK-NEXT: br i1 [[C]], label [[LOOP_PREHEADER]], label [[EXIT:%.*]]48; CHECK: exit:49; CHECK-NEXT: ret void50;51entry:52 %conv19 = sext i16 %x to i6453 %add = add i64 %conv19, 49280276883081406754 br label %loop.preheader55 56loop.preheader:57 %div = udiv i64 %y, %add58 %inc = add i64 %div, 159 br label %loop60 61loop:62 %iv = phi i64 [ %iv.next, %loop ], [ 0, %loop.preheader ]63 store i32 0, ptr %ptr, align 464 %v2 = trunc i64 %iv to i865 %v3 = add i8 %v2, 166 %cmp15 = icmp slt i8 %v3, 567 %iv.next = add i64 %iv, %inc68 br i1 %cmp15, label %loop, label %loop.exit69 70loop.exit:71 %div.1 = udiv i64 %y, %add72 %v1 = add i64 %div.1, 173 br label %loop.274 75loop.2:76 %iv.1 = phi i64 [ %iv.next.1, %loop.2 ], [ 0, %loop.exit ]77 %iv.next.1 = add i64 %iv.1, %v178 call void @use(i64 %iv.next.1)79 %ec = icmp ult i64 %iv.next.1, 20080 br i1 %ec, label %loop.2, label %loop.2.exit81 82loop.2.exit:83 %c = call i1 @cond()84 br i1 %c, label %loop.preheader, label %exit85 86exit:87 ret void88}89 90declare void @use(i64)91declare i1 @cond()92