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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 62; RUN: opt -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S %s | FileCheck --check-prefix=VF2 %s3; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s4 5define void @test1_pr58811(ptr %dst) {6; VF2-LABEL: define void @test1_pr58811(7; VF2-SAME: ptr [[DST:%.*]]) {8; VF2-NEXT: [[ENTRY:.*]]:9; VF2-NEXT: br label %[[LOOP_1_PREHEADER:.*]]10; VF2: [[LOOP_1_PREHEADER]]:11; VF2-NEXT: [[IV_1_PH:%.*]] = phi i32 [ [[SUB93_2:%.*]], %[[UNREACHABLE_BB:.*]] ], [ 0, %[[ENTRY]] ]12; VF2-NEXT: [[TMP0:%.*]] = sub i32 0, [[IV_1_PH]]13; VF2-NEXT: br label %[[LOOP_1:.*]]14; VF2: [[LOOP_1]]:15; VF2-NEXT: [[INDUCTION_IV:%.*]] = phi i32 [ [[INDUCTION_IV_NEXT:%.*]], %[[LOOP_1]] ], [ [[TMP0]], %[[LOOP_1_PREHEADER]] ]16; VF2-NEXT: [[IV_1:%.*]] = phi i32 [ [[IV_1_NEXT:%.*]], %[[LOOP_1]] ], [ [[IV_1_PH]], %[[LOOP_1_PREHEADER]] ]17; VF2-NEXT: [[IV_2:%.*]] = phi i32 [ [[IV_2_NEXT:%.*]], %[[LOOP_1]] ], [ 0, %[[LOOP_1_PREHEADER]] ]18; VF2-NEXT: [[TMP1:%.*]] = mul nuw nsw i32 [[IV_2]], -119; VF2-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 120; VF2-NEXT: [[IV_1_NEXT]] = add i32 [[IV_2]], [[IV_1]]21; VF2-NEXT: [[INDUCTION_IV_NEXT]] = add i32 [[INDUCTION_IV]], [[TMP1]]22; VF2-NEXT: br i1 false, label %[[LOOP_1]], label %[[LOOP_2_PREHEADER:.*]]23; VF2: [[LOOP_2_PREHEADER]]:24; VF2-NEXT: [[IV_1_LCSSA:%.*]] = phi i32 [ [[IV_1]], %[[LOOP_1]] ]25; VF2-NEXT: br label %[[VECTOR_PH:.*]]26; VF2: [[VECTOR_PH]]:27; VF2-NEXT: [[TMP2:%.*]] = mul i32 198, [[INDUCTION_IV]]28; VF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[INDUCTION_IV]], i64 029; VF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer30; VF2-NEXT: [[TMP3:%.*]] = mul <2 x i32> <i32 0, i32 1>, [[BROADCAST_SPLAT]]31; VF2-NEXT: [[INDUCTION:%.*]] = add <2 x i32> zeroinitializer, [[TMP3]]32; VF2-NEXT: [[TMP4:%.*]] = mul i32 [[INDUCTION_IV]], 233; VF2-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <2 x i32> poison, i32 [[TMP4]], i64 034; VF2-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT1]], <2 x i32> poison, <2 x i32> zeroinitializer35; VF2-NEXT: br label %[[VECTOR_BODY:.*]]36; VF2: [[VECTOR_BODY]]:37; VF2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]38; VF2-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]39; VF2-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i1640; VF2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[DST]], i16 [[OFFSET_IDX]]41; VF2-NEXT: store <2 x i32> [[VEC_IND]], ptr [[TMP5]], align 442; VF2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 243; VF2-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]44; VF2-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 19845; VF2-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]46; VF2: [[MIDDLE_BLOCK]]:47; VF2-NEXT: br label %[[SCALAR_PH:.*]]48; VF2: [[SCALAR_PH]]:49; VF2-NEXT: br label %[[LOOP_2:.*]]50; VF2: [[LOOP_2]]:51; VF2-NEXT: [[IV_3:%.*]] = phi i16 [ [[IV_3_NEXT:%.*]], %[[LOOP_2]] ], [ 198, %[[SCALAR_PH]] ]52; VF2-NEXT: [[IV_4:%.*]] = phi i32 [ [[IV_4_NEXT:%.*]], %[[LOOP_2]] ], [ [[TMP2]], %[[SCALAR_PH]] ]53; VF2-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i32, ptr [[DST]], i16 [[IV_3]]54; VF2-NEXT: store i32 [[IV_4]], ptr [[GEP_DST]], align 455; VF2-NEXT: [[IV_4_NEXT]] = sub i32 [[IV_4]], [[IV_1_LCSSA]]56; VF2-NEXT: [[IV_3_NEXT]] = add i16 [[IV_3]], 157; VF2-NEXT: [[CMP88_1:%.*]] = icmp ult i16 [[IV_3]], 19858; VF2-NEXT: br i1 [[CMP88_1]], label %[[LOOP_2]], label %[[LOOP_3_PREHEADER:.*]], !llvm.loop [[LOOP3:![0-9]+]]59; VF2: [[LOOP_3_PREHEADER]]:60; VF2-NEXT: [[IV_4_LCSSA:%.*]] = phi i32 [ [[IV_4]], %[[LOOP_2]] ]61; VF2-NEXT: br label %[[LOOP_3:.*]]62; VF2: [[LOOP_3]]:63; VF2-NEXT: [[IV_5:%.*]] = phi i32 [ [[SUB93_2]], %[[LOOP_3]] ], [ 0, %[[LOOP_3_PREHEADER]] ]64; VF2-NEXT: [[SUB93_2]] = sub i32 [[IV_5]], [[IV_4_LCSSA]]65; VF2-NEXT: br label %[[LOOP_3]]66; VF2: [[UNREACHABLE_BB]]:67; VF2-NEXT: br label %[[LOOP_1_PREHEADER]]68;69; CHECK-LABEL: define void @test1_pr58811(70; CHECK-SAME: ptr [[DST:%.*]]) {71; CHECK-NEXT: [[ENTRY:.*]]:72; CHECK-NEXT: br label %[[LOOP_1_PREHEADER:.*]]73; CHECK: [[LOOP_1_PREHEADER]]:74; CHECK-NEXT: [[IV_1_PH:%.*]] = phi i32 [ [[SUB93_2:%.*]], %[[UNREACHABLE_BB:.*]] ], [ 0, %[[ENTRY]] ]75; CHECK-NEXT: [[TMP0:%.*]] = sub i32 0, [[IV_1_PH]]76; CHECK-NEXT: br label %[[LOOP_1:.*]]77; CHECK: [[LOOP_1]]:78; CHECK-NEXT: [[INDUCTION_IV:%.*]] = phi i32 [ [[INDUCTION_IV_NEXT:%.*]], %[[LOOP_1]] ], [ [[TMP0]], %[[LOOP_1_PREHEADER]] ]79; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ [[IV_1_NEXT:%.*]], %[[LOOP_1]] ], [ [[IV_1_PH]], %[[LOOP_1_PREHEADER]] ]80; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[IV_2_NEXT:%.*]], %[[LOOP_1]] ], [ 0, %[[LOOP_1_PREHEADER]] ]81; CHECK-NEXT: [[TMP1:%.*]] = mul nuw nsw i32 [[IV_2]], -182; CHECK-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 183; CHECK-NEXT: [[IV_1_NEXT]] = add i32 [[IV_2]], [[IV_1]]84; CHECK-NEXT: [[INDUCTION_IV_NEXT]] = add i32 [[INDUCTION_IV]], [[TMP1]]85; CHECK-NEXT: br i1 false, label %[[LOOP_1]], label %[[LOOP_2_PREHEADER:.*]]86; CHECK: [[LOOP_2_PREHEADER]]:87; CHECK-NEXT: [[IV_1_LCSSA:%.*]] = phi i32 [ [[IV_1]], %[[LOOP_1]] ]88; CHECK-NEXT: br label %[[VECTOR_PH:.*]]89; CHECK: [[VECTOR_PH]]:90; CHECK-NEXT: [[IND_END:%.*]] = mul i32 196, [[INDUCTION_IV]]91; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[INDUCTION_IV]], i64 092; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer93; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[BROADCAST_SPLAT]]94; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> zeroinitializer, [[TMP3]]95; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[INDUCTION_IV]], 496; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i64 097; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT1]], <4 x i32> poison, <4 x i32> zeroinitializer98; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]99; CHECK: [[VECTOR_BODY]]:100; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]101; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]102; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16103; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[DST]], i16 [[OFFSET_IDX]]104; CHECK-NEXT: store <4 x i32> [[VEC_IND]], ptr [[TMP5]], align 4105; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4106; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]107; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], 196108; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]109; CHECK: [[MIDDLE_BLOCK]]:110; CHECK-NEXT: br label %[[SCALAR_PH:.*]]111; CHECK: [[SCALAR_PH]]:112; CHECK-NEXT: br label %[[LOOP_2:.*]]113; CHECK: [[LOOP_2]]:114; CHECK-NEXT: [[IV_3:%.*]] = phi i16 [ [[IV_3_NEXT:%.*]], %[[LOOP_2]] ], [ 196, %[[SCALAR_PH]] ]115; CHECK-NEXT: [[IV_4:%.*]] = phi i32 [ [[IV_4_NEXT:%.*]], %[[LOOP_2]] ], [ [[IND_END]], %[[SCALAR_PH]] ]116; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i32, ptr [[DST]], i16 [[IV_3]]117; CHECK-NEXT: store i32 [[IV_4]], ptr [[GEP_DST]], align 4118; CHECK-NEXT: [[IV_4_NEXT]] = sub i32 [[IV_4]], [[IV_1_LCSSA]]119; CHECK-NEXT: [[IV_3_NEXT]] = add i16 [[IV_3]], 1120; CHECK-NEXT: [[CMP88_1:%.*]] = icmp ult i16 [[IV_3]], 198121; CHECK-NEXT: br i1 [[CMP88_1]], label %[[LOOP_2]], label %[[LOOP_3_PREHEADER:.*]], !llvm.loop [[LOOP3:![0-9]+]]122; CHECK: [[LOOP_3_PREHEADER]]:123; CHECK-NEXT: [[IV_4_LCSSA:%.*]] = phi i32 [ [[IV_4]], %[[LOOP_2]] ]124; CHECK-NEXT: br label %[[LOOP_3:.*]]125; CHECK: [[LOOP_3]]:126; CHECK-NEXT: [[IV_5:%.*]] = phi i32 [ [[SUB93_2]], %[[LOOP_3]] ], [ 0, %[[LOOP_3_PREHEADER]] ]127; CHECK-NEXT: [[SUB93_2]] = sub i32 [[IV_5]], [[IV_4_LCSSA]]128; CHECK-NEXT: br label %[[LOOP_3]]129; CHECK: [[UNREACHABLE_BB]]:130; CHECK-NEXT: br label %[[LOOP_1_PREHEADER]]131;132entry:133 br label %loop.1.preheader134 135loop.1.preheader:136 %iv.1.ph = phi i32 [ %sub93.2, %unreachable.bb ], [ 0, %entry ]137 br label %loop.1138 139loop.1:140 %iv.1 = phi i32 [ %iv.1.next, %loop.1 ], [ %iv.1.ph, %loop.1.preheader ]141 %iv.2 = phi i32 [ %iv.2.next, %loop.1 ], [ 0, %loop.1.preheader ]142 %iv.2.next = add i32 %iv.2, 1143 %iv.1.next = add i32 %iv.2, %iv.1144 br i1 false, label %loop.1, label %loop.2.preheader145 146loop.2.preheader:147 %iv.1.lcssa = phi i32 [ %iv.1, %loop.1 ]148 br label %loop.2149 150loop.2:151 %iv.3 = phi i16 [ %iv.3.next, %loop.2 ], [ 0, %loop.2.preheader ]152 %iv.4 = phi i32 [ %iv.4.next, %loop.2 ], [ 0, %loop.2.preheader ]153 %gep.dst = getelementptr inbounds i32, ptr %dst, i16 %iv.3154 store i32 %iv.4, ptr %gep.dst155 %iv.4.next = sub i32 %iv.4, %iv.1.lcssa156 %iv.3.next = add i16 %iv.3, 1157 %cmp88.1 = icmp ult i16 %iv.3, 198158 br i1 %cmp88.1, label %loop.2, label %loop.3.preheader159 160loop.3.preheader:161 %iv.4.lcssa = phi i32 [ %iv.4, %loop.2 ]162 br label %loop.3163 164loop.3:165 %iv.5 = phi i32 [ %sub93.2, %loop.3 ], [ 0, %loop.3.preheader ]166 %sub93.2 = sub i32 %iv.5, %iv.4.lcssa167 br label %loop.3168 169unreachable.bb: ; No predecessors!170 br label %loop.1.preheader171}172 173define void @test2_pr58811(ptr %dst) {174; VF2-LABEL: define void @test2_pr58811(175; VF2-SAME: ptr [[DST:%.*]]) {176; VF2-NEXT: [[ENTRY:.*]]:177; VF2-NEXT: br label %[[LOOP_1_HEADER:.*]]178; VF2: [[LOOP_1_HEADER_LOOPEXIT:.*]]:179; VF2-NEXT: [[SUB93_2_LCSSA:%.*]] = phi i32 [ [[SUB93_2:%.*]], %[[LOOP_4:.*]] ]180; VF2-NEXT: br label %[[LOOP_1_HEADER]]181; VF2: [[LOOP_1_HEADER]]:182; VF2-NEXT: [[P_1:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUB93_2_LCSSA]], %[[LOOP_1_HEADER_LOOPEXIT]] ]183; VF2-NEXT: [[TMP0:%.*]] = mul i32 [[P_1]], -1184; VF2-NEXT: br label %[[LOOP_2:.*]]185; VF2: [[LOOP_2]]:186; VF2-NEXT: [[INDUCTION_IV:%.*]] = phi i32 [ [[INDUCTION_IV_NEXT:%.*]], %[[LOOP_2]] ], [ [[TMP0]], %[[LOOP_1_HEADER]] ]187; VF2-NEXT: [[IV_2:%.*]] = phi i32 [ [[P_1]], %[[LOOP_1_HEADER]] ], [ [[ADD101:%.*]], %[[LOOP_2]] ]188; VF2-NEXT: [[IV_3:%.*]] = phi i32 [ 0, %[[LOOP_1_HEADER]] ], [ [[SUB93:%.*]], %[[LOOP_2]] ]189; VF2-NEXT: [[TMP1:%.*]] = mul nuw nsw i32 [[IV_3]], -1190; VF2-NEXT: [[SUB93]] = add i32 [[IV_3]], 1191; VF2-NEXT: [[ADD101]] = add i32 [[IV_3]], [[IV_2]]192; VF2-NEXT: [[INDUCTION_IV_NEXT]] = add i32 [[INDUCTION_IV]], [[TMP1]]193; VF2-NEXT: br i1 false, label %[[LOOP_2]], label %[[LOOP_3_PREHEADER:.*]]194; VF2: [[LOOP_3_PREHEADER]]:195; VF2-NEXT: [[INDUCTION_IV_LCSSA:%.*]] = phi i32 [ [[INDUCTION_IV]], %[[LOOP_2]] ]196; VF2-NEXT: [[IV_2_LCSSA:%.*]] = phi i32 [ [[IV_2]], %[[LOOP_2]] ]197; VF2-NEXT: br label %[[VECTOR_PH:.*]]198; VF2: [[VECTOR_PH]]:199; VF2-NEXT: [[TMP2:%.*]] = mul i32 198, [[INDUCTION_IV_LCSSA]]200; VF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[INDUCTION_IV_LCSSA]], i64 0201; VF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer202; VF2-NEXT: [[TMP3:%.*]] = mul <2 x i32> <i32 0, i32 1>, [[BROADCAST_SPLAT]]203; VF2-NEXT: [[INDUCTION:%.*]] = add <2 x i32> zeroinitializer, [[TMP3]]204; VF2-NEXT: [[TMP4:%.*]] = mul i32 [[INDUCTION_IV_LCSSA]], 2205; VF2-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <2 x i32> poison, i32 [[TMP4]], i64 0206; VF2-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT1]], <2 x i32> poison, <2 x i32> zeroinitializer207; VF2-NEXT: br label %[[VECTOR_BODY:.*]]208; VF2: [[VECTOR_BODY]]:209; VF2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]210; VF2-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]211; VF2-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16212; VF2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[DST]], i16 [[OFFSET_IDX]]213; VF2-NEXT: store <2 x i32> [[VEC_IND]], ptr [[TMP5]], align 4214; VF2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2215; VF2-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]216; VF2-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 198217; VF2-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]218; VF2: [[MIDDLE_BLOCK]]:219; VF2-NEXT: br label %[[SCALAR_PH:.*]]220; VF2: [[SCALAR_PH]]:221; VF2-NEXT: br label %[[LOOP_3:.*]]222; VF2: [[LOOP_3]]:223; VF2-NEXT: [[IV_4:%.*]] = phi i16 [ [[INC_1:%.*]], %[[LOOP_3]] ], [ 198, %[[SCALAR_PH]] ]224; VF2-NEXT: [[IV_5:%.*]] = phi i32 [ [[SUB93_1:%.*]], %[[LOOP_3]] ], [ [[TMP2]], %[[SCALAR_PH]] ]225; VF2-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i32, ptr [[DST]], i16 [[IV_4]]226; VF2-NEXT: store i32 [[IV_5]], ptr [[GEP_DST]], align 4227; VF2-NEXT: [[SUB93_1]] = sub i32 [[IV_5]], [[IV_2_LCSSA]]228; VF2-NEXT: [[INC_1]] = add i16 [[IV_4]], 1229; VF2-NEXT: [[CMP88_1:%.*]] = icmp ult i16 [[IV_4]], 198230; VF2-NEXT: br i1 [[CMP88_1]], label %[[LOOP_3]], label %[[LOOP_4_PREHEADER:.*]], !llvm.loop [[LOOP5:![0-9]+]]231; VF2: [[LOOP_4_PREHEADER]]:232; VF2-NEXT: [[IV_5_LCSSA:%.*]] = phi i32 [ [[IV_5]], %[[LOOP_3]] ]233; VF2-NEXT: br label %[[LOOP_4]]234; VF2: [[LOOP_4]]:235; VF2-NEXT: [[IV_6:%.*]] = phi i32 [ [[SUB93_2]], %[[LOOP_4]] ], [ 0, %[[LOOP_4_PREHEADER]] ]236; VF2-NEXT: [[SUB93_2]] = sub i32 [[IV_6]], [[IV_5_LCSSA]]237; VF2-NEXT: br i1 false, label %[[LOOP_4]], label %[[LOOP_1_HEADER_LOOPEXIT]]238;239; CHECK-LABEL: define void @test2_pr58811(240; CHECK-SAME: ptr [[DST:%.*]]) {241; CHECK-NEXT: [[ENTRY:.*]]:242; CHECK-NEXT: br label %[[LOOP_1_HEADER:.*]]243; CHECK: [[LOOP_1_HEADER_LOOPEXIT:.*]]:244; CHECK-NEXT: [[SUB93_2_LCSSA:%.*]] = phi i32 [ [[SUB93_2:%.*]], %[[LOOP_4:.*]] ]245; CHECK-NEXT: br label %[[LOOP_1_HEADER]]246; CHECK: [[LOOP_1_HEADER]]:247; CHECK-NEXT: [[P_1:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUB93_2_LCSSA]], %[[LOOP_1_HEADER_LOOPEXIT]] ]248; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[P_1]], -1249; CHECK-NEXT: br label %[[LOOP_2:.*]]250; CHECK: [[LOOP_2]]:251; CHECK-NEXT: [[INDUCTION_IV:%.*]] = phi i32 [ [[INDUCTION_IV_NEXT:%.*]], %[[LOOP_2]] ], [ [[TMP0]], %[[LOOP_1_HEADER]] ]252; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[P_1]], %[[LOOP_1_HEADER]] ], [ [[ADD101:%.*]], %[[LOOP_2]] ]253; CHECK-NEXT: [[IV_3:%.*]] = phi i32 [ 0, %[[LOOP_1_HEADER]] ], [ [[SUB93:%.*]], %[[LOOP_2]] ]254; CHECK-NEXT: [[TMP1:%.*]] = mul nuw nsw i32 [[IV_3]], -1255; CHECK-NEXT: [[SUB93]] = add i32 [[IV_3]], 1256; CHECK-NEXT: [[ADD101]] = add i32 [[IV_3]], [[IV_2]]257; CHECK-NEXT: [[INDUCTION_IV_NEXT]] = add i32 [[INDUCTION_IV]], [[TMP1]]258; CHECK-NEXT: br i1 false, label %[[LOOP_2]], label %[[LOOP_3_PREHEADER:.*]]259; CHECK: [[LOOP_3_PREHEADER]]:260; CHECK-NEXT: [[INDUCTION_IV_LCSSA:%.*]] = phi i32 [ [[INDUCTION_IV]], %[[LOOP_2]] ]261; CHECK-NEXT: [[IV_2_LCSSA:%.*]] = phi i32 [ [[IV_2]], %[[LOOP_2]] ]262; CHECK-NEXT: br label %[[VECTOR_PH:.*]]263; CHECK: [[VECTOR_PH]]:264; CHECK-NEXT: [[IND_END:%.*]] = mul i32 196, [[INDUCTION_IV_LCSSA]]265; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[INDUCTION_IV_LCSSA]], i64 0266; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer267; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[BROADCAST_SPLAT]]268; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> zeroinitializer, [[TMP3]]269; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[INDUCTION_IV_LCSSA]], 4270; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i64 0271; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT1]], <4 x i32> poison, <4 x i32> zeroinitializer272; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]273; CHECK: [[VECTOR_BODY]]:274; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]275; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]276; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16277; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[DST]], i16 [[OFFSET_IDX]]278; CHECK-NEXT: store <4 x i32> [[VEC_IND]], ptr [[TMP5]], align 4279; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4280; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]281; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], 196282; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]283; CHECK: [[MIDDLE_BLOCK]]:284; CHECK-NEXT: br label %[[SCALAR_PH:.*]]285; CHECK: [[SCALAR_PH]]:286; CHECK-NEXT: br label %[[LOOP_3:.*]]287; CHECK: [[LOOP_3]]:288; CHECK-NEXT: [[IV_4:%.*]] = phi i16 [ [[INC_1:%.*]], %[[LOOP_3]] ], [ 196, %[[SCALAR_PH]] ]289; CHECK-NEXT: [[IV_5:%.*]] = phi i32 [ [[SUB93_1:%.*]], %[[LOOP_3]] ], [ [[IND_END]], %[[SCALAR_PH]] ]290; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i32, ptr [[DST]], i16 [[IV_4]]291; CHECK-NEXT: store i32 [[IV_5]], ptr [[GEP_DST]], align 4292; CHECK-NEXT: [[SUB93_1]] = sub i32 [[IV_5]], [[IV_2_LCSSA]]293; CHECK-NEXT: [[INC_1]] = add i16 [[IV_4]], 1294; CHECK-NEXT: [[CMP88_1:%.*]] = icmp ult i16 [[IV_4]], 198295; CHECK-NEXT: br i1 [[CMP88_1]], label %[[LOOP_3]], label %[[LOOP_4_PREHEADER:.*]], !llvm.loop [[LOOP5:![0-9]+]]296; CHECK: [[LOOP_4_PREHEADER]]:297; CHECK-NEXT: [[IV_5_LCSSA:%.*]] = phi i32 [ [[IV_5]], %[[LOOP_3]] ]298; CHECK-NEXT: br label %[[LOOP_4]]299; CHECK: [[LOOP_4]]:300; CHECK-NEXT: [[IV_6:%.*]] = phi i32 [ [[SUB93_2]], %[[LOOP_4]] ], [ 0, %[[LOOP_4_PREHEADER]] ]301; CHECK-NEXT: [[SUB93_2]] = sub i32 [[IV_6]], [[IV_5_LCSSA]]302; CHECK-NEXT: br i1 false, label %[[LOOP_4]], label %[[LOOP_1_HEADER_LOOPEXIT]]303;304entry:305 br label %loop.1.header306 307loop.1.header:308 %p.1 = phi i32 [ 0, %entry ], [ %sub93.2, %loop.4 ]309 br label %loop.2310 311loop.2:312 %iv.2 = phi i32 [ %p.1, %loop.1.header ], [ %add101, %loop.2 ]313 %iv.3 = phi i32 [ 0, %loop.1.header ], [ %sub93, %loop.2 ]314 %sub93 = add i32 %iv.3, 1315 %add101 = add i32 %iv.3, %iv.2316 br i1 false, label %loop.2, label %loop.3317 318loop.3:319 %iv.4 = phi i16 [ 0, %loop.2 ], [ %inc.1, %loop.3 ]320 %iv.5 = phi i32 [ 0, %loop.2 ], [ %sub93.1, %loop.3 ]321 %gep.dst = getelementptr inbounds i32, ptr %dst, i16 %iv.4322 store i32 %iv.5, ptr %gep.dst323 %sub93.1 = sub i32 %iv.5, %iv.2324 %inc.1 = add i16 %iv.4, 1325 %cmp88.1 = icmp ult i16 %iv.4, 198326 br i1 %cmp88.1, label %loop.3, label %loop.4327 328loop.4:329 %iv.6 = phi i32 [ 0, %loop.3 ], [ %sub93.2, %loop.4 ]330 %sub93.2 = sub i32 %iv.6, %iv.5331 br i1 false, label %loop.4, label %loop.1.header332}333 334define void @test3_pr58811(ptr %dst) {335; VF2-LABEL: define void @test3_pr58811(336; VF2-SAME: ptr [[DST:%.*]]) {337; VF2-NEXT: [[ENTRY:.*]]:338; VF2-NEXT: br label %[[LOOP_1_HEADER:.*]]339; VF2: [[LOOP_1_HEADER]]:340; VF2-NEXT: [[P_1:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUB93_2:%.*]], %[[LOOP_1_LATCH:.*]] ]341; VF2-NEXT: [[REM85:%.*]] = urem i32 1, [[P_1]]342; VF2-NEXT: br label %[[LOOP_2:.*]]343; VF2: [[LOOP_2]]:344; VF2-NEXT: [[P_2:%.*]] = phi i32 [ 1, %[[LOOP_1_HEADER]] ], [ 0, %[[LOOP_2]] ]345; VF2-NEXT: [[ADD101:%.*]] = add i32 [[REM85]], [[P_2]]346; VF2-NEXT: br i1 false, label %[[LOOP_2]], label %[[LOOP_3_PREHEADER:.*]]347; VF2: [[LOOP_3_PREHEADER]]:348; VF2-NEXT: [[ADD101_LCSSA:%.*]] = phi i32 [ [[ADD101]], %[[LOOP_2]] ]349; VF2-NEXT: [[TMP0:%.*]] = udiv i32 1, [[P_1]]350; VF2-NEXT: [[TMP1:%.*]] = mul nuw i32 [[P_1]], [[TMP0]]351; VF2-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -1352; VF2-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[P_2]]353; VF2-NEXT: br label %[[VECTOR_PH:.*]]354; VF2: [[VECTOR_PH]]:355; VF2-NEXT: [[TMP15:%.*]] = mul i32 198, [[TMP3]]356; VF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[TMP3]], i64 0357; VF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer358; VF2-NEXT: [[TMP5:%.*]] = mul <2 x i32> <i32 0, i32 1>, [[BROADCAST_SPLAT]]359; VF2-NEXT: [[INDUCTION:%.*]] = add <2 x i32> zeroinitializer, [[TMP5]]360; VF2-NEXT: [[TMP6:%.*]] = mul i32 [[TMP3]], 2361; VF2-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <2 x i32> poison, i32 [[TMP6]], i64 0362; VF2-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT1]], <2 x i32> poison, <2 x i32> zeroinitializer363; VF2-NEXT: br label %[[VECTOR_BODY:.*]]364; VF2: [[VECTOR_BODY]]:365; VF2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]366; VF2-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]367; VF2-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16368; VF2-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[DST]], i16 [[OFFSET_IDX]]369; VF2-NEXT: store <2 x i32> [[VEC_IND]], ptr [[TMP7]], align 4370; VF2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2371; VF2-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]372; VF2-NEXT: [[TMP22:%.*]] = icmp eq i32 [[INDEX_NEXT]], 198373; VF2-NEXT: br i1 [[TMP22]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]374; VF2: [[MIDDLE_BLOCK]]:375; VF2-NEXT: br label %[[SCALAR_PH:.*]]376; VF2: [[SCALAR_PH]]:377; VF2-NEXT: br label %[[LOOP_3:.*]]378; VF2: [[LOOP_3]]:379; VF2-NEXT: [[IV_3:%.*]] = phi i16 [ [[INC_1:%.*]], %[[LOOP_3]] ], [ 198, %[[SCALAR_PH]] ]380; VF2-NEXT: [[IV_4:%.*]] = phi i32 [ [[SUB93_1:%.*]], %[[LOOP_3]] ], [ [[TMP15]], %[[SCALAR_PH]] ]381; VF2-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i32, ptr [[DST]], i16 [[IV_3]]382; VF2-NEXT: store i32 [[IV_4]], ptr [[GEP_DST]], align 4383; VF2-NEXT: [[SUB93_1]] = sub i32 [[IV_4]], [[ADD101_LCSSA]]384; VF2-NEXT: [[INC_1]] = add i16 [[IV_3]], 1385; VF2-NEXT: [[CMP88_1:%.*]] = icmp ult i16 [[IV_3]], 198386; VF2-NEXT: br i1 [[CMP88_1]], label %[[LOOP_3]], label %[[LOOP_4_PREHEADER:.*]], !llvm.loop [[LOOP7:![0-9]+]]387; VF2: [[LOOP_4_PREHEADER]]:388; VF2-NEXT: [[IV_4_LCSSA:%.*]] = phi i32 [ [[IV_4]], %[[LOOP_3]] ]389; VF2-NEXT: br label %[[LOOP_4:.*]]390; VF2: [[LOOP_4]]:391; VF2-NEXT: [[IV_5:%.*]] = phi i32 [ [[SUB93_2]], %[[LOOP_4]] ], [ 0, %[[LOOP_4_PREHEADER]] ]392; VF2-NEXT: [[SUB93_2]] = sub i32 [[IV_5]], [[IV_4_LCSSA]]393; VF2-NEXT: br label %[[LOOP_4]]394; VF2: [[LOOP_1_LATCH]]:395; VF2-NEXT: br label %[[LOOP_1_HEADER]]396;397; CHECK-LABEL: define void @test3_pr58811(398; CHECK-SAME: ptr [[DST:%.*]]) {399; CHECK-NEXT: [[ENTRY:.*]]:400; CHECK-NEXT: br label %[[LOOP_1_HEADER:.*]]401; CHECK: [[LOOP_1_HEADER]]:402; CHECK-NEXT: [[P_1:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUB93_2:%.*]], %[[LOOP_1_LATCH:.*]] ]403; CHECK-NEXT: [[REM85:%.*]] = urem i32 1, [[P_1]]404; CHECK-NEXT: br label %[[LOOP_2:.*]]405; CHECK: [[LOOP_2]]:406; CHECK-NEXT: [[P_2:%.*]] = phi i32 [ 1, %[[LOOP_1_HEADER]] ], [ 0, %[[LOOP_2]] ]407; CHECK-NEXT: [[ADD101:%.*]] = add i32 [[REM85]], [[P_2]]408; CHECK-NEXT: br i1 false, label %[[LOOP_2]], label %[[LOOP_3_PREHEADER:.*]]409; CHECK: [[LOOP_3_PREHEADER]]:410; CHECK-NEXT: [[ADD101_LCSSA:%.*]] = phi i32 [ [[ADD101]], %[[LOOP_2]] ]411; CHECK-NEXT: [[TMP0:%.*]] = udiv i32 1, [[P_1]]412; CHECK-NEXT: [[TMP1:%.*]] = mul nuw i32 [[P_1]], [[TMP0]]413; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -1414; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[P_2]]415; CHECK-NEXT: br label %[[VECTOR_PH:.*]]416; CHECK: [[VECTOR_PH]]:417; CHECK-NEXT: [[IND_END:%.*]] = mul i32 196, [[TMP3]]418; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[TMP3]], i64 0419; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer420; CHECK-NEXT: [[TMP5:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[BROADCAST_SPLAT]]421; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> zeroinitializer, [[TMP5]]422; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP3]], 4423; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP6]], i64 0424; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT1]], <4 x i32> poison, <4 x i32> zeroinitializer425; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]426; CHECK: [[VECTOR_BODY]]:427; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]428; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]429; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16430; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[DST]], i16 [[OFFSET_IDX]]431; CHECK-NEXT: store <4 x i32> [[VEC_IND]], ptr [[TMP7]], align 4432; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4433; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]434; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 196435; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]436; CHECK: [[MIDDLE_BLOCK]]:437; CHECK-NEXT: br label %[[SCALAR_PH:.*]]438; CHECK: [[SCALAR_PH]]:439; CHECK-NEXT: br label %[[LOOP_3:.*]]440; CHECK: [[LOOP_3]]:441; CHECK-NEXT: [[IV_3:%.*]] = phi i16 [ [[INC_1:%.*]], %[[LOOP_3]] ], [ 196, %[[SCALAR_PH]] ]442; CHECK-NEXT: [[IV_4:%.*]] = phi i32 [ [[SUB93_1:%.*]], %[[LOOP_3]] ], [ [[IND_END]], %[[SCALAR_PH]] ]443; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i32, ptr [[DST]], i16 [[IV_3]]444; CHECK-NEXT: store i32 [[IV_4]], ptr [[GEP_DST]], align 4445; CHECK-NEXT: [[SUB93_1]] = sub i32 [[IV_4]], [[ADD101_LCSSA]]446; CHECK-NEXT: [[INC_1]] = add i16 [[IV_3]], 1447; CHECK-NEXT: [[CMP88_1:%.*]] = icmp ult i16 [[IV_3]], 198448; CHECK-NEXT: br i1 [[CMP88_1]], label %[[LOOP_3]], label %[[LOOP_4_PREHEADER:.*]], !llvm.loop [[LOOP7:![0-9]+]]449; CHECK: [[LOOP_4_PREHEADER]]:450; CHECK-NEXT: [[IV_4_LCSSA:%.*]] = phi i32 [ [[IV_4]], %[[LOOP_3]] ]451; CHECK-NEXT: br label %[[LOOP_4:.*]]452; CHECK: [[LOOP_4]]:453; CHECK-NEXT: [[IV_5:%.*]] = phi i32 [ [[SUB93_2]], %[[LOOP_4]] ], [ 0, %[[LOOP_4_PREHEADER]] ]454; CHECK-NEXT: [[SUB93_2]] = sub i32 [[IV_5]], [[IV_4_LCSSA]]455; CHECK-NEXT: br label %[[LOOP_4]]456; CHECK: [[LOOP_1_LATCH]]:457; CHECK-NEXT: br label %[[LOOP_1_HEADER]]458;459entry:460 br label %loop.1.header461 462loop.1.header:463 %p.1 = phi i32 [ 0, %entry ], [ %sub93.2, %loop.1.latch ]464 %rem85 = urem i32 1, %p.1465 br label %loop.2466 467loop.2:468 %p.2 = phi i32 [ 1, %loop.1.header ], [ 0, %loop.2 ]469 %add101 = add i32 %rem85, %p.2470 br i1 false, label %loop.2, label %loop.3471 472loop.3:473 %iv.3 = phi i16 [ 0, %loop.2 ], [ %inc.1, %loop.3 ]474 %iv.4 = phi i32 [ 0, %loop.2 ], [ %sub93.1, %loop.3 ]475 %gep.dst = getelementptr inbounds i32, ptr %dst, i16 %iv.3476 store i32 %iv.4, ptr %gep.dst477 %sub93.1 = sub i32 %iv.4, %add101478 %inc.1 = add i16 %iv.3, 1479 %cmp88.1 = icmp ult i16 %iv.3, 198480 br i1 %cmp88.1, label %loop.3, label %loop.4481 482loop.4:483 %iv.5 = phi i32 [ 0, %loop.3 ], [ %sub93.2, %loop.4 ]484 %sub93.2 = sub i32 %iv.5, %iv.4485 br label %loop.4486 487loop.1.latch: ; No predecessors!488 br label %loop.1.header489}490 491define void @iv_start_from_shl_of_previous_iv(ptr %dst) {492; VF2-LABEL: define void @iv_start_from_shl_of_previous_iv(493; VF2-SAME: ptr [[DST:%.*]]) {494; VF2-NEXT: [[ENTRY:.*:]]495; VF2-NEXT: br label %[[VECTOR_PH:.*]]496; VF2: [[VECTOR_PH]]:497; VF2-NEXT: br label %[[VECTOR_BODY:.*]]498; VF2: [[VECTOR_BODY]]:499; VF2-NEXT: store <2 x i8> zeroinitializer, ptr [[DST]], align 1500; VF2-NEXT: br label %[[MIDDLE_BLOCK:.*]]501; VF2: [[MIDDLE_BLOCK]]:502; VF2-NEXT: br label %[[LOOP_1_EXIT:.*]]503; VF2: [[LOOP_1_EXIT]]:504; VF2-NEXT: [[IV_1_SHL:%.*]] = shl i64 1, 1505; VF2-NEXT: br label %[[VECTOR_PH1:.*]]506; VF2: [[VECTOR_PH1]]:507; VF2-NEXT: [[TMP0:%.*]] = add i64 [[IV_1_SHL]], 98508; VF2-NEXT: br label %[[VECTOR_BODY2:.*]]509; VF2: [[VECTOR_BODY2]]:510; VF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY2]] ]511; VF2-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[IV_1_SHL]], [[INDEX]]512; VF2-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[DST]], i64 [[OFFSET_IDX]]513; VF2-NEXT: store <2 x i8> splat (i8 1), ptr [[TMP1]], align 1514; VF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2515; VF2-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 98516; VF2-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK3:.*]], label %[[VECTOR_BODY2]], !llvm.loop [[LOOP8:![0-9]+]]517; VF2: [[MIDDLE_BLOCK3]]:518; VF2-NEXT: br label %[[SCALAR_PH:.*]]519; VF2: [[SCALAR_PH]]:520; VF2-NEXT: br label %[[LOOP_2:.*]]521; VF2: [[LOOP_2]]:522; VF2-NEXT: [[IV_2:%.*]] = phi i64 [ [[TMP0]], %[[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP_2]] ]523; VF2-NEXT: [[GEP_2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV_2]]524; VF2-NEXT: store i8 1, ptr [[GEP_2]], align 1525; VF2-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], 1526; VF2-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[IV_2]], 100527; VF2-NEXT: br i1 [[CMP_2]], label %[[EXIT:.*]], label %[[LOOP_2]], !llvm.loop [[LOOP9:![0-9]+]]528; VF2: [[EXIT]]:529; VF2-NEXT: ret void530;531; CHECK-LABEL: define void @iv_start_from_shl_of_previous_iv(532; CHECK-SAME: ptr [[DST:%.*]]) {533; CHECK-NEXT: [[ENTRY:.*]]:534; CHECK-NEXT: br label %[[LOOP_1:.*]]535; CHECK: [[LOOP_1]]:536; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP_1]] ]537; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV_1]]538; CHECK-NEXT: store i8 0, ptr [[GEP_1]], align 1539; CHECK-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], 1540; CHECK-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[IV_1]], 0541; CHECK-NEXT: br i1 [[CMP_1]], label %[[LOOP_1]], label %[[LOOP_1_EXIT:.*]]542; CHECK: [[LOOP_1_EXIT]]:543; CHECK-NEXT: [[IV_1_LCSSA:%.*]] = phi i64 [ [[IV_1]], %[[LOOP_1]] ]544; CHECK-NEXT: [[IV_1_SHL:%.*]] = shl i64 [[IV_1_LCSSA]], 1545; CHECK-NEXT: br label %[[VECTOR_PH:.*]]546; CHECK: [[VECTOR_PH]]:547; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[IV_1_SHL]], 96548; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]549; CHECK: [[VECTOR_BODY]]:550; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]551; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[IV_1_SHL]], [[INDEX]]552; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[DST]], i64 [[OFFSET_IDX]]553; CHECK-NEXT: store <4 x i8> splat (i8 1), ptr [[TMP0]], align 1554; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4555; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96556; CHECK-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]557; CHECK: [[MIDDLE_BLOCK]]:558; CHECK-NEXT: br label %[[SCALAR_PH:.*]]559; CHECK: [[SCALAR_PH]]:560; CHECK-NEXT: br label %[[LOOP_2:.*]]561; CHECK: [[LOOP_2]]:562; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[TMP2]], %[[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP_2]] ]563; CHECK-NEXT: [[GEP_2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV_2]]564; CHECK-NEXT: store i8 1, ptr [[GEP_2]], align 1565; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], 1566; CHECK-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[IV_2]], 100567; CHECK-NEXT: br i1 [[CMP_2]], label %[[EXIT:.*]], label %[[LOOP_2]], !llvm.loop [[LOOP9:![0-9]+]]568; CHECK: [[EXIT]]:569; CHECK-NEXT: ret void570;571entry:572 br label %loop.1573 574loop.1:575 %iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop.1 ]576 %gep.1 = getelementptr i8, ptr %dst, i64 %iv.1577 store i8 0, ptr %gep.1, align 1578 %iv.1.next = add i64 %iv.1, 1579 %cmp.1 = icmp eq i64 %iv.1, 0580 br i1 %cmp.1, label %loop.1, label %loop.1.exit581 582loop.1.exit:583 %iv.1.shl = shl i64 %iv.1, 1584 br label %loop.2585 586loop.2:587 %iv.2 = phi i64 [ %iv.1.shl, %loop.1.exit ], [ %iv.2.next, %loop.2 ]588 %gep.2 = getelementptr i8, ptr %dst, i64 %iv.2589 store i8 1, ptr %gep.2, align 1590 %iv.2.next = add i64 %iv.2, 1591 %cmp.2 = icmp eq i64 %iv.2, 100592 br i1 %cmp.2, label %exit, label %loop.2593 594exit:595 ret void596}597