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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=IC1 %s3; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=2 -S %s | FileCheck --check-prefixes=IC2 %s4 5define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {6; IC1-LABEL: define void @switch4_default_common_dest_with_case(7; IC1-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {8; IC1-NEXT: [[ENTRY:.*]]:9; IC1-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i6410; IC1-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i6411; IC1-NEXT: [[TMP0:%.*]] = sub i64 [[END1]], [[START2]]12; IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 213; IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]14; IC1: [[VECTOR_PH]]:15; IC1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 216; IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]17; IC1-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[N_VEC]]18; IC1-NEXT: br label %[[VECTOR_BODY:.*]]19; IC1: [[VECTOR_BODY]]:20; IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE13:.*]] ]21; IC1-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 022; IC1-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 123; IC1-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP1]]24; IC1-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP2]]25; IC1-NEXT: [[TMP12:%.*]] = insertelement <2 x ptr> poison, ptr [[NEXT_GEP]], i32 026; IC1-NEXT: [[TMP16:%.*]] = insertelement <2 x ptr> [[TMP12]], ptr [[NEXT_GEP3]], i32 127; IC1-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[NEXT_GEP]], align 128; IC1-NEXT: [[TMP7:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD]], splat (i8 -12)29; IC1-NEXT: [[TMP4:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD]], splat (i8 13)30; IC1-NEXT: [[TMP11:%.*]] = or <2 x i1> [[TMP7]], [[TMP4]]31; IC1-NEXT: [[TMP10:%.*]] = xor <2 x i1> [[TMP11]], splat (i1 true)32; IC1-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP4]], i32 033; IC1-NEXT: br i1 [[TMP5]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]34; IC1: [[PRED_STORE_IF]]:35; IC1-NEXT: store i8 0, ptr [[NEXT_GEP]], align 136; IC1-NEXT: br label %[[PRED_STORE_CONTINUE]]37; IC1: [[PRED_STORE_CONTINUE]]:38; IC1-NEXT: [[TMP6:%.*]] = extractelement <2 x i1> [[TMP4]], i32 139; IC1-NEXT: br i1 [[TMP6]], label %[[PRED_STORE_IF4:.*]], label %[[PRED_STORE_CONTINUE5:.*]]40; IC1: [[PRED_STORE_IF4]]:41; IC1-NEXT: store i8 0, ptr [[NEXT_GEP3]], align 142; IC1-NEXT: br label %[[PRED_STORE_CONTINUE5]]43; IC1: [[PRED_STORE_CONTINUE5]]:44; IC1-NEXT: [[TMP8:%.*]] = extractelement <2 x i1> [[TMP7]], i32 045; IC1-NEXT: br i1 [[TMP8]], label %[[PRED_STORE_IF6:.*]], label %[[PRED_STORE_CONTINUE7:.*]]46; IC1: [[PRED_STORE_IF6]]:47; IC1-NEXT: store i8 42, ptr [[NEXT_GEP]], align 148; IC1-NEXT: br label %[[PRED_STORE_CONTINUE7]]49; IC1: [[PRED_STORE_CONTINUE7]]:50; IC1-NEXT: [[TMP9:%.*]] = extractelement <2 x i1> [[TMP7]], i32 151; IC1-NEXT: br i1 [[TMP9]], label %[[PRED_STORE_IF8:.*]], label %[[PRED_STORE_CONTINUE9:.*]]52; IC1: [[PRED_STORE_IF8]]:53; IC1-NEXT: store i8 42, ptr [[NEXT_GEP3]], align 154; IC1-NEXT: br label %[[PRED_STORE_CONTINUE9]]55; IC1: [[PRED_STORE_CONTINUE9]]:56; IC1-NEXT: [[TMP13:%.*]] = extractelement <2 x i1> [[TMP10]], i32 057; IC1-NEXT: br i1 [[TMP13]], label %[[PRED_STORE_IF10:.*]], label %[[PRED_STORE_CONTINUE11:.*]]58; IC1: [[PRED_STORE_IF10]]:59; IC1-NEXT: store i8 2, ptr [[NEXT_GEP]], align 160; IC1-NEXT: br label %[[PRED_STORE_CONTINUE11]]61; IC1: [[PRED_STORE_CONTINUE11]]:62; IC1-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP10]], i32 163; IC1-NEXT: br i1 [[TMP14]], label %[[PRED_STORE_IF12:.*]], label %[[PRED_STORE_CONTINUE13]]64; IC1: [[PRED_STORE_IF12]]:65; IC1-NEXT: store i8 2, ptr [[NEXT_GEP3]], align 166; IC1-NEXT: br label %[[PRED_STORE_CONTINUE13]]67; IC1: [[PRED_STORE_CONTINUE13]]:68; IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 269; IC1-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]70; IC1-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]71; IC1: [[MIDDLE_BLOCK]]:72; IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]73; IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]74; IC1: [[SCALAR_PH]]:75; IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]76; IC1-NEXT: br label %[[LOOP_HEADER:.*]]77; IC1: [[LOOP_HEADER]]:78; IC1-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]79; IC1-NEXT: [[L:%.*]] = load i8, ptr [[PTR_IV]], align 180; IC1-NEXT: switch i8 [[L]], label %[[DEFAULT:.*]] [81; IC1-NEXT: i8 -12, label %[[IF_THEN_1:.*]]82; IC1-NEXT: i8 13, label %[[IF_THEN_2:.*]]83; IC1-NEXT: i8 0, label %[[DEFAULT]]84; IC1-NEXT: ]85; IC1: [[IF_THEN_1]]:86; IC1-NEXT: store i8 42, ptr [[PTR_IV]], align 187; IC1-NEXT: br label %[[LOOP_LATCH]]88; IC1: [[IF_THEN_2]]:89; IC1-NEXT: store i8 0, ptr [[PTR_IV]], align 190; IC1-NEXT: br label %[[LOOP_LATCH]]91; IC1: [[DEFAULT]]:92; IC1-NEXT: store i8 2, ptr [[PTR_IV]], align 193; IC1-NEXT: br label %[[LOOP_LATCH]]94; IC1: [[LOOP_LATCH]]:95; IC1-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i8, ptr [[PTR_IV]], i64 196; IC1-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]97; IC1-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]98; IC1: [[EXIT]]:99; IC1-NEXT: ret void100;101; IC2-LABEL: define void @switch4_default_common_dest_with_case(102; IC2-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {103; IC2-NEXT: [[ENTRY:.*]]:104; IC2-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64105; IC2-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64106; IC2-NEXT: [[TMP0:%.*]] = sub i64 [[END1]], [[START2]]107; IC2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4108; IC2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]109; IC2: [[VECTOR_PH]]:110; IC2-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 4111; IC2-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]112; IC2-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[N_VEC]]113; IC2-NEXT: br label %[[VECTOR_BODY:.*]]114; IC2: [[VECTOR_BODY]]:115; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE28:.*]] ]116; IC2-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 0117; IC2-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 1118; IC2-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 2119; IC2-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 3120; IC2-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP1]]121; IC2-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP2]]122; IC2-NEXT: [[TMP23:%.*]] = insertelement <2 x ptr> poison, ptr [[NEXT_GEP]], i32 0123; IC2-NEXT: [[TMP24:%.*]] = insertelement <2 x ptr> [[TMP23]], ptr [[NEXT_GEP3]], i32 1124; IC2-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP3]]125; IC2-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]126; IC2-NEXT: [[TMP30:%.*]] = insertelement <2 x ptr> poison, ptr [[NEXT_GEP4]], i32 0127; IC2-NEXT: [[TMP31:%.*]] = insertelement <2 x ptr> [[TMP30]], ptr [[NEXT_GEP5]], i32 1128; IC2-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 2129; IC2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[NEXT_GEP]], align 1130; IC2-NEXT: [[WIDE_LOAD6:%.*]] = load <2 x i8>, ptr [[TMP6]], align 1131; IC2-NEXT: [[TMP13:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD]], splat (i8 -12)132; IC2-NEXT: [[TMP14:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD6]], splat (i8 -12)133; IC2-NEXT: [[TMP7:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD]], splat (i8 13)134; IC2-NEXT: [[TMP8:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD6]], splat (i8 13)135; IC2-NEXT: [[TMP21:%.*]] = or <2 x i1> [[TMP13]], [[TMP7]]136; IC2-NEXT: [[TMP22:%.*]] = or <2 x i1> [[TMP14]], [[TMP8]]137; IC2-NEXT: [[TMP19:%.*]] = xor <2 x i1> [[TMP21]], splat (i1 true)138; IC2-NEXT: [[TMP20:%.*]] = xor <2 x i1> [[TMP22]], splat (i1 true)139; IC2-NEXT: [[TMP9:%.*]] = extractelement <2 x i1> [[TMP7]], i32 0140; IC2-NEXT: br i1 [[TMP9]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]141; IC2: [[PRED_STORE_IF]]:142; IC2-NEXT: store i8 0, ptr [[NEXT_GEP]], align 1143; IC2-NEXT: br label %[[PRED_STORE_CONTINUE]]144; IC2: [[PRED_STORE_CONTINUE]]:145; IC2-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP7]], i32 1146; IC2-NEXT: br i1 [[TMP10]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]147; IC2: [[PRED_STORE_IF7]]:148; IC2-NEXT: store i8 0, ptr [[NEXT_GEP3]], align 1149; IC2-NEXT: br label %[[PRED_STORE_CONTINUE8]]150; IC2: [[PRED_STORE_CONTINUE8]]:151; IC2-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP8]], i32 0152; IC2-NEXT: br i1 [[TMP11]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]153; IC2: [[PRED_STORE_IF9]]:154; IC2-NEXT: store i8 0, ptr [[NEXT_GEP4]], align 1155; IC2-NEXT: br label %[[PRED_STORE_CONTINUE10]]156; IC2: [[PRED_STORE_CONTINUE10]]:157; IC2-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP8]], i32 1158; IC2-NEXT: br i1 [[TMP12]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]159; IC2: [[PRED_STORE_IF11]]:160; IC2-NEXT: store i8 0, ptr [[NEXT_GEP5]], align 1161; IC2-NEXT: br label %[[PRED_STORE_CONTINUE12]]162; IC2: [[PRED_STORE_CONTINUE12]]:163; IC2-NEXT: [[TMP15:%.*]] = extractelement <2 x i1> [[TMP13]], i32 0164; IC2-NEXT: br i1 [[TMP15]], label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14:.*]]165; IC2: [[PRED_STORE_IF13]]:166; IC2-NEXT: store i8 42, ptr [[NEXT_GEP]], align 1167; IC2-NEXT: br label %[[PRED_STORE_CONTINUE14]]168; IC2: [[PRED_STORE_CONTINUE14]]:169; IC2-NEXT: [[TMP16:%.*]] = extractelement <2 x i1> [[TMP13]], i32 1170; IC2-NEXT: br i1 [[TMP16]], label %[[PRED_STORE_IF15:.*]], label %[[PRED_STORE_CONTINUE16:.*]]171; IC2: [[PRED_STORE_IF15]]:172; IC2-NEXT: store i8 42, ptr [[NEXT_GEP3]], align 1173; IC2-NEXT: br label %[[PRED_STORE_CONTINUE16]]174; IC2: [[PRED_STORE_CONTINUE16]]:175; IC2-NEXT: [[TMP17:%.*]] = extractelement <2 x i1> [[TMP14]], i32 0176; IC2-NEXT: br i1 [[TMP17]], label %[[PRED_STORE_IF17:.*]], label %[[PRED_STORE_CONTINUE18:.*]]177; IC2: [[PRED_STORE_IF17]]:178; IC2-NEXT: store i8 42, ptr [[NEXT_GEP4]], align 1179; IC2-NEXT: br label %[[PRED_STORE_CONTINUE18]]180; IC2: [[PRED_STORE_CONTINUE18]]:181; IC2-NEXT: [[TMP18:%.*]] = extractelement <2 x i1> [[TMP14]], i32 1182; IC2-NEXT: br i1 [[TMP18]], label %[[PRED_STORE_IF19:.*]], label %[[PRED_STORE_CONTINUE20:.*]]183; IC2: [[PRED_STORE_IF19]]:184; IC2-NEXT: store i8 42, ptr [[NEXT_GEP5]], align 1185; IC2-NEXT: br label %[[PRED_STORE_CONTINUE20]]186; IC2: [[PRED_STORE_CONTINUE20]]:187; IC2-NEXT: [[TMP25:%.*]] = extractelement <2 x i1> [[TMP19]], i32 0188; IC2-NEXT: br i1 [[TMP25]], label %[[PRED_STORE_IF21:.*]], label %[[PRED_STORE_CONTINUE22:.*]]189; IC2: [[PRED_STORE_IF21]]:190; IC2-NEXT: store i8 2, ptr [[NEXT_GEP]], align 1191; IC2-NEXT: br label %[[PRED_STORE_CONTINUE22]]192; IC2: [[PRED_STORE_CONTINUE22]]:193; IC2-NEXT: [[TMP26:%.*]] = extractelement <2 x i1> [[TMP19]], i32 1194; IC2-NEXT: br i1 [[TMP26]], label %[[PRED_STORE_IF23:.*]], label %[[PRED_STORE_CONTINUE24:.*]]195; IC2: [[PRED_STORE_IF23]]:196; IC2-NEXT: store i8 2, ptr [[NEXT_GEP3]], align 1197; IC2-NEXT: br label %[[PRED_STORE_CONTINUE24]]198; IC2: [[PRED_STORE_CONTINUE24]]:199; IC2-NEXT: [[TMP27:%.*]] = extractelement <2 x i1> [[TMP20]], i32 0200; IC2-NEXT: br i1 [[TMP27]], label %[[PRED_STORE_IF25:.*]], label %[[PRED_STORE_CONTINUE26:.*]]201; IC2: [[PRED_STORE_IF25]]:202; IC2-NEXT: store i8 2, ptr [[NEXT_GEP4]], align 1203; IC2-NEXT: br label %[[PRED_STORE_CONTINUE26]]204; IC2: [[PRED_STORE_CONTINUE26]]:205; IC2-NEXT: [[TMP28:%.*]] = extractelement <2 x i1> [[TMP20]], i32 1206; IC2-NEXT: br i1 [[TMP28]], label %[[PRED_STORE_IF27:.*]], label %[[PRED_STORE_CONTINUE28]]207; IC2: [[PRED_STORE_IF27]]:208; IC2-NEXT: store i8 2, ptr [[NEXT_GEP5]], align 1209; IC2-NEXT: br label %[[PRED_STORE_CONTINUE28]]210; IC2: [[PRED_STORE_CONTINUE28]]:211; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4212; IC2-NEXT: [[TMP29:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]213; IC2-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]214; IC2: [[MIDDLE_BLOCK]]:215; IC2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]216; IC2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]217; IC2: [[SCALAR_PH]]:218; IC2-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]219; IC2-NEXT: br label %[[LOOP_HEADER:.*]]220; IC2: [[LOOP_HEADER]]:221; IC2-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]222; IC2-NEXT: [[L:%.*]] = load i8, ptr [[PTR_IV]], align 1223; IC2-NEXT: switch i8 [[L]], label %[[DEFAULT:.*]] [224; IC2-NEXT: i8 -12, label %[[IF_THEN_1:.*]]225; IC2-NEXT: i8 13, label %[[IF_THEN_2:.*]]226; IC2-NEXT: i8 0, label %[[DEFAULT]]227; IC2-NEXT: ]228; IC2: [[IF_THEN_1]]:229; IC2-NEXT: store i8 42, ptr [[PTR_IV]], align 1230; IC2-NEXT: br label %[[LOOP_LATCH]]231; IC2: [[IF_THEN_2]]:232; IC2-NEXT: store i8 0, ptr [[PTR_IV]], align 1233; IC2-NEXT: br label %[[LOOP_LATCH]]234; IC2: [[DEFAULT]]:235; IC2-NEXT: store i8 2, ptr [[PTR_IV]], align 1236; IC2-NEXT: br label %[[LOOP_LATCH]]237; IC2: [[LOOP_LATCH]]:238; IC2-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i8, ptr [[PTR_IV]], i64 1239; IC2-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]240; IC2-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]241; IC2: [[EXIT]]:242; IC2-NEXT: ret void243;244entry:245 br label %loop.header246 247loop.header:248 %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]249 %l = load i8, ptr %ptr.iv, align 1250 switch i8 %l, label %default [251 i8 -12, label %if.then.1252 i8 13, label %if.then.2253 i8 0, label %default254 ]255 256if.then.1:257 store i8 42, ptr %ptr.iv, align 1258 br label %loop.latch259 260if.then.2:261 store i8 0, ptr %ptr.iv, align 1262 br label %loop.latch263 264default:265 store i8 2, ptr %ptr.iv, align 1266 br label %loop.latch267 268loop.latch:269 %ptr.iv.next = getelementptr inbounds i8, ptr %ptr.iv, i64 1270 %ec = icmp eq ptr %ptr.iv.next, %end271 br i1 %ec, label %exit, label %loop.header272 273exit:274 ret void275}276 277define void @switch_exiting(ptr %start) {278; IC1-LABEL: define void @switch_exiting(279; IC1-SAME: ptr [[START:%.*]]) {280; IC1-NEXT: [[ENTRY:.*]]:281; IC1-NEXT: br label %[[LOOP_HEADER:.*]]282; IC1: [[LOOP_HEADER]]:283; IC1-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]284; IC1-NEXT: switch i64 [[IV]], label %[[LOOP_LATCH]] [285; IC1-NEXT: i64 -12, label %[[IF_THEN:.*]]286; IC1-NEXT: i64 100, label %[[EXIT:.*]]287; IC1-NEXT: ]288; IC1: [[IF_THEN]]:289; IC1-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[START]], i64 [[IV]]290; IC1-NEXT: store i64 42, ptr [[GEP]], align 1291; IC1-NEXT: br label %[[LOOP_LATCH]]292; IC1: [[LOOP_LATCH]]:293; IC1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1294; IC1-NEXT: br label %[[LOOP_HEADER]]295; IC1: [[EXIT]]:296; IC1-NEXT: ret void297;298; IC2-LABEL: define void @switch_exiting(299; IC2-SAME: ptr [[START:%.*]]) {300; IC2-NEXT: [[ENTRY:.*]]:301; IC2-NEXT: br label %[[LOOP_HEADER:.*]]302; IC2: [[LOOP_HEADER]]:303; IC2-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]304; IC2-NEXT: switch i64 [[IV]], label %[[LOOP_LATCH]] [305; IC2-NEXT: i64 -12, label %[[IF_THEN:.*]]306; IC2-NEXT: i64 100, label %[[EXIT:.*]]307; IC2-NEXT: ]308; IC2: [[IF_THEN]]:309; IC2-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[START]], i64 [[IV]]310; IC2-NEXT: store i64 42, ptr [[GEP]], align 1311; IC2-NEXT: br label %[[LOOP_LATCH]]312; IC2: [[LOOP_LATCH]]:313; IC2-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1314; IC2-NEXT: br label %[[LOOP_HEADER]]315; IC2: [[EXIT]]:316; IC2-NEXT: ret void317;318entry:319 br label %loop.header320 321loop.header:322 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]323 switch i64 %iv, label %loop.latch [324 i64 -12, label %if.then325 i64 100, label %exit326 ]327 328if.then:329 %gep = getelementptr inbounds i64, ptr %start, i64 %iv330 store i64 42, ptr %gep, align 1331 br label %loop.latch332 333loop.latch:334 %iv.next = add i64 %iv, 1335 br label %loop.header336 337exit:338 ret void339}340 341define void @switch_to_header(ptr %start) {342; IC1-LABEL: define void @switch_to_header(343; IC1-SAME: ptr [[START:%.*]]) {344; IC1-NEXT: [[ENTRY:.*]]:345; IC1-NEXT: br label %[[LOOP_HEADER:.*]]346; IC1: [[LOOP_HEADER]]:347; IC1-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[IF_THEN:.*]] ]348; IC1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1349; IC1-NEXT: switch i64 [[IV]], label %[[LOOP_LATCH:.*]] [350; IC1-NEXT: i64 120, label %[[IF_THEN]]351; IC1-NEXT: i64 100, label %[[LOOP_LATCH]]352; IC1-NEXT: ]353; IC1: [[IF_THEN]]:354; IC1-NEXT: br label %[[LOOP_HEADER]]355; IC1: [[IF_THEN1:.*:]]356; IC1-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[START]], i64 poison357; IC1-NEXT: store i64 42, ptr [[GEP]], align 1358; IC1-NEXT: unreachable359; IC1: [[LOOP_LATCH]]:360; IC1-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 100361; IC1-NEXT: br i1 [[CMP]], label %[[EXIT:.*]], label %[[IF_THEN]]362; IC1: [[EXIT]]:363; IC1-NEXT: ret void364;365; IC2-LABEL: define void @switch_to_header(366; IC2-SAME: ptr [[START:%.*]]) {367; IC2-NEXT: [[ENTRY:.*]]:368; IC2-NEXT: br label %[[LOOP_HEADER:.*]]369; IC2: [[LOOP_HEADER]]:370; IC2-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[IF_THEN:.*]] ]371; IC2-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1372; IC2-NEXT: switch i64 [[IV]], label %[[LOOP_LATCH:.*]] [373; IC2-NEXT: i64 120, label %[[IF_THEN]]374; IC2-NEXT: i64 100, label %[[LOOP_LATCH]]375; IC2-NEXT: ]376; IC2: [[IF_THEN]]:377; IC2-NEXT: br label %[[LOOP_HEADER]]378; IC2: [[IF_THEN1:.*:]]379; IC2-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[START]], i64 poison380; IC2-NEXT: store i64 42, ptr [[GEP]], align 1381; IC2-NEXT: unreachable382; IC2: [[LOOP_LATCH]]:383; IC2-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 100384; IC2-NEXT: br i1 [[CMP]], label %[[EXIT:.*]], label %[[IF_THEN]]385; IC2: [[EXIT]]:386; IC2-NEXT: ret void387;388entry:389 br label %loop.header390 391loop.header:392 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ], [ %iv.next, %loop.header ]393 %iv.next = add i64 %iv, 1394 switch i64 %iv, label %loop.latch [395 i64 120, label %loop.header396 i64 100, label %loop.latch397 ]398 399if.then:400 %gep = getelementptr inbounds i64, ptr %start, i64 %iv401 store i64 42, ptr %gep, align 1402 br label %loop.latch403 404loop.latch:405 %cmp = icmp eq i64 %iv.next, 100406 br i1 %cmp, label %exit, label %loop.header407 408exit:409 ret void410}411 412define void @switch_all_to_default(ptr %start) {413; IC1-LABEL: define void @switch_all_to_default(414; IC1-SAME: ptr [[START:%.*]]) {415; IC1-NEXT: [[ENTRY:.*:]]416; IC1-NEXT: br label %[[VECTOR_PH:.*]]417; IC1: [[VECTOR_PH]]:418; IC1-NEXT: br label %[[VECTOR_BODY:.*]]419; IC1: [[VECTOR_BODY]]:420; IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]421; IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[START]], i64 [[INDEX]]422; IC1-NEXT: store <2 x i64> splat (i64 42), ptr [[TMP1]], align 1423; IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2424; IC1-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100425; IC1-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]426; IC1: [[MIDDLE_BLOCK]]:427; IC1-NEXT: br label %[[EXIT:.*]]428; IC1: [[EXIT]]:429; IC1-NEXT: ret void430;431; IC2-LABEL: define void @switch_all_to_default(432; IC2-SAME: ptr [[START:%.*]]) {433; IC2-NEXT: [[ENTRY:.*:]]434; IC2-NEXT: br label %[[VECTOR_PH:.*]]435; IC2: [[VECTOR_PH]]:436; IC2-NEXT: br label %[[VECTOR_BODY:.*]]437; IC2: [[VECTOR_BODY]]:438; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]439; IC2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[START]], i64 [[INDEX]]440; IC2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i64 2441; IC2-NEXT: store <2 x i64> splat (i64 42), ptr [[TMP2]], align 1442; IC2-NEXT: store <2 x i64> splat (i64 42), ptr [[TMP5]], align 1443; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4444; IC2-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100445; IC2-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]446; IC2: [[MIDDLE_BLOCK]]:447; IC2-NEXT: br label %[[EXIT:.*]]448; IC2: [[EXIT]]:449; IC2-NEXT: ret void450;451entry:452 br label %loop.header453 454loop.header:455 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]456 %iv.next = add i64 %iv, 1457 switch i64 %iv, label %loop.latch [458 i64 120, label %loop.latch459 i64 100, label %loop.latch460 ]461 462loop.latch:463 %gep = getelementptr inbounds i64, ptr %start, i64 %iv464 store i64 42, ptr %gep, align 1465 %cmp = icmp eq i64 %iv.next, 100466 br i1 %cmp, label %exit, label %loop.header467 468exit:469 ret void470}471 472define void @switch_unconditional(ptr %start) {473; IC1-LABEL: define void @switch_unconditional(474; IC1-SAME: ptr [[START:%.*]]) {475; IC1-NEXT: [[ENTRY:.*:]]476; IC1-NEXT: br label %[[VECTOR_PH:.*]]477; IC1: [[VECTOR_PH]]:478; IC1-NEXT: br label %[[VECTOR_BODY:.*]]479; IC1: [[VECTOR_BODY]]:480; IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]481; IC1-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[START]], i64 [[INDEX]]482; IC1-NEXT: store <2 x i32> zeroinitializer, ptr [[TMP1]], align 4483; IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2484; IC1-NEXT: [[TMP0:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100485; IC1-NEXT: br i1 [[TMP0]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]486; IC1: [[MIDDLE_BLOCK]]:487; IC1-NEXT: br label %[[EXIT:.*]]488; IC1: [[EXIT]]:489; IC1-NEXT: ret void490;491; IC2-LABEL: define void @switch_unconditional(492; IC2-SAME: ptr [[START:%.*]]) {493; IC2-NEXT: [[ENTRY:.*:]]494; IC2-NEXT: br label %[[VECTOR_PH:.*]]495; IC2: [[VECTOR_PH]]:496; IC2-NEXT: br label %[[VECTOR_BODY:.*]]497; IC2: [[VECTOR_BODY]]:498; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]499; IC2-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[START]], i64 [[INDEX]]500; IC2-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[TMP2]], i64 2501; IC2-NEXT: store <2 x i32> zeroinitializer, ptr [[TMP2]], align 4502; IC2-NEXT: store <2 x i32> zeroinitializer, ptr [[TMP1]], align 4503; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4504; IC2-NEXT: [[TMP0:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100505; IC2-NEXT: br i1 [[TMP0]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]506; IC2: [[MIDDLE_BLOCK]]:507; IC2-NEXT: br label %[[EXIT:.*]]508; IC2: [[EXIT]]:509; IC2-NEXT: ret void510;511entry:512 br label %loop513 514loop:515 %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ]516 %gep = getelementptr i32, ptr %start, i64 %iv517 %x = load i32, ptr %gep518 switch i32 %x, label %foo []519 520foo:521 br label %latch522 523latch:524 store i32 0, ptr %gep525 %iv.next = add i64 %iv, 1526 %cmp = icmp eq i64 %iv.next, 100527 br i1 %cmp, label %exit, label %loop528 529exit:530 ret void531}532 533;.534; IC1: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}535; IC1: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}536; IC1: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}537; IC1: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}538; IC1: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}539; IC1: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]}540;.541; IC2: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}542; IC2: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}543; IC2: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}544; IC2: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}545; IC2: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}546; IC2: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]}547;.548