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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -passes=loop-vectorize -force-vector-width=4 -S %s | FileCheck %s3 4define void @loop_invariant_store(ptr %p, i64 %a, i8 %b) {5; CHECK-LABEL: define void @loop_invariant_store(6; CHECK-SAME: ptr [[P:%.*]], i64 [[A:%.*]], i8 [[B:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*:]]8; CHECK-NEXT: br label %[[VECTOR_PH:.*]]9; CHECK: [[VECTOR_PH]]:10; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i64 011; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT]], <4 x i8> poison, <4 x i32> zeroinitializer12; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[A]], 4813; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> poison, i64 [[TMP0]], i64 014; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> poison, <4 x i32> zeroinitializer15; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i64> [[BROADCAST_SPLAT2]], splat (i64 52)16; CHECK-NEXT: [[TMP2:%.*]] = trunc <4 x i64> [[TMP1]] to <4 x i32>17; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT]] to <4 x i32>18; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]19; CHECK: [[VECTOR_BODY]]:20; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE8:.*]] ]21; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE8]] ]22; CHECK-NEXT: [[TMP4:%.*]] = icmp ule <4 x i32> [[VEC_IND]], splat (i32 8)23; CHECK-NEXT: [[TMP5:%.*]] = icmp slt <4 x i32> [[VEC_IND]], splat (i32 2)24; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[TMP3]], <4 x i32> [[TMP2]]25; CHECK-NEXT: [[TMP7:%.*]] = shl <4 x i32> [[PREDPHI]], splat (i32 8)26; CHECK-NEXT: [[TMP8:%.*]] = trunc <4 x i32> [[TMP7]] to <4 x i8>27; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i1> [[TMP4]], i32 028; CHECK-NEXT: br i1 [[TMP16]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]29; CHECK: [[PRED_STORE_IF]]:30; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i8> [[TMP8]], i32 031; CHECK-NEXT: store i8 [[TMP17]], ptr [[P]], align 132; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]33; CHECK: [[PRED_STORE_CONTINUE]]:34; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP4]], i32 135; CHECK-NEXT: br i1 [[TMP11]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]36; CHECK: [[PRED_STORE_IF3]]:37; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i8> [[TMP8]], i32 138; CHECK-NEXT: store i8 [[TMP12]], ptr [[P]], align 139; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]40; CHECK: [[PRED_STORE_CONTINUE4]]:41; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i1> [[TMP4]], i32 242; CHECK-NEXT: br i1 [[TMP13]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]43; CHECK: [[PRED_STORE_IF5]]:44; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i8> [[TMP8]], i32 245; CHECK-NEXT: store i8 [[TMP14]], ptr [[P]], align 146; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]47; CHECK: [[PRED_STORE_CONTINUE6]]:48; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i1> [[TMP4]], i32 349; CHECK-NEXT: br i1 [[TMP15]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8]]50; CHECK: [[PRED_STORE_IF7]]:51; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i8> [[TMP8]], i32 352; CHECK-NEXT: store i8 [[TMP9]], ptr [[P]], align 153; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE8]]54; CHECK: [[PRED_STORE_CONTINUE8]]:55; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 456; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)57; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1258; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]59; CHECK: [[MIDDLE_BLOCK]]:60; CHECK-NEXT: br label %[[EXIT:.*]]61; CHECK: [[EXIT]]:62; CHECK-NEXT: ret void63;64entry:65 br label %loop.header66 67loop.header: ; preds = %loop.latch, %entry68 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]69 %iv.next = add i32 %iv, 170 %cmp.slt = icmp slt i32 %iv, 271 %shl = shl i64 %a, 4872 %ashr = ashr i64 %shl, 5273 %trunc.i32 = trunc i64 %ashr to i3274 br i1 %cmp.slt, label %cond.false, label %loop.latch75 76cond.false: ; preds = %loop.header77 %zext = zext i8 %b to i3278 br label %loop.latch79 80loop.latch: ; preds = %cond.false, %loop.header81 %cond = phi i32 [ %trunc.i32, %loop.header ], [ %zext, %cond.false ]82 %shl.i32 = shl i32 %cond, 883 %trunc = trunc i32 %shl.i32 to i884 store i8 %trunc, ptr %p, align 185 %exitcond = icmp slt i32 %iv, 886 br i1 %exitcond, label %loop.header, label %exit87 88exit: ; preds = %loop.latch89 ret void90}91 92define void @loop_invariant_srem(ptr %p, i64 %a, i8 %b) {93; CHECK-LABEL: define void @loop_invariant_srem(94; CHECK-SAME: ptr [[P:%.*]], i64 [[A:%.*]], i8 [[B:%.*]]) {95; CHECK-NEXT: [[ENTRY:.*:]]96; CHECK-NEXT: br label %[[VECTOR_PH:.*]]97; CHECK: [[VECTOR_PH]]:98; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i64 099; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT]], <4 x i8> poison, <4 x i32> zeroinitializer100; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[A]], 48101; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> poison, i64 [[TMP0]], i64 0102; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> poison, <4 x i32> zeroinitializer103; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i64> [[BROADCAST_SPLAT2]], splat (i64 52)104; CHECK-NEXT: [[TMP2:%.*]] = trunc <4 x i64> [[TMP1]] to <4 x i32>105; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT]] to <4 x i32>106; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]107; CHECK: [[VECTOR_BODY]]:108; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE10:.*]] ]109; CHECK-NEXT: [[VEC_IND1:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE10]] ]110; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <4 x i32> poison, i32 [[INDEX]], i64 0111; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT3]], <4 x i32> poison, <4 x i32> zeroinitializer112; CHECK-NEXT: [[VEC_IND:%.*]] = add <4 x i32> [[BROADCAST_SPLAT4]], <i32 0, i32 1, i32 2, i32 3>113; CHECK-NEXT: [[TMP4:%.*]] = icmp ule <4 x i32> [[VEC_IND]], splat (i32 8)114; CHECK-NEXT: [[TMP5:%.*]] = icmp slt <4 x i8> [[VEC_IND1]], splat (i8 2)115; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[TMP3]], <4 x i32> [[TMP2]]116; CHECK-NEXT: [[TMP7:%.*]] = shl <4 x i32> [[PREDPHI]], splat (i32 8)117; CHECK-NEXT: [[TMP8:%.*]] = trunc <4 x i32> [[TMP7]] to <4 x i8>118; CHECK-NEXT: [[TMP11:%.*]] = srem <4 x i8> [[VEC_IND1]], [[TMP8]]119; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP4]], i32 0120; CHECK-NEXT: br i1 [[TMP10]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]121; CHECK: [[PRED_STORE_IF]]:122; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i8> [[TMP11]], i32 0123; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[P]], i8 [[TMP13]]124; CHECK-NEXT: store i32 4, ptr [[TMP12]], align 4125; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]126; CHECK: [[PRED_STORE_CONTINUE]]:127; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i1> [[TMP4]], i32 1128; CHECK-NEXT: br i1 [[TMP14]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]129; CHECK: [[PRED_STORE_IF5]]:130; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i8> [[TMP11]], i32 1131; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[P]], i8 [[TMP16]]132; CHECK-NEXT: store i32 4, ptr [[TMP15]], align 4133; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]134; CHECK: [[PRED_STORE_CONTINUE6]]:135; CHECK-NEXT: [[TMP18:%.*]] = extractelement <4 x i1> [[TMP4]], i32 2136; CHECK-NEXT: br i1 [[TMP18]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]137; CHECK: [[PRED_STORE_IF7]]:138; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i8> [[TMP11]], i32 2139; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr [[P]], i8 [[TMP20]]140; CHECK-NEXT: store i32 4, ptr [[TMP19]], align 4141; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE8]]142; CHECK: [[PRED_STORE_CONTINUE8]]:143; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x i1> [[TMP4]], i32 3144; CHECK-NEXT: br i1 [[TMP22]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10]]145; CHECK: [[PRED_STORE_IF9]]:146; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i8> [[TMP11]], i32 3147; CHECK-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[P]], i8 [[TMP21]]148; CHECK-NEXT: store i32 4, ptr [[TMP23]], align 4149; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE10]]150; CHECK: [[PRED_STORE_CONTINUE10]]:151; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4152; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND1]], splat (i8 4)153; CHECK-NEXT: [[TMP26:%.*]] = icmp eq i32 [[INDEX_NEXT]], 12154; CHECK-NEXT: br i1 [[TMP26]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]155; CHECK: [[MIDDLE_BLOCK]]:156; CHECK-NEXT: br label %[[EXIT:.*]]157; CHECK: [[EXIT]]:158; CHECK-NEXT: ret void159;160entry:161 br label %loop.header162 163loop.header: ; preds = %loop.latch, %entry164 %iv = phi i8 [ 0, %entry ], [ %iv.next, %loop.latch ]165 %iv.next = add i8 %iv, 1166 %cmp.slt = icmp slt i8 %iv, 2167 %shl = shl i64 %a, 48168 %ashr = ashr i64 %shl, 52169 %trunc.i32 = trunc i64 %ashr to i32170 br i1 %cmp.slt, label %cond.false, label %loop.latch171 172cond.false: ; preds = %loop.header173 %zext = zext i8 %b to i32174 br label %loop.latch175 176loop.latch: ; preds = %cond.false, %loop.header177 %cond = phi i32 [ %trunc.i32, %loop.header ], [ %zext, %cond.false ]178 %shl.i32 = shl i32 %cond, 8179 %trunc = trunc i32 %shl.i32 to i8180 %rem = srem i8 %iv, %trunc181 %gep.p.rem = getelementptr i32, ptr %p, i8 %rem182 store i32 4, ptr %gep.p.rem183 %ec = icmp eq i8 %iv, 8184 br i1 %ec, label %exit, label %loop.header185 186exit: ; preds = %loop.latch187 ret void188}189 190define void @loop_invariant_float_store(ptr %p, i32 %a) {191; CHECK-LABEL: define void @loop_invariant_float_store(192; CHECK-SAME: ptr [[P:%.*]], i32 [[A:%.*]]) {193; CHECK-NEXT: [[ENTRY:.*:]]194; CHECK-NEXT: [[TMP10:%.*]] = sitofp i32 [[A]] to float195; CHECK-NEXT: br label %[[VECTOR_PH:.*]]196; CHECK: [[VECTOR_PH]]:197; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]198; CHECK: [[VECTOR_BODY]]:199; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]200; CHECK-NEXT: store float [[TMP10]], ptr [[P]], align 4201; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4202; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT]], 12203; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]204; CHECK: [[MIDDLE_BLOCK]]:205; CHECK-NEXT: br label %[[EXIT:.*]]206; CHECK: [[EXIT]]:207; CHECK-NEXT: ret void208;209entry:210 %a.conv = sitofp i32 %a to float211 br label %loop.header212 213loop.header: ; preds = %loop.latch, %entry214 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]215 %iv.next = add i32 %iv, 1216 %cmp.slt = icmp slt i32 %iv, 2217 br i1 %cmp.slt, label %cond.false, label %loop.latch218 219cond.false: ; preds = %loop.header220 br label %loop.latch221 222loop.latch: ; preds = %cond.false, %loop.header223 store float %a.conv, ptr %p224 %exitcond = icmp slt i32 %iv, 8225 br i1 %exitcond, label %loop.header, label %exit226 227exit: ; preds = %loop.latch228 ret void229}230 231; Test case for https://github.com/llvm/llvm-project/issues/149347.232define void @test_store_to_invariant_address_needs_mask_due_to_low_trip_count(ptr %dst) {233; CHECK-LABEL: define void @test_store_to_invariant_address_needs_mask_due_to_low_trip_count(234; CHECK-SAME: ptr [[DST:%.*]]) {235; CHECK-NEXT: [[ENTRY:.*:]]236; CHECK-NEXT: br label %[[VECTOR_PH:.*]]237; CHECK: [[VECTOR_PH]]:238; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]239; CHECK: [[VECTOR_BODY]]:240; CHECK-NEXT: br i1 true, label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]241; CHECK: [[PRED_STORE_IF]]:242; CHECK-NEXT: store i32 1, ptr [[DST]], align 4243; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]244; CHECK: [[PRED_STORE_CONTINUE]]:245; CHECK-NEXT: br i1 true, label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]246; CHECK: [[PRED_STORE_IF1]]:247; CHECK-NEXT: store i32 1, ptr [[DST]], align 4248; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE2]]249; CHECK: [[PRED_STORE_CONTINUE2]]:250; CHECK-NEXT: br i1 true, label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]251; CHECK: [[PRED_STORE_IF3]]:252; CHECK-NEXT: store i32 1, ptr [[DST]], align 4253; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]254; CHECK: [[PRED_STORE_CONTINUE4]]:255; CHECK-NEXT: br i1 false, label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]256; CHECK: [[PRED_STORE_IF5]]:257; CHECK-NEXT: store i32 1, ptr [[DST]], align 4258; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]259; CHECK: [[PRED_STORE_CONTINUE6]]:260; CHECK-NEXT: br label %[[MIDDLE_BLOCK:.*]]261; CHECK: [[MIDDLE_BLOCK]]:262; CHECK-NEXT: br label %[[EXIT:.*]]263; CHECK: [[EXIT]]:264; CHECK-NEXT: ret void265;266entry:267 br label %loop.header268 269loop.header:270 %iv = phi i16 [ 0, %entry ], [ %iv.next, %loop.latch ]271 br i1 true, label %loop.latch, label %else272 273else:274 br label %loop.latch275 276loop.latch:277 %merge = phi i32 [ 1, %loop.header ], [ 0, %else ]278 store i32 %merge, ptr %dst, align 4279 %iv.next = add i16 %iv, 1280 %ec = icmp eq i16 %iv.next, 3281 br i1 %ec, label %exit, label %loop.header282 283exit:284 ret void285}286