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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s3 4; TODO: Preserve disjoint flag on OR instruction.5define void @generate_disjoint_flags(i64 %n, ptr noalias %x) {6; CHECK-LABEL: define void @generate_disjoint_flags(7; CHECK-SAME: i64 [[N:%.*]], ptr noalias [[X:%.*]]) {8; CHECK-NEXT: entry:9; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 410; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]11; CHECK: vector.ph:12; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 413; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]14; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]15; CHECK: vector.body:16; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]17; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[X]], i64 [[INDEX]]18; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 419; CHECK-NEXT: [[TMP3:%.*]] = or disjoint <4 x i32> [[WIDE_LOAD]], splat (i32 1)20; CHECK-NEXT: [[TMP4:%.*]] = or <4 x i32> [[WIDE_LOAD]], splat (i32 3)21; CHECK-NEXT: [[TMP5:%.*]] = add nuw nsw <4 x i32> [[TMP3]], [[TMP4]]22; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP1]], align 423; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 424; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]25; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]26; CHECK: middle.block:27; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]28; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]29; CHECK: scalar.ph:30; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]31; CHECK-NEXT: br label [[LOOP:%.*]]32; CHECK: loop:33; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]34; CHECK-NEXT: [[GEP_X:%.*]] = getelementptr inbounds i32, ptr [[X]], i64 [[IV]]35; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_X]], align 436; CHECK-NEXT: [[OR_1:%.*]] = or disjoint i32 [[LV]], 137; CHECK-NEXT: [[OR_2:%.*]] = or i32 [[LV]], 338; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[OR_1]], [[OR_2]]39; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP_X]], align 440; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 141; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]42; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]43; CHECK: exit:44; CHECK-NEXT: ret void45;46entry:47 br label %loop48 49loop:50 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]51 %gep.x = getelementptr inbounds i32, ptr %x, i64 %iv52 %lv = load i32, ptr %gep.x, align 453 %or.1 = or disjoint i32 %lv, 154 %or.2 = or i32 %lv, 355 %add = add nsw nuw i32 %or.1, %or.256 store i32 %add, ptr %gep.x, align 457 %iv.next = add i64 %iv, 158 %exitcond = icmp eq i64 %iv.next, %n59 br i1 %exitcond, label %exit, label %loop60 61exit:62 ret void63}64;.65; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}66; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}67; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}68; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}69;.70