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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 62; RUN: opt < %s -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -S | FileCheck %s3; RUN: opt < %s -passes=loop-vectorize -force-vector-interleave=2 -force-vector-width=4 -prefer-inloop-reductions -S | FileCheck %s --check-prefix=CHECK-INTERLEAVED4 5target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"6 7define i32 @reduction_sum_single(ptr noalias nocapture %A) {8; CHECK-LABEL: define i32 @reduction_sum_single(9; CHECK-SAME: ptr noalias captures(none) [[A:%.*]]) {10; CHECK-NEXT:  [[ENTRY:.*:]]11; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]12; CHECK:       [[VECTOR_PH]]:13; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]14; CHECK:       [[VECTOR_BODY]]:15; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]16; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]17; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]18; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 419; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD]])20; CHECK-NEXT:    [[TMP2]] = add i32 [[VEC_PHI]], [[TMP1]]21; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 422; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 25623; CHECK-NEXT:    br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]24; CHECK:       [[MIDDLE_BLOCK]]:25; CHECK-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]26; CHECK:       [[__CRIT_EDGE:.*:]]27; CHECK-NEXT:    ret i32 [[TMP2]]28;29; CHECK-INTERLEAVED-LABEL: define i32 @reduction_sum_single(30; CHECK-INTERLEAVED-SAME: ptr noalias captures(none) [[A:%.*]]) {31; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]32; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]33; CHECK-INTERLEAVED:       [[VECTOR_PH]]:34; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]35; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:36; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]37; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]38; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]39; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]40; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 441; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 442; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP1]], align 443; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD]])44; CHECK-INTERLEAVED-NEXT:    [[TMP3]] = add i32 [[VEC_PHI]], [[TMP2]]45; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD2]])46; CHECK-INTERLEAVED-NEXT:    [[TMP5]] = add i32 [[VEC_PHI1]], [[TMP4]]47; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 848; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 25649; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]50; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:51; CHECK-INTERLEAVED-NEXT:    [[SUM_0_LCSSA:%.*]] = add i32 [[TMP5]], [[TMP3]]52; CHECK-INTERLEAVED-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]53; CHECK-INTERLEAVED:       [[__CRIT_EDGE:.*:]]54; CHECK-INTERLEAVED-NEXT:    ret i32 [[SUM_0_LCSSA]]55;56entry:57  br label %.lr.ph58 59.lr.ph:                                           ; preds = %entry, %.lr.ph60  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %entry ]61  %sum.02 = phi i32 [ %l7, %.lr.ph ], [ 0, %entry ]62  %l2 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv63  %l3 = load i32, ptr %l2, align 464  %l7 = add i32 %sum.02, %l365  %indvars.iv.next = add i64 %indvars.iv, 166  %lftr.wideiv = trunc i64 %indvars.iv.next to i3267  %exitcond = icmp eq i32 %lftr.wideiv, 25668  br i1 %exitcond, label %._crit_edge, label %.lr.ph69 70._crit_edge:                                      ; preds = %.lr.ph71  %sum.0.lcssa = phi i32 [ %l7, %.lr.ph ]72  ret i32 %sum.0.lcssa73}74 75define i32 @reduction_sum(ptr noalias nocapture %A, ptr noalias nocapture %B) {76; CHECK-LABEL: define i32 @reduction_sum(77; CHECK-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {78; CHECK-NEXT:  [[ENTRY:.*:]]79; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]80; CHECK:       [[VECTOR_PH]]:81; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]82; CHECK:       [[VECTOR_BODY]]:83; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]84; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]85; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]86; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]87; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 488; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]89; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 490; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[VEC_IND]])91; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[VEC_PHI]], [[TMP2]]92; CHECK-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD]])93; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[TMP3]], [[TMP4]]94; CHECK-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD1]])95; CHECK-NEXT:    [[TMP7]] = add i32 [[TMP5]], [[TMP6]]96; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 497; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)98; CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 25699; CHECK-NEXT:    br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]100; CHECK:       [[MIDDLE_BLOCK]]:101; CHECK-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]102; CHECK:       [[__CRIT_EDGE:.*:]]103; CHECK-NEXT:    ret i32 [[TMP7]]104;105; CHECK-INTERLEAVED-LABEL: define i32 @reduction_sum(106; CHECK-INTERLEAVED-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {107; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]108; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]109; CHECK-INTERLEAVED:       [[VECTOR_PH]]:110; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]111; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:112; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]113; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]114; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ]115; CHECK-INTERLEAVED-NEXT:    [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]116; CHECK-INTERLEAVED-NEXT:    [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4)117; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]118; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 4119; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4120; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4121; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]122; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 4123; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4124; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4125; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[VEC_IND]])126; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = add i32 [[VEC_PHI]], [[TMP4]]127; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[STEP_ADD]])128; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = add i32 [[VEC_PHI1]], [[TMP6]]129; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD]])130; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = add i32 [[TMP5]], [[TMP8]]131; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD2]])132; CHECK-INTERLEAVED-NEXT:    [[TMP11:%.*]] = add i32 [[TMP7]], [[TMP10]]133; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD3]])134; CHECK-INTERLEAVED-NEXT:    [[TMP13]] = add i32 [[TMP9]], [[TMP12]]135; CHECK-INTERLEAVED-NEXT:    [[TMP14:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD4]])136; CHECK-INTERLEAVED-NEXT:    [[TMP15]] = add i32 [[TMP11]], [[TMP14]]137; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8138; CHECK-INTERLEAVED-NEXT:    [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], splat (i32 4)139; CHECK-INTERLEAVED-NEXT:    [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256140; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]141; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:142; CHECK-INTERLEAVED-NEXT:    [[SUM_0_LCSSA:%.*]] = add i32 [[TMP15]], [[TMP13]]143; CHECK-INTERLEAVED-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]144; CHECK-INTERLEAVED:       [[__CRIT_EDGE:.*:]]145; CHECK-INTERLEAVED-NEXT:    ret i32 [[SUM_0_LCSSA]]146;147entry:148  br label %.lr.ph149 150.lr.ph:                                           ; preds = %entry, %.lr.ph151  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %entry ]152  %sum.02 = phi i32 [ %l9, %.lr.ph ], [ 0, %entry ]153  %l2 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv154  %l3 = load i32, ptr %l2, align 4155  %l4 = getelementptr inbounds i32, ptr %B, i64 %indvars.iv156  %l5 = load i32, ptr %l4, align 4157  %l6 = trunc i64 %indvars.iv to i32158  %l7 = add i32 %sum.02, %l6159  %l8 = add i32 %l7, %l3160  %l9 = add i32 %l8, %l5161  %indvars.iv.next = add i64 %indvars.iv, 1162  %lftr.wideiv = trunc i64 %indvars.iv.next to i32163  %exitcond = icmp eq i32 %lftr.wideiv, 256164  br i1 %exitcond, label %._crit_edge, label %.lr.ph165 166._crit_edge:                                      ; preds = %.lr.ph167  %sum.0.lcssa = phi i32 [ %l9, %.lr.ph ]168  ret i32 %sum.0.lcssa169}170 171define i32 @reduction_sum_const(ptr noalias nocapture %A) {172; CHECK-LABEL: define i32 @reduction_sum_const(173; CHECK-SAME: ptr noalias captures(none) [[A:%.*]]) {174; CHECK-NEXT:  [[ENTRY:.*:]]175; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]176; CHECK:       [[VECTOR_PH]]:177; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]178; CHECK:       [[VECTOR_BODY]]:179; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]180; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]181; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]182; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4183; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD]])184; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[VEC_PHI]], [[TMP1]]185; CHECK-NEXT:    [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> splat (i32 3))186; CHECK-NEXT:    [[TMP3]] = add i32 [[TMP2]], [[TMP5]]187; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4188; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256189; CHECK-NEXT:    br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]190; CHECK:       [[MIDDLE_BLOCK]]:191; CHECK-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]192; CHECK:       [[__CRIT_EDGE:.*:]]193; CHECK-NEXT:    ret i32 [[TMP3]]194;195; CHECK-INTERLEAVED-LABEL: define i32 @reduction_sum_const(196; CHECK-INTERLEAVED-SAME: ptr noalias captures(none) [[A:%.*]]) {197; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]198; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]199; CHECK-INTERLEAVED:       [[VECTOR_PH]]:200; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]201; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:202; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]203; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]204; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]205; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]206; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 4207; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4208; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4209; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD]])210; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = add i32 [[VEC_PHI]], [[TMP2]]211; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD2]])212; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = add i32 [[VEC_PHI1]], [[TMP4]]213; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> splat (i32 3))214; CHECK-INTERLEAVED-NEXT:    [[TMP6]] = add i32 [[TMP3]], [[TMP9]]215; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> splat (i32 3))216; CHECK-INTERLEAVED-NEXT:    [[TMP7]] = add i32 [[TMP5]], [[TMP10]]217; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8218; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256219; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]220; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:221; CHECK-INTERLEAVED-NEXT:    [[SUM_0_LCSSA:%.*]] = add i32 [[TMP7]], [[TMP6]]222; CHECK-INTERLEAVED-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]223; CHECK-INTERLEAVED:       [[__CRIT_EDGE:.*:]]224; CHECK-INTERLEAVED-NEXT:    ret i32 [[SUM_0_LCSSA]]225;226entry:227  br label %.lr.ph228 229.lr.ph:                                           ; preds = %entry, %.lr.ph230  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %entry ]231  %sum.02 = phi i32 [ %l9, %.lr.ph ], [ 0, %entry ]232  %l2 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv233  %l3 = load i32, ptr %l2, align 4234  %l7 = add i32 %sum.02, %l3235  %l9 = add i32 %l7, 3236  %indvars.iv.next = add i64 %indvars.iv, 1237  %lftr.wideiv = trunc i64 %indvars.iv.next to i32238  %exitcond = icmp eq i32 %lftr.wideiv, 256239  br i1 %exitcond, label %._crit_edge, label %.lr.ph240 241._crit_edge:                                      ; preds = %.lr.ph242  %sum.0.lcssa = phi i32 [ %l9, %.lr.ph ]243  ret i32 %sum.0.lcssa244}245 246define i32 @reduction_prod(ptr noalias nocapture %A, ptr noalias nocapture %B) {247; CHECK-LABEL: define i32 @reduction_prod(248; CHECK-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {249; CHECK-NEXT:  [[ENTRY:.*:]]250; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]251; CHECK:       [[VECTOR_PH]]:252; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]253; CHECK:       [[VECTOR_BODY]]:254; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]255; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 1, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]256; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]257; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]258; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4259; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]260; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4261; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[VEC_IND]])262; CHECK-NEXT:    [[TMP3:%.*]] = mul i32 [[VEC_PHI]], [[TMP2]]263; CHECK-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[WIDE_LOAD]])264; CHECK-NEXT:    [[TMP5:%.*]] = mul i32 [[TMP3]], [[TMP4]]265; CHECK-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[WIDE_LOAD1]])266; CHECK-NEXT:    [[TMP7]] = mul i32 [[TMP5]], [[TMP6]]267; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4268; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)269; CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256270; CHECK-NEXT:    br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]271; CHECK:       [[MIDDLE_BLOCK]]:272; CHECK-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]273; CHECK:       [[__CRIT_EDGE:.*:]]274; CHECK-NEXT:    ret i32 [[TMP7]]275;276; CHECK-INTERLEAVED-LABEL: define i32 @reduction_prod(277; CHECK-INTERLEAVED-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {278; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]279; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]280; CHECK-INTERLEAVED:       [[VECTOR_PH]]:281; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]282; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:283; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]284; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 1, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]285; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 1, %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ]286; CHECK-INTERLEAVED-NEXT:    [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]287; CHECK-INTERLEAVED-NEXT:    [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4)288; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]289; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 4290; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4291; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4292; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]293; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 4294; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4295; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4296; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[VEC_IND]])297; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = mul i32 [[VEC_PHI]], [[TMP4]]298; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[STEP_ADD]])299; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = mul i32 [[VEC_PHI1]], [[TMP6]]300; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[WIDE_LOAD]])301; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = mul i32 [[TMP5]], [[TMP8]]302; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[WIDE_LOAD2]])303; CHECK-INTERLEAVED-NEXT:    [[TMP11:%.*]] = mul i32 [[TMP7]], [[TMP10]]304; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[WIDE_LOAD3]])305; CHECK-INTERLEAVED-NEXT:    [[TMP13]] = mul i32 [[TMP9]], [[TMP12]]306; CHECK-INTERLEAVED-NEXT:    [[TMP14:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[WIDE_LOAD4]])307; CHECK-INTERLEAVED-NEXT:    [[TMP15]] = mul i32 [[TMP11]], [[TMP14]]308; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8309; CHECK-INTERLEAVED-NEXT:    [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], splat (i32 4)310; CHECK-INTERLEAVED-NEXT:    [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256311; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]312; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:313; CHECK-INTERLEAVED-NEXT:    [[PROD_0_LCSSA:%.*]] = mul i32 [[TMP15]], [[TMP13]]314; CHECK-INTERLEAVED-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]315; CHECK-INTERLEAVED:       [[__CRIT_EDGE:.*:]]316; CHECK-INTERLEAVED-NEXT:    ret i32 [[PROD_0_LCSSA]]317;318entry:319  br label %.lr.ph320 321.lr.ph:                                           ; preds = %entry, %.lr.ph322  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %entry ]323  %prod.02 = phi i32 [ %l9, %.lr.ph ], [ 1, %entry ]324  %l2 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv325  %l3 = load i32, ptr %l2, align 4326  %l4 = getelementptr inbounds i32, ptr %B, i64 %indvars.iv327  %l5 = load i32, ptr %l4, align 4328  %l6 = trunc i64 %indvars.iv to i32329  %l7 = mul i32 %prod.02, %l6330  %l8 = mul i32 %l7, %l3331  %l9 = mul i32 %l8, %l5332  %indvars.iv.next = add i64 %indvars.iv, 1333  %lftr.wideiv = trunc i64 %indvars.iv.next to i32334  %exitcond = icmp eq i32 %lftr.wideiv, 256335  br i1 %exitcond, label %._crit_edge, label %.lr.ph336 337._crit_edge:                                      ; preds = %.lr.ph338  %prod.0.lcssa = phi i32 [ %l9, %.lr.ph ]339  ret i32 %prod.0.lcssa340}341 342define i32 @reduction_mix(ptr noalias nocapture %A, ptr noalias nocapture %B) {343; CHECK-LABEL: define i32 @reduction_mix(344; CHECK-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {345; CHECK-NEXT:  [[ENTRY:.*:]]346; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]347; CHECK:       [[VECTOR_PH]]:348; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]349; CHECK:       [[VECTOR_BODY]]:350; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]351; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]352; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]353; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]354; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4355; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]356; CHECK-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP8]], align 4357; CHECK-NEXT:    [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[VEC_IND]])358; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[VEC_PHI]], [[TMP3]]359; CHECK-NEXT:    [[TMP2:%.*]] = mul nsw <4 x i32> [[WIDE_LOAD2]], [[WIDE_LOAD1]]360; CHECK-NEXT:    [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])361; CHECK-NEXT:    [[TMP6]] = add i32 [[TMP4]], [[TMP5]]362; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4363; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)364; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256365; CHECK-NEXT:    br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]366; CHECK:       [[MIDDLE_BLOCK]]:367; CHECK-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]368; CHECK:       [[__CRIT_EDGE:.*:]]369; CHECK-NEXT:    ret i32 [[TMP6]]370;371; CHECK-INTERLEAVED-LABEL: define i32 @reduction_mix(372; CHECK-INTERLEAVED-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {373; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]374; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]375; CHECK-INTERLEAVED:       [[VECTOR_PH]]:376; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]377; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:378; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]379; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ]380; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]381; CHECK-INTERLEAVED-NEXT:    [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]382; CHECK-INTERLEAVED-NEXT:    [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4)383; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]384; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 4385; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4386; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4387; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]388; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 4389; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4390; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4391; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[VEC_IND]])392; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = add i32 [[VEC_PHI]], [[TMP4]]393; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[STEP_ADD]])394; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = add i32 [[VEC_PHI1]], [[TMP6]]395; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = mul nsw <4 x i32> [[WIDE_LOAD3]], [[WIDE_LOAD]]396; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP8]])397; CHECK-INTERLEAVED-NEXT:    [[TMP10]] = add i32 [[TMP5]], [[TMP9]]398; CHECK-INTERLEAVED-NEXT:    [[TMP11:%.*]] = mul nsw <4 x i32> [[WIDE_LOAD4]], [[WIDE_LOAD2]]399; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP11]])400; CHECK-INTERLEAVED-NEXT:    [[TMP13]] = add i32 [[TMP7]], [[TMP12]]401; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8402; CHECK-INTERLEAVED-NEXT:    [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], splat (i32 4)403; CHECK-INTERLEAVED-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256404; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]405; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:406; CHECK-INTERLEAVED-NEXT:    [[SUM_0_LCSSA:%.*]] = add i32 [[TMP13]], [[TMP10]]407; CHECK-INTERLEAVED-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]408; CHECK-INTERLEAVED:       [[__CRIT_EDGE:.*:]]409; CHECK-INTERLEAVED-NEXT:    ret i32 [[SUM_0_LCSSA]]410;411entry:412  br label %.lr.ph413 414.lr.ph:                                           ; preds = %entry, %.lr.ph415  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %entry ]416  %sum.02 = phi i32 [ %l9, %.lr.ph ], [ 0, %entry ]417  %l2 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv418  %l3 = load i32, ptr %l2, align 4419  %l4 = getelementptr inbounds i32, ptr %B, i64 %indvars.iv420  %l5 = load i32, ptr %l4, align 4421  %l6 = mul nsw i32 %l5, %l3422  %l7 = trunc i64 %indvars.iv to i32423  %l8 = add i32 %sum.02, %l7424  %l9 = add i32 %l8, %l6425  %indvars.iv.next = add i64 %indvars.iv, 1426  %lftr.wideiv = trunc i64 %indvars.iv.next to i32427  %exitcond = icmp eq i32 %lftr.wideiv, 256428  br i1 %exitcond, label %._crit_edge, label %.lr.ph429 430._crit_edge:                                      ; preds = %.lr.ph431  %sum.0.lcssa = phi i32 [ %l9, %.lr.ph ]432  ret i32 %sum.0.lcssa433}434 435define i32 @reduction_mul(ptr noalias nocapture %A, ptr noalias nocapture %B) {436; CHECK-LABEL: define i32 @reduction_mul(437; CHECK-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {438; CHECK-NEXT:  [[ENTRY:.*:]]439; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]440; CHECK:       [[VECTOR_PH]]:441; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]442; CHECK:       [[VECTOR_BODY]]:443; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]444; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 19, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]445; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]446; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4447; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]448; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4449; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[WIDE_LOAD]])450; CHECK-NEXT:    [[TMP3:%.*]] = mul i32 [[VEC_PHI]], [[TMP2]]451; CHECK-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[WIDE_LOAD1]])452; CHECK-NEXT:    [[TMP5]] = mul i32 [[TMP3]], [[TMP4]]453; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4454; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256455; CHECK-NEXT:    br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]456; CHECK:       [[MIDDLE_BLOCK]]:457; CHECK-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]458; CHECK:       [[__CRIT_EDGE:.*:]]459; CHECK-NEXT:    ret i32 [[TMP5]]460;461; CHECK-INTERLEAVED-LABEL: define i32 @reduction_mul(462; CHECK-INTERLEAVED-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {463; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]464; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]465; CHECK-INTERLEAVED:       [[VECTOR_PH]]:466; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]467; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:468; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]469; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 19, %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]470; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 1, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]471; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]472; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 4473; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4474; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4475; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]476; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 4477; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4478; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4479; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[WIDE_LOAD]])480; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = mul i32 [[VEC_PHI]], [[TMP4]]481; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[WIDE_LOAD2]])482; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = mul i32 [[VEC_PHI1]], [[TMP6]]483; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[WIDE_LOAD3]])484; CHECK-INTERLEAVED-NEXT:    [[TMP9]] = mul i32 [[TMP5]], [[TMP8]]485; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[WIDE_LOAD4]])486; CHECK-INTERLEAVED-NEXT:    [[TMP11]] = mul i32 [[TMP7]], [[TMP10]]487; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8488; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256489; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]490; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:491; CHECK-INTERLEAVED-NEXT:    [[SUM_0_LCSSA:%.*]] = mul i32 [[TMP11]], [[TMP9]]492; CHECK-INTERLEAVED-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]493; CHECK-INTERLEAVED:       [[__CRIT_EDGE:.*:]]494; CHECK-INTERLEAVED-NEXT:    ret i32 [[SUM_0_LCSSA]]495;496entry:497  br label %.lr.ph498 499.lr.ph:                                           ; preds = %entry, %.lr.ph500  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %entry ]501  %sum.02 = phi i32 [ %l7, %.lr.ph ], [ 19, %entry ]502  %l2 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv503  %l3 = load i32, ptr %l2, align 4504  %l4 = getelementptr inbounds i32, ptr %B, i64 %indvars.iv505  %l5 = load i32, ptr %l4, align 4506  %l6 = mul i32 %sum.02, %l3507  %l7 = mul i32 %l6, %l5508  %indvars.iv.next = add i64 %indvars.iv, 1509  %lftr.wideiv = trunc i64 %indvars.iv.next to i32510  %exitcond = icmp eq i32 %lftr.wideiv, 256511  br i1 %exitcond, label %._crit_edge, label %.lr.ph512 513._crit_edge:                                      ; preds = %.lr.ph514  %sum.0.lcssa = phi i32 [ %l7, %.lr.ph ]515  ret i32 %sum.0.lcssa516}517 518define i32 @start_at_non_zero(ptr nocapture %in, ptr nocapture %coeff, ptr nocapture %out) {519; CHECK-LABEL: define i32 @start_at_non_zero(520; CHECK-SAME: ptr captures(none) [[IN:%.*]], ptr captures(none) [[COEFF:%.*]], ptr captures(none) [[OUT:%.*]]) {521; CHECK-NEXT:  [[ENTRY:.*:]]522; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]523; CHECK:       [[VECTOR_PH]]:524; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]525; CHECK:       [[VECTOR_BODY]]:526; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]527; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 120, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]528; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[IN]], i64 [[INDEX]]529; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4530; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[COEFF]], i64 [[INDEX]]531; CHECK-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4532; CHECK-NEXT:    [[TMP2:%.*]] = mul nsw <4 x i32> [[WIDE_LOAD2]], [[WIDE_LOAD1]]533; CHECK-NEXT:    [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])534; CHECK-NEXT:    [[TMP4]] = add i32 [[VEC_PHI]], [[TMP3]]535; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4536; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256537; CHECK-NEXT:    br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]538; CHECK:       [[MIDDLE_BLOCK]]:539; CHECK-NEXT:    br label %[[FOR_END:.*]]540; CHECK:       [[FOR_END]]:541; CHECK-NEXT:    ret i32 [[TMP4]]542;543; CHECK-INTERLEAVED-LABEL: define i32 @start_at_non_zero(544; CHECK-INTERLEAVED-SAME: ptr captures(none) [[IN:%.*]], ptr captures(none) [[COEFF:%.*]], ptr captures(none) [[OUT:%.*]]) {545; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]546; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]547; CHECK-INTERLEAVED:       [[VECTOR_PH]]:548; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]549; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:550; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]551; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 120, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]552; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]553; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[IN]], i64 [[INDEX]]554; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 4555; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4556; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4557; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[COEFF]], i64 [[INDEX]]558; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 4559; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4560; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4561; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = mul nsw <4 x i32> [[WIDE_LOAD3]], [[WIDE_LOAD]]562; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP4]])563; CHECK-INTERLEAVED-NEXT:    [[TMP6]] = add i32 [[VEC_PHI]], [[TMP5]]564; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = mul nsw <4 x i32> [[WIDE_LOAD4]], [[WIDE_LOAD2]]565; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP7]])566; CHECK-INTERLEAVED-NEXT:    [[TMP9]] = add i32 [[VEC_PHI1]], [[TMP8]]567; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8568; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256569; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]570; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:571; CHECK-INTERLEAVED-NEXT:    [[BIN_RDX:%.*]] = add i32 [[TMP9]], [[TMP6]]572; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_END:.*]]573; CHECK-INTERLEAVED:       [[FOR_END]]:574; CHECK-INTERLEAVED-NEXT:    ret i32 [[BIN_RDX]]575;576entry:577  br label %for.body578 579for.body:                                         ; preds = %entry, %for.body580  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]581  %sum.09 = phi i32 [ %add, %for.body ], [ 120, %entry ]582  %arrayidx = getelementptr inbounds i32, ptr %in, i64 %indvars.iv583  %l0 = load i32, ptr %arrayidx, align 4584  %arrayidx2 = getelementptr inbounds i32, ptr %coeff, i64 %indvars.iv585  %l1 = load i32, ptr %arrayidx2, align 4586  %mul = mul nsw i32 %l1, %l0587  %add = add nsw i32 %mul, %sum.09588  %indvars.iv.next = add i64 %indvars.iv, 1589  %lftr.wideiv = trunc i64 %indvars.iv.next to i32590  %exitcond = icmp eq i32 %lftr.wideiv, 256591  br i1 %exitcond, label %for.end, label %for.body592 593for.end:                                          ; preds = %for.body, %entry594  %sum.0.lcssa = phi i32 [ %add, %for.body ]595  ret i32 %sum.0.lcssa596}597 598define i32 @reduction_and(ptr nocapture %A, ptr nocapture %B) {599; CHECK-LABEL: define i32 @reduction_and(600; CHECK-SAME: ptr captures(none) [[A:%.*]], ptr captures(none) [[B:%.*]]) {601; CHECK-NEXT:  [[ENTRY:.*:]]602; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]603; CHECK:       [[VECTOR_PH]]:604; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]605; CHECK:       [[VECTOR_BODY]]:606; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]607; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ -1, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]608; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]609; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4610; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]611; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4612; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[WIDE_LOAD]])613; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[VEC_PHI]], [[TMP2]]614; CHECK-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[WIDE_LOAD1]])615; CHECK-NEXT:    [[TMP5]] = and i32 [[TMP3]], [[TMP4]]616; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4617; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256618; CHECK-NEXT:    br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]619; CHECK:       [[MIDDLE_BLOCK]]:620; CHECK-NEXT:    br label %[[FOR_END:.*]]621; CHECK:       [[FOR_END]]:622; CHECK-NEXT:    ret i32 [[TMP5]]623;624; CHECK-INTERLEAVED-LABEL: define i32 @reduction_and(625; CHECK-INTERLEAVED-SAME: ptr captures(none) [[A:%.*]], ptr captures(none) [[B:%.*]]) {626; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]627; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]628; CHECK-INTERLEAVED:       [[VECTOR_PH]]:629; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]630; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:631; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]632; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ -1, %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]633; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ -1, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]634; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]635; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 4636; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4637; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4638; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]639; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 4640; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4641; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4642; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[WIDE_LOAD]])643; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = and i32 [[VEC_PHI]], [[TMP4]]644; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[WIDE_LOAD2]])645; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = and i32 [[VEC_PHI1]], [[TMP6]]646; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[WIDE_LOAD3]])647; CHECK-INTERLEAVED-NEXT:    [[TMP9]] = and i32 [[TMP5]], [[TMP8]]648; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[WIDE_LOAD4]])649; CHECK-INTERLEAVED-NEXT:    [[TMP11]] = and i32 [[TMP7]], [[TMP10]]650; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8651; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256652; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]653; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:654; CHECK-INTERLEAVED-NEXT:    [[RESULT_0_LCSSA:%.*]] = and i32 [[TMP11]], [[TMP9]]655; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_END:.*]]656; CHECK-INTERLEAVED:       [[FOR_END]]:657; CHECK-INTERLEAVED-NEXT:    ret i32 [[RESULT_0_LCSSA]]658;659entry:660  br label %for.body661 662for.body:                                         ; preds = %entry, %for.body663  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]664  %result.08 = phi i32 [ %and, %for.body ], [ -1, %entry ]665  %arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv666  %l0 = load i32, ptr %arrayidx, align 4667  %arrayidx2 = getelementptr inbounds i32, ptr %B, i64 %indvars.iv668  %l1 = load i32, ptr %arrayidx2, align 4669  %add = and i32 %result.08, %l0670  %and = and i32 %add, %l1671  %indvars.iv.next = add i64 %indvars.iv, 1672  %lftr.wideiv = trunc i64 %indvars.iv.next to i32673  %exitcond = icmp eq i32 %lftr.wideiv, 256674  br i1 %exitcond, label %for.end, label %for.body675 676for.end:                                          ; preds = %for.body, %entry677  %result.0.lcssa = phi i32 [ %and, %for.body ]678  ret i32 %result.0.lcssa679}680 681define i32 @reduction_or(ptr nocapture %A, ptr nocapture %B) {682; CHECK-LABEL: define i32 @reduction_or(683; CHECK-SAME: ptr captures(none) [[A:%.*]], ptr captures(none) [[B:%.*]]) {684; CHECK-NEXT:  [[ENTRY:.*:]]685; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]686; CHECK:       [[VECTOR_PH]]:687; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]688; CHECK:       [[VECTOR_BODY]]:689; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]690; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]691; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]692; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4693; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]694; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4695; CHECK-NEXT:    [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[WIDE_LOAD]]696; CHECK-NEXT:    [[TMP3:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP2]])697; CHECK-NEXT:    [[TMP4]] = or i32 [[VEC_PHI]], [[TMP3]]698; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4699; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256700; CHECK-NEXT:    br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]701; CHECK:       [[MIDDLE_BLOCK]]:702; CHECK-NEXT:    br label %[[FOR_END:.*]]703; CHECK:       [[FOR_END]]:704; CHECK-NEXT:    ret i32 [[TMP4]]705;706; CHECK-INTERLEAVED-LABEL: define i32 @reduction_or(707; CHECK-INTERLEAVED-SAME: ptr captures(none) [[A:%.*]], ptr captures(none) [[B:%.*]]) {708; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]709; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]710; CHECK-INTERLEAVED:       [[VECTOR_PH]]:711; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]712; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:713; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]714; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]715; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]716; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]717; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 4718; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4719; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4720; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]721; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 4722; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4723; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4724; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = add nsw <4 x i32> [[WIDE_LOAD3]], [[WIDE_LOAD]]725; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD4]], [[WIDE_LOAD2]]726; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP4]])727; CHECK-INTERLEAVED-NEXT:    [[TMP7]] = or i32 [[VEC_PHI]], [[TMP6]]728; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP5]])729; CHECK-INTERLEAVED-NEXT:    [[TMP9]] = or i32 [[VEC_PHI1]], [[TMP8]]730; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8731; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256732; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]733; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:734; CHECK-INTERLEAVED-NEXT:    [[RESULT_0_LCSSA:%.*]] = or i32 [[TMP9]], [[TMP7]]735; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_END:.*]]736; CHECK-INTERLEAVED:       [[FOR_END]]:737; CHECK-INTERLEAVED-NEXT:    ret i32 [[RESULT_0_LCSSA]]738;739entry:740  br label %for.body741 742for.body:                                         ; preds = %entry, %for.body743  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]744  %result.08 = phi i32 [ %or, %for.body ], [ 0, %entry ]745  %arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv746  %l0 = load i32, ptr %arrayidx, align 4747  %arrayidx2 = getelementptr inbounds i32, ptr %B, i64 %indvars.iv748  %l1 = load i32, ptr %arrayidx2, align 4749  %add = add nsw i32 %l1, %l0750  %or = or i32 %add, %result.08751  %indvars.iv.next = add i64 %indvars.iv, 1752  %lftr.wideiv = trunc i64 %indvars.iv.next to i32753  %exitcond = icmp eq i32 %lftr.wideiv, 256754  br i1 %exitcond, label %for.end, label %for.body755 756for.end:                                          ; preds = %for.body, %entry757  %result.0.lcssa = phi i32 [ %or, %for.body ]758  ret i32 %result.0.lcssa759}760 761define i32 @reduction_xor(ptr nocapture %A, ptr nocapture %B) {762; CHECK-LABEL: define i32 @reduction_xor(763; CHECK-SAME: ptr captures(none) [[A:%.*]], ptr captures(none) [[B:%.*]]) {764; CHECK-NEXT:  [[ENTRY:.*:]]765; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]766; CHECK:       [[VECTOR_PH]]:767; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]768; CHECK:       [[VECTOR_BODY]]:769; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]770; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]771; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]772; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4773; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]774; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4775; CHECK-NEXT:    [[TMP2:%.*]] = add nsw <4 x i32> [[WIDE_LOAD1]], [[WIDE_LOAD]]776; CHECK-NEXT:    [[TMP3:%.*]] = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> [[TMP2]])777; CHECK-NEXT:    [[TMP4]] = xor i32 [[VEC_PHI]], [[TMP3]]778; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4779; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256780; CHECK-NEXT:    br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]781; CHECK:       [[MIDDLE_BLOCK]]:782; CHECK-NEXT:    br label %[[FOR_END:.*]]783; CHECK:       [[FOR_END]]:784; CHECK-NEXT:    ret i32 [[TMP4]]785;786; CHECK-INTERLEAVED-LABEL: define i32 @reduction_xor(787; CHECK-INTERLEAVED-SAME: ptr captures(none) [[A:%.*]], ptr captures(none) [[B:%.*]]) {788; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]789; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]790; CHECK-INTERLEAVED:       [[VECTOR_PH]]:791; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]792; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:793; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]794; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]795; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]796; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]797; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 4798; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4799; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4800; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]801; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 4802; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4803; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4804; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = add nsw <4 x i32> [[WIDE_LOAD3]], [[WIDE_LOAD]]805; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD4]], [[WIDE_LOAD2]]806; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> [[TMP4]])807; CHECK-INTERLEAVED-NEXT:    [[TMP7]] = xor i32 [[VEC_PHI]], [[TMP6]]808; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> [[TMP5]])809; CHECK-INTERLEAVED-NEXT:    [[TMP9]] = xor i32 [[VEC_PHI1]], [[TMP8]]810; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8811; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256812; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]813; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:814; CHECK-INTERLEAVED-NEXT:    [[RESULT_0_LCSSA:%.*]] = xor i32 [[TMP9]], [[TMP7]]815; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_END:.*]]816; CHECK-INTERLEAVED:       [[FOR_END]]:817; CHECK-INTERLEAVED-NEXT:    ret i32 [[RESULT_0_LCSSA]]818;819entry:820  br label %for.body821 822for.body:                                         ; preds = %entry, %for.body823  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]824  %result.08 = phi i32 [ %xor, %for.body ], [ 0, %entry ]825  %arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv826  %l0 = load i32, ptr %arrayidx, align 4827  %arrayidx2 = getelementptr inbounds i32, ptr %B, i64 %indvars.iv828  %l1 = load i32, ptr %arrayidx2, align 4829  %add = add nsw i32 %l1, %l0830  %xor = xor i32 %add, %result.08831  %indvars.iv.next = add i64 %indvars.iv, 1832  %lftr.wideiv = trunc i64 %indvars.iv.next to i32833  %exitcond = icmp eq i32 %lftr.wideiv, 256834  br i1 %exitcond, label %for.end, label %for.body835 836for.end:                                          ; preds = %for.body, %entry837  %result.0.lcssa = phi i32 [ %xor, %for.body ]838  ret i32 %result.0.lcssa839}840 841define float @reduction_fadd(ptr nocapture %A, ptr nocapture %B) {842; CHECK-LABEL: define float @reduction_fadd(843; CHECK-SAME: ptr captures(none) [[A:%.*]], ptr captures(none) [[B:%.*]]) {844; CHECK-NEXT:  [[ENTRY:.*:]]845; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]846; CHECK:       [[VECTOR_PH]]:847; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]848; CHECK:       [[VECTOR_BODY]]:849; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]850; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]851; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]]852; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 4853; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDEX]]854; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP1]], align 4855; CHECK-NEXT:    [[TMP2:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[WIDE_LOAD]])856; CHECK-NEXT:    [[TMP5:%.*]] = fadd fast float [[VEC_PHI]], [[TMP2]]857; CHECK-NEXT:    [[TMP6:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[WIDE_LOAD1]])858; CHECK-NEXT:    [[TMP3]] = fadd fast float [[TMP5]], [[TMP6]]859; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4860; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256861; CHECK-NEXT:    br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]862; CHECK:       [[MIDDLE_BLOCK]]:863; CHECK-NEXT:    br label %[[FOR_END:.*]]864; CHECK:       [[FOR_END]]:865; CHECK-NEXT:    ret float [[TMP3]]866;867; CHECK-INTERLEAVED-LABEL: define float @reduction_fadd(868; CHECK-INTERLEAVED-SAME: ptr captures(none) [[A:%.*]], ptr captures(none) [[B:%.*]]) {869; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]870; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]871; CHECK-INTERLEAVED:       [[VECTOR_PH]]:872; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]873; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:874; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]875; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]876; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi float [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]877; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]]878; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds float, ptr [[TMP0]], i64 4879; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 4880; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x float>, ptr [[TMP1]], align 4881; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDEX]]882; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 4883; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x float>, ptr [[TMP2]], align 4884; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP3]], align 4885; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[WIDE_LOAD]])886; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = fadd fast float [[VEC_PHI]], [[TMP4]]887; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[WIDE_LOAD2]])888; CHECK-INTERLEAVED-NEXT:    [[TMP11:%.*]] = fadd fast float [[VEC_PHI1]], [[TMP9]]889; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[WIDE_LOAD3]])890; CHECK-INTERLEAVED-NEXT:    [[TMP6]] = fadd fast float [[TMP5]], [[TMP12]]891; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[WIDE_LOAD4]])892; CHECK-INTERLEAVED-NEXT:    [[TMP7]] = fadd fast float [[TMP11]], [[TMP10]]893; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8894; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256895; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]896; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:897; CHECK-INTERLEAVED-NEXT:    [[RESULT_0_LCSSA:%.*]] = fadd fast float [[TMP7]], [[TMP6]]898; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_END:.*]]899; CHECK-INTERLEAVED:       [[FOR_END]]:900; CHECK-INTERLEAVED-NEXT:    ret float [[RESULT_0_LCSSA]]901;902entry:903  br label %for.body904 905for.body:                                         ; preds = %entry, %for.body906  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]907  %result.08 = phi float [ %fadd, %for.body ], [ 0.0, %entry ]908  %arrayidx = getelementptr inbounds float, ptr %A, i64 %indvars.iv909  %l0 = load float, ptr %arrayidx, align 4910  %arrayidx2 = getelementptr inbounds float, ptr %B, i64 %indvars.iv911  %l1 = load float, ptr %arrayidx2, align 4912  %add = fadd fast float %result.08, %l0913  %fadd = fadd fast float %add, %l1914  %indvars.iv.next = add i64 %indvars.iv, 1915  %lftr.wideiv = trunc i64 %indvars.iv.next to i32916  %exitcond = icmp eq i32 %lftr.wideiv, 256917  br i1 %exitcond, label %for.end, label %for.body918 919for.end:                                          ; preds = %for.body, %entry920  %result.0.lcssa = phi float [ %fadd, %for.body ]921  ret float %result.0.lcssa922}923 924define float @reduction_fmul(ptr nocapture %A, ptr nocapture %B) {925; CHECK-LABEL: define float @reduction_fmul(926; CHECK-SAME: ptr captures(none) [[A:%.*]], ptr captures(none) [[B:%.*]]) {927; CHECK-NEXT:  [[ENTRY:.*:]]928; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]929; CHECK:       [[VECTOR_PH]]:930; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]931; CHECK:       [[VECTOR_BODY]]:932; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]933; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]934; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]]935; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 4936; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDEX]]937; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP1]], align 4938; CHECK-NEXT:    [[TMP2:%.*]] = call fast float @llvm.vector.reduce.fmul.v4f32(float 1.000000e+00, <4 x float> [[WIDE_LOAD]])939; CHECK-NEXT:    [[TMP3:%.*]] = fmul fast float [[VEC_PHI]], [[TMP2]]940; CHECK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.vector.reduce.fmul.v4f32(float 1.000000e+00, <4 x float> [[WIDE_LOAD1]])941; CHECK-NEXT:    [[TMP5]] = fmul fast float [[TMP3]], [[TMP4]]942; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4943; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256944; CHECK-NEXT:    br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]945; CHECK:       [[MIDDLE_BLOCK]]:946; CHECK-NEXT:    br label %[[FOR_END:.*]]947; CHECK:       [[FOR_END]]:948; CHECK-NEXT:    ret float [[TMP5]]949;950; CHECK-INTERLEAVED-LABEL: define float @reduction_fmul(951; CHECK-INTERLEAVED-SAME: ptr captures(none) [[A:%.*]], ptr captures(none) [[B:%.*]]) {952; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]953; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]954; CHECK-INTERLEAVED:       [[VECTOR_PH]]:955; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]956; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:957; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]958; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]959; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi float [ 1.000000e+00, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]960; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]]961; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds float, ptr [[TMP0]], i64 4962; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 4963; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x float>, ptr [[TMP1]], align 4964; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDEX]]965; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 4966; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x float>, ptr [[TMP2]], align 4967; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP3]], align 4968; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = call fast float @llvm.vector.reduce.fmul.v4f32(float 1.000000e+00, <4 x float> [[WIDE_LOAD]])969; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = fmul fast float [[VEC_PHI]], [[TMP4]]970; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = call fast float @llvm.vector.reduce.fmul.v4f32(float 1.000000e+00, <4 x float> [[WIDE_LOAD2]])971; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = fmul fast float [[VEC_PHI1]], [[TMP6]]972; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = call fast float @llvm.vector.reduce.fmul.v4f32(float 1.000000e+00, <4 x float> [[WIDE_LOAD3]])973; CHECK-INTERLEAVED-NEXT:    [[TMP9]] = fmul fast float [[TMP5]], [[TMP8]]974; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = call fast float @llvm.vector.reduce.fmul.v4f32(float 1.000000e+00, <4 x float> [[WIDE_LOAD4]])975; CHECK-INTERLEAVED-NEXT:    [[TMP11]] = fmul fast float [[TMP7]], [[TMP10]]976; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8977; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256978; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]979; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:980; CHECK-INTERLEAVED-NEXT:    [[RESULT_0_LCSSA:%.*]] = fmul fast float [[TMP11]], [[TMP9]]981; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_END:.*]]982; CHECK-INTERLEAVED:       [[FOR_END]]:983; CHECK-INTERLEAVED-NEXT:    ret float [[RESULT_0_LCSSA]]984;985entry:986  br label %for.body987 988for.body:                                         ; preds = %entry, %for.body989  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]990  %result.08 = phi float [ %fmul, %for.body ], [ 0.0, %entry ]991  %arrayidx = getelementptr inbounds float, ptr %A, i64 %indvars.iv992  %l0 = load float, ptr %arrayidx, align 4993  %arrayidx2 = getelementptr inbounds float, ptr %B, i64 %indvars.iv994  %l1 = load float, ptr %arrayidx2, align 4995  %add = fmul fast float %result.08, %l0996  %fmul = fmul fast float %add, %l1997  %indvars.iv.next = add i64 %indvars.iv, 1998  %lftr.wideiv = trunc i64 %indvars.iv.next to i32999  %exitcond = icmp eq i32 %lftr.wideiv, 2561000  br i1 %exitcond, label %for.end, label %for.body1001 1002for.end:                                          ; preds = %for.body, %entry1003  %result.0.lcssa = phi float [ %fmul, %for.body ]1004  ret float %result.0.lcssa1005}1006 1007; We can create an in-loop reduction for sub-reductions with a sub and add-reduction1008define i32 @reduction_sub_lhs(ptr noalias nocapture %A) {1009; CHECK-LABEL: define i32 @reduction_sub_lhs(1010; CHECK-SAME: ptr noalias captures(none) [[A:%.*]]) {1011; CHECK-NEXT:  [[ENTRY:.*:]]1012; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]1013; CHECK:       [[VECTOR_PH]]:1014; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]1015; CHECK:       [[VECTOR_BODY]]:1016; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1017; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 3, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]1018; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]1019; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 41020; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD]])1021; CHECK-NEXT:    [[TMP5]] = sub i32 [[VEC_PHI]], [[TMP1]]1022; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 41023; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2561024; CHECK-NEXT:    br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]1025; CHECK:       [[MIDDLE_BLOCK]]:1026; CHECK-NEXT:    br label %[[FOR_END:.*]]1027; CHECK:       [[FOR_END]]:1028; CHECK-NEXT:    ret i32 [[TMP5]]1029;1030; CHECK-INTERLEAVED-LABEL: define i32 @reduction_sub_lhs(1031; CHECK-INTERLEAVED-SAME: ptr noalias captures(none) [[A:%.*]]) {1032; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]1033; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]1034; CHECK-INTERLEAVED:       [[VECTOR_PH]]:1035; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]1036; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:1037; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1038; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 3, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]1039; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI2:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]1040; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]1041; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 41042; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 41043; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP1]], align 41044; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD]])1045; CHECK-INTERLEAVED-NEXT:    [[TMP7]] = sub i32 [[VEC_PHI1]], [[TMP4]]1046; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD2]])1047; CHECK-INTERLEAVED-NEXT:    [[TMP5]] = sub i32 [[VEC_PHI2]], [[TMP6]]1048; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 81049; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2561050; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]1051; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:1052; CHECK-INTERLEAVED-NEXT:    [[BIN_RDX:%.*]] = add i32 [[TMP5]], [[TMP7]]1053; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_END:.*]]1054; CHECK-INTERLEAVED:       [[FOR_END]]:1055; CHECK-INTERLEAVED-NEXT:    ret i32 [[BIN_RDX]]1056;1057entry:1058  br label %for.body1059 1060for.body:                                         ; preds = %entry, %for.body1061  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]1062  %x.05 = phi i32 [ %sub, %for.body ], [ 3, %entry ]1063  %arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv1064  %l0 = load i32, ptr %arrayidx, align 41065  %sub = sub nsw i32 %x.05, %l01066  %indvars.iv.next = add i64 %indvars.iv, 11067  %lftr.wideiv = trunc i64 %indvars.iv.next to i321068  %exitcond = icmp eq i32 %lftr.wideiv, 2561069  br i1 %exitcond, label %for.end, label %for.body1070 1071for.end:                                          ; preds = %for.body, %entry1072  %x.0.lcssa = phi i32 [ %sub, %for.body ]1073  ret i32 %x.0.lcssa1074}1075 1076; Conditional reductions with multi-input phis.1077define float @reduction_conditional(ptr %A, ptr %B, ptr %C, float %S) {1078; CHECK-LABEL: define float @reduction_conditional(1079; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], float [[S:%.*]]) {1080; CHECK-NEXT:  [[ENTRY:.*:]]1081; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]1082; CHECK:       [[VECTOR_PH]]:1083; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x float> zeroinitializer, float [[S]], i32 01084; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]1085; CHECK:       [[VECTOR_BODY]]:1086; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1087; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <4 x float> [ [[TMP0]], %[[VECTOR_PH]] ], [ [[PREDPHI3:%.*]], %[[VECTOR_BODY]] ]1088; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]]1089; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP1]], align 41090; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDEX]]1091; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP2]], align 41092; CHECK-NEXT:    [[TMP3:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD1]]1093; CHECK-NEXT:    [[TMP4:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD1]], splat (float 1.000000e+00)1094; CHECK-NEXT:    [[TMP8:%.*]] = xor <4 x i1> [[TMP4]], splat (i1 true)1095; CHECK-NEXT:    [[TMP6:%.*]] = fcmp ule <4 x float> [[WIDE_LOAD]], splat (float 2.000000e+00)1096; CHECK-NEXT:    [[TMP7:%.*]] = fadd fast <4 x float> [[VEC_PHI]], [[WIDE_LOAD1]]1097; CHECK-NEXT:    [[TMP5:%.*]] = select <4 x i1> [[TMP3]], <4 x i1> [[TMP4]], <4 x i1> zeroinitializer1098; CHECK-NEXT:    [[TMP9:%.*]] = fadd fast <4 x float> [[VEC_PHI]], [[WIDE_LOAD]]1099; CHECK-NEXT:    [[TMP10:%.*]] = select <4 x i1> [[TMP8]], <4 x i1> [[TMP6]], <4 x i1> zeroinitializer1100; CHECK-NEXT:    [[TMP11:%.*]] = select <4 x i1> [[TMP3]], <4 x i1> [[TMP10]], <4 x i1> zeroinitializer1101; CHECK-NEXT:    [[PREDPHI:%.*]] = select <4 x i1> [[TMP11]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP7]]1102; CHECK-NEXT:    [[PREDPHI2:%.*]] = select <4 x i1> [[TMP5]], <4 x float> [[TMP9]], <4 x float> [[PREDPHI]]1103; CHECK-NEXT:    [[PREDPHI3]] = select <4 x i1> [[TMP3]], <4 x float> [[PREDPHI2]], <4 x float> [[VEC_PHI]]1104; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 41105; CHECK-NEXT:    [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1281106; CHECK-NEXT:    br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]1107; CHECK:       [[MIDDLE_BLOCK]]:1108; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[PREDPHI3]])1109; CHECK-NEXT:    br label %[[FOR_END:.*]]1110; CHECK:       [[FOR_END]]:1111; CHECK-NEXT:    ret float [[TMP13]]1112;1113; CHECK-INTERLEAVED-LABEL: define float @reduction_conditional(1114; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], float [[S:%.*]]) {1115; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]1116; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]1117; CHECK-INTERLEAVED:       [[VECTOR_PH]]:1118; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = insertelement <4 x float> zeroinitializer, float [[S]], i32 01119; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]1120; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:1121; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1122; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi <4 x float> [ [[TMP0]], %[[VECTOR_PH]] ], [ [[PREDPHI6:%.*]], %[[VECTOR_BODY]] ]1123; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi <4 x float> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[PREDPHI9:%.*]], %[[VECTOR_BODY]] ]1124; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]]1125; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i64 41126; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP1]], align 41127; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x float>, ptr [[TMP2]], align 41128; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDEX]]1129; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i64 41130; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x float>, ptr [[TMP3]], align 41131; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP4]], align 41132; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD3]]1133; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD2]], [[WIDE_LOAD4]]1134; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD3]], splat (float 1.000000e+00)1135; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD4]], splat (float 1.000000e+00)1136; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = xor <4 x i1> [[TMP7]], splat (i1 true)1137; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = xor <4 x i1> [[TMP8]], splat (i1 true)1138; CHECK-INTERLEAVED-NEXT:    [[TMP11:%.*]] = fcmp ule <4 x float> [[WIDE_LOAD]], splat (float 2.000000e+00)1139; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = fcmp ule <4 x float> [[WIDE_LOAD2]], splat (float 2.000000e+00)1140; CHECK-INTERLEAVED-NEXT:    [[TMP13:%.*]] = fadd fast <4 x float> [[VEC_PHI]], [[WIDE_LOAD3]]1141; CHECK-INTERLEAVED-NEXT:    [[TMP14:%.*]] = fadd fast <4 x float> [[VEC_PHI1]], [[WIDE_LOAD4]]1142; CHECK-INTERLEAVED-NEXT:    [[TMP15:%.*]] = select <4 x i1> [[TMP5]], <4 x i1> [[TMP7]], <4 x i1> zeroinitializer1143; CHECK-INTERLEAVED-NEXT:    [[TMP16:%.*]] = select <4 x i1> [[TMP6]], <4 x i1> [[TMP8]], <4 x i1> zeroinitializer1144; CHECK-INTERLEAVED-NEXT:    [[TMP17:%.*]] = fadd fast <4 x float> [[VEC_PHI]], [[WIDE_LOAD]]1145; CHECK-INTERLEAVED-NEXT:    [[TMP18:%.*]] = fadd fast <4 x float> [[VEC_PHI1]], [[WIDE_LOAD2]]1146; CHECK-INTERLEAVED-NEXT:    [[TMP19:%.*]] = select <4 x i1> [[TMP9]], <4 x i1> [[TMP11]], <4 x i1> zeroinitializer1147; CHECK-INTERLEAVED-NEXT:    [[TMP21:%.*]] = select <4 x i1> [[TMP10]], <4 x i1> [[TMP12]], <4 x i1> zeroinitializer1148; CHECK-INTERLEAVED-NEXT:    [[TMP20:%.*]] = select <4 x i1> [[TMP5]], <4 x i1> [[TMP19]], <4 x i1> zeroinitializer1149; CHECK-INTERLEAVED-NEXT:    [[TMP22:%.*]] = select <4 x i1> [[TMP6]], <4 x i1> [[TMP21]], <4 x i1> zeroinitializer1150; CHECK-INTERLEAVED-NEXT:    [[PREDPHI:%.*]] = select <4 x i1> [[TMP20]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP13]]1151; CHECK-INTERLEAVED-NEXT:    [[PREDPHI5:%.*]] = select <4 x i1> [[TMP15]], <4 x float> [[TMP17]], <4 x float> [[PREDPHI]]1152; CHECK-INTERLEAVED-NEXT:    [[PREDPHI6]] = select <4 x i1> [[TMP5]], <4 x float> [[PREDPHI5]], <4 x float> [[VEC_PHI]]1153; CHECK-INTERLEAVED-NEXT:    [[PREDPHI7:%.*]] = select <4 x i1> [[TMP22]], <4 x float> [[VEC_PHI1]], <4 x float> [[TMP14]]1154; CHECK-INTERLEAVED-NEXT:    [[PREDPHI8:%.*]] = select <4 x i1> [[TMP16]], <4 x float> [[TMP18]], <4 x float> [[PREDPHI7]]1155; CHECK-INTERLEAVED-NEXT:    [[PREDPHI9]] = select <4 x i1> [[TMP6]], <4 x float> [[PREDPHI8]], <4 x float> [[VEC_PHI1]]1156; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 81157; CHECK-INTERLEAVED-NEXT:    [[TMP23:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1281158; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]1159; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:1160; CHECK-INTERLEAVED-NEXT:    [[BIN_RDX:%.*]] = fadd fast <4 x float> [[PREDPHI9]], [[PREDPHI6]]1161; CHECK-INTERLEAVED-NEXT:    [[TMP24:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[BIN_RDX]])1162; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_END:.*]]1163; CHECK-INTERLEAVED:       [[FOR_END]]:1164; CHECK-INTERLEAVED-NEXT:    ret float [[TMP24]]1165;1166entry:1167  br label %for.body1168 1169for.body:1170  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ]1171  %sum.033 = phi float [ %S, %entry ], [ %sum.1, %for.inc ]1172  %arrayidx = getelementptr inbounds float, ptr %A, i64 %indvars.iv1173  %l0 = load float, ptr %arrayidx, align 41174  %arrayidx2 = getelementptr inbounds float, ptr %B, i64 %indvars.iv1175  %l1 = load float, ptr %arrayidx2, align 41176  %cmp3 = fcmp ogt float %l0, %l11177  br i1 %cmp3, label %if.then, label %for.inc1178 1179if.then:1180  %cmp6 = fcmp ogt float %l1, 1.000000e+001181  br i1 %cmp6, label %if.then8, label %if.else1182 1183if.then8:1184  %add = fadd fast float %sum.033, %l01185  br label %for.inc1186 1187if.else:1188  %cmp14 = fcmp ogt float %l0, 2.000000e+001189  br i1 %cmp14, label %if.then16, label %for.inc1190 1191if.then16:1192  %add19 = fadd fast float %sum.033, %l11193  br label %for.inc1194 1195for.inc:1196  %sum.1 = phi float [ %add, %if.then8 ], [ %add19, %if.then16 ], [ %sum.033, %if.else ], [ %sum.033, %for.body ]1197  %indvars.iv.next = add i64 %indvars.iv, 11198  %lftr.wideiv = trunc i64 %indvars.iv.next to i321199  %exitcond = icmp ne i32 %lftr.wideiv, 1281200  br i1 %exitcond, label %for.body, label %for.end1201 1202for.end:1203  %sum.1.lcssa = phi float [ %sum.1, %for.inc ]1204  ret float %sum.1.lcssa1205}1206 1207define i32 @reduction_sum_multiuse(ptr noalias nocapture %A, ptr noalias nocapture %B) {1208; CHECK-LABEL: define i32 @reduction_sum_multiuse(1209; CHECK-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {1210; CHECK-NEXT:  [[_LR_PH1:.*]]:1211; CHECK-NEXT:    br label %[[DOTLR_PH:.*]]1212; CHECK:       [[_LR_PH:.*:]]1213; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[DOTLR_PH]] ], [ 0, %[[_LR_PH1]] ]1214; CHECK-NEXT:    [[SUM_02:%.*]] = phi i32 [ [[L10:%.*]], %[[DOTLR_PH]] ], [ 0, %[[_LR_PH1]] ]1215; CHECK-NEXT:    [[L2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV]]1216; CHECK-NEXT:    [[L3:%.*]] = load i32, ptr [[L2]], align 41217; CHECK-NEXT:    [[L4:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDVARS_IV]]1218; CHECK-NEXT:    [[L5:%.*]] = load i32, ptr [[L4]], align 41219; CHECK-NEXT:    [[L6:%.*]] = trunc i64 [[INDVARS_IV]] to i321220; CHECK-NEXT:    [[L7:%.*]] = add i32 [[SUM_02]], [[L6]]1221; CHECK-NEXT:    [[L8:%.*]] = add i32 [[L7]], [[L3]]1222; CHECK-NEXT:    [[L9:%.*]] = add i32 [[L8]], [[L5]]1223; CHECK-NEXT:    [[L10]] = add i32 [[L8]], [[SUM_02]]1224; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 11225; CHECK-NEXT:    [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i321226; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[LFTR_WIDEIV]], 2561227; CHECK-NEXT:    br i1 [[EXITCOND]], label %[[END:.*]], label %[[DOTLR_PH]]1228; CHECK:       [[END]]:1229; CHECK-NEXT:    [[F1:%.*]] = phi i32 [ [[L10]], %[[DOTLR_PH]] ]1230; CHECK-NEXT:    ret i32 [[F1]]1231;1232; CHECK-INTERLEAVED-LABEL: define i32 @reduction_sum_multiuse(1233; CHECK-INTERLEAVED-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {1234; CHECK-INTERLEAVED-NEXT:  [[_LR_PH1:.*]]:1235; CHECK-INTERLEAVED-NEXT:    br label %[[DOTLR_PH:.*]]1236; CHECK-INTERLEAVED:       [[_LR_PH:.*:]]1237; CHECK-INTERLEAVED-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[DOTLR_PH]] ], [ 0, %[[_LR_PH1]] ]1238; CHECK-INTERLEAVED-NEXT:    [[SUM_02:%.*]] = phi i32 [ [[L10:%.*]], %[[DOTLR_PH]] ], [ 0, %[[_LR_PH1]] ]1239; CHECK-INTERLEAVED-NEXT:    [[L2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV]]1240; CHECK-INTERLEAVED-NEXT:    [[L3:%.*]] = load i32, ptr [[L2]], align 41241; CHECK-INTERLEAVED-NEXT:    [[L4:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDVARS_IV]]1242; CHECK-INTERLEAVED-NEXT:    [[L5:%.*]] = load i32, ptr [[L4]], align 41243; CHECK-INTERLEAVED-NEXT:    [[L6:%.*]] = trunc i64 [[INDVARS_IV]] to i321244; CHECK-INTERLEAVED-NEXT:    [[L7:%.*]] = add i32 [[SUM_02]], [[L6]]1245; CHECK-INTERLEAVED-NEXT:    [[L8:%.*]] = add i32 [[L7]], [[L3]]1246; CHECK-INTERLEAVED-NEXT:    [[L9:%.*]] = add i32 [[L8]], [[L5]]1247; CHECK-INTERLEAVED-NEXT:    [[L10]] = add i32 [[L8]], [[SUM_02]]1248; CHECK-INTERLEAVED-NEXT:    [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 11249; CHECK-INTERLEAVED-NEXT:    [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i321250; CHECK-INTERLEAVED-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[LFTR_WIDEIV]], 2561251; CHECK-INTERLEAVED-NEXT:    br i1 [[EXITCOND]], label %[[END:.*]], label %[[DOTLR_PH]]1252; CHECK-INTERLEAVED:       [[END]]:1253; CHECK-INTERLEAVED-NEXT:    [[F1:%.*]] = phi i32 [ [[L10]], %[[DOTLR_PH]] ]1254; CHECK-INTERLEAVED-NEXT:    ret i32 [[F1]]1255;1256entry:1257  br label %.lr.ph1258 1259.lr.ph:                                           ; preds = %entry, %.lr.ph1260  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %entry ]1261  %sum.02 = phi i32 [ %l10, %.lr.ph ], [ 0, %entry ]1262  %l2 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv1263  %l3 = load i32, ptr %l2, align 41264  %l4 = getelementptr inbounds i32, ptr %B, i64 %indvars.iv1265  %l5 = load i32, ptr %l4, align 41266  %l6 = trunc i64 %indvars.iv to i321267  %l7 = add i32 %sum.02, %l61268  %l8 = add i32 %l7, %l31269  %l9 = add i32 %l8, %l51270  %l10 = add i32 %l8, %sum.021271  %indvars.iv.next = add i64 %indvars.iv, 11272  %lftr.wideiv = trunc i64 %indvars.iv.next to i321273  %exitcond = icmp eq i32 %lftr.wideiv, 2561274  br i1 %exitcond, label %end, label %.lr.ph1275 1276end:1277  %f1 = phi i32 [ %l10, %.lr.ph ]1278  ret i32 %f11279}1280 1281; Predicated loop, cannot (yet) use in-loop reductions.1282define i32 @reduction_predicated(ptr noalias nocapture %A, ptr noalias nocapture %B) {1283; CHECK-LABEL: define i32 @reduction_predicated(1284; CHECK-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {1285; CHECK-NEXT:  [[ENTRY:.*:]]1286; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]1287; CHECK:       [[VECTOR_PH]]:1288; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]1289; CHECK:       [[VECTOR_BODY]]:1290; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1291; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]1292; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]1293; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]1294; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 41295; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]1296; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 41297; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[VEC_IND]])1298; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[VEC_PHI]], [[TMP2]]1299; CHECK-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD]])1300; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[TMP3]], [[TMP4]]1301; CHECK-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD1]])1302; CHECK-NEXT:    [[TMP7]] = add i32 [[TMP5]], [[TMP6]]1303; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 41304; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)1305; CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2561306; CHECK-NEXT:    br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]1307; CHECK:       [[MIDDLE_BLOCK]]:1308; CHECK-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]1309; CHECK:       [[__CRIT_EDGE:.*:]]1310; CHECK-NEXT:    ret i32 [[TMP7]]1311;1312; CHECK-INTERLEAVED-LABEL: define i32 @reduction_predicated(1313; CHECK-INTERLEAVED-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {1314; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]1315; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]1316; CHECK-INTERLEAVED:       [[VECTOR_PH]]:1317; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]1318; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:1319; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1320; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]1321; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ]1322; CHECK-INTERLEAVED-NEXT:    [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]1323; CHECK-INTERLEAVED-NEXT:    [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4)1324; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]1325; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 41326; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 41327; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP1]], align 41328; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]1329; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 41330; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP2]], align 41331; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP3]], align 41332; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[VEC_IND]])1333; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = add i32 [[VEC_PHI]], [[TMP4]]1334; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[STEP_ADD]])1335; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = add i32 [[VEC_PHI1]], [[TMP6]]1336; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD]])1337; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = add i32 [[TMP5]], [[TMP8]]1338; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD2]])1339; CHECK-INTERLEAVED-NEXT:    [[TMP11:%.*]] = add i32 [[TMP7]], [[TMP10]]1340; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD3]])1341; CHECK-INTERLEAVED-NEXT:    [[TMP13]] = add i32 [[TMP9]], [[TMP12]]1342; CHECK-INTERLEAVED-NEXT:    [[TMP14:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD4]])1343; CHECK-INTERLEAVED-NEXT:    [[TMP15]] = add i32 [[TMP11]], [[TMP14]]1344; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 81345; CHECK-INTERLEAVED-NEXT:    [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], splat (i32 4)1346; CHECK-INTERLEAVED-NEXT:    [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2561347; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]1348; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:1349; CHECK-INTERLEAVED-NEXT:    [[SUM_0_LCSSA:%.*]] = add i32 [[TMP15]], [[TMP13]]1350; CHECK-INTERLEAVED-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]1351; CHECK-INTERLEAVED:       [[__CRIT_EDGE:.*:]]1352; CHECK-INTERLEAVED-NEXT:    ret i32 [[SUM_0_LCSSA]]1353;1354entry:1355  br label %.lr.ph1356 1357.lr.ph:                                           ; preds = %entry, %.lr.ph1358  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %entry ]1359  %sum.02 = phi i32 [ %l9, %.lr.ph ], [ 0, %entry ]1360  %l2 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv1361  %l3 = load i32, ptr %l2, align 41362  %l4 = getelementptr inbounds i32, ptr %B, i64 %indvars.iv1363  %l5 = load i32, ptr %l4, align 41364  %l6 = trunc i64 %indvars.iv to i321365  %l7 = add i32 %sum.02, %l61366  %l8 = add i32 %l7, %l31367  %l9 = add i32 %l8, %l51368  %indvars.iv.next = add i64 %indvars.iv, 11369  %lftr.wideiv = trunc i64 %indvars.iv.next to i321370  %exitcond = icmp eq i32 %lftr.wideiv, 2561371  br i1 %exitcond, label %._crit_edge, label %.lr.ph, !llvm.loop !61372 1373._crit_edge:                                      ; preds = %.lr.ph1374  %sum.0.lcssa = phi i32 [ %l9, %.lr.ph ]1375  ret i32 %sum.0.lcssa1376}1377 1378define i8 @reduction_add_trunc(ptr noalias nocapture %A) {1379; CHECK-LABEL: define i8 @reduction_add_trunc(1380; CHECK-SAME: ptr noalias captures(none) [[A:%.*]]) {1381; CHECK-NEXT:  [[ENTRY:.*:]]1382; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]1383; CHECK:       [[VECTOR_PH]]:1384; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]1385; CHECK:       [[VECTOR_BODY]]:1386; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1387; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <4 x i32> [ <i32 255, i32 0, i32 0, i32 0>, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]1388; CHECK-NEXT:    [[TMP0:%.*]] = and <4 x i32> [[VEC_PHI]], splat (i32 255)1389; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[INDEX]]1390; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 41391; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i8> [[WIDE_LOAD]] to <4 x i32>1392; CHECK-NEXT:    [[TMP6:%.*]] = add <4 x i32> [[TMP0]], [[TMP2]]1393; CHECK-NEXT:    [[TMP4:%.*]] = trunc <4 x i32> [[TMP6]] to <4 x i8>1394; CHECK-NEXT:    [[TMP5]] = zext <4 x i8> [[TMP4]] to <4 x i32>1395; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 41396; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 2561397; CHECK-NEXT:    br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]1398; CHECK:       [[MIDDLE_BLOCK]]:1399; CHECK-NEXT:    [[TMP7:%.*]] = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> [[TMP4]])1400; CHECK-NEXT:    [[TMP8:%.*]] = zext i8 [[TMP7]] to i321401; CHECK-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]1402; CHECK:       [[__CRIT_EDGE:.*:]]1403; CHECK-NEXT:    [[SUM_0_LCSSA:%.*]] = trunc i32 [[TMP8]] to i81404; CHECK-NEXT:    ret i8 [[SUM_0_LCSSA]]1405;1406; CHECK-INTERLEAVED-LABEL: define i8 @reduction_add_trunc(1407; CHECK-INTERLEAVED-SAME: ptr noalias captures(none) [[A:%.*]]) {1408; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]1409; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]1410; CHECK-INTERLEAVED:       [[VECTOR_PH]]:1411; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]1412; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:1413; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1414; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi <4 x i32> [ <i32 255, i32 0, i32 0, i32 0>, %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ]1415; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]1416; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = and <4 x i32> [[VEC_PHI]], splat (i32 255)1417; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = and <4 x i32> [[VEC_PHI1]], splat (i32 255)1418; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[INDEX]]1419; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 41420; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 41421; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i8>, ptr [[TMP2]], align 41422; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = zext <4 x i8> [[WIDE_LOAD]] to <4 x i32>1423; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = zext <4 x i8> [[WIDE_LOAD2]] to <4 x i32>1424; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = add <4 x i32> [[TMP0]], [[TMP4]]1425; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = add <4 x i32> [[TMP3]], [[TMP12]]1426; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = trunc <4 x i32> [[TMP6]] to <4 x i8>1427; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = trunc <4 x i32> [[TMP7]] to <4 x i8>1428; CHECK-INTERLEAVED-NEXT:    [[TMP10]] = zext <4 x i8> [[TMP8]] to <4 x i32>1429; CHECK-INTERLEAVED-NEXT:    [[TMP11]] = zext <4 x i8> [[TMP9]] to <4 x i32>1430; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 81431; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], 2561432; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]1433; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:1434; CHECK-INTERLEAVED-NEXT:    [[BIN_RDX:%.*]] = add <4 x i8> [[TMP9]], [[TMP8]]1435; CHECK-INTERLEAVED-NEXT:    [[TMP13:%.*]] = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> [[BIN_RDX]])1436; CHECK-INTERLEAVED-NEXT:    [[TMP14:%.*]] = zext i8 [[TMP13]] to i321437; CHECK-INTERLEAVED-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]1438; CHECK-INTERLEAVED:       [[__CRIT_EDGE:.*:]]1439; CHECK-INTERLEAVED-NEXT:    [[SUM_0_LCSSA:%.*]] = trunc i32 [[TMP14]] to i81440; CHECK-INTERLEAVED-NEXT:    ret i8 [[SUM_0_LCSSA]]1441;1442entry:1443  br label %.lr.ph1444 1445.lr.ph:                                           ; preds = %entry, %.lr.ph1446  %indvars.iv = phi i32 [ %indvars.iv.next, %.lr.ph ], [ 0, %entry ]1447  %sum.02p = phi i32 [ %l9, %.lr.ph ], [ 255, %entry ]1448  %sum.02 = and i32 %sum.02p, 2551449  %l2 = getelementptr inbounds i8, ptr %A, i32 %indvars.iv1450  %l3 = load i8, ptr %l2, align 41451  %l3e = zext i8 %l3 to i321452  %l9 = add i32 %sum.02, %l3e1453  %indvars.iv.next = add i32 %indvars.iv, 11454  %exitcond = icmp eq i32 %indvars.iv.next, 2561455  br i1 %exitcond, label %._crit_edge, label %.lr.ph1456 1457._crit_edge:                                      ; preds = %.lr.ph1458  %sum.0.lcssa = phi i32 [ %l9, %.lr.ph ]1459  %ret = trunc i32 %sum.0.lcssa to i81460  ret i8 %ret1461}1462 1463 1464define i8 @reduction_and_trunc(ptr noalias nocapture %A) {1465; CHECK-LABEL: define i8 @reduction_and_trunc(1466; CHECK-SAME: ptr noalias captures(none) [[A:%.*]]) {1467; CHECK-NEXT:  [[ENTRY:.*:]]1468; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]1469; CHECK:       [[VECTOR_PH]]:1470; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]1471; CHECK:       [[VECTOR_BODY]]:1472; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1473; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <4 x i32> [ <i32 255, i32 -1, i32 -1, i32 -1>, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]1474; CHECK-NEXT:    [[TMP0:%.*]] = and <4 x i32> [[VEC_PHI]], splat (i32 255)1475; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[INDEX]]1476; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 41477; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i8> [[WIDE_LOAD]] to <4 x i32>1478; CHECK-NEXT:    [[TMP6:%.*]] = and <4 x i32> [[TMP0]], [[TMP2]]1479; CHECK-NEXT:    [[TMP4:%.*]] = trunc <4 x i32> [[TMP6]] to <4 x i8>1480; CHECK-NEXT:    [[TMP5]] = zext <4 x i8> [[TMP4]] to <4 x i32>1481; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 41482; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 2561483; CHECK-NEXT:    br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]1484; CHECK:       [[MIDDLE_BLOCK]]:1485; CHECK-NEXT:    [[TMP7:%.*]] = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> [[TMP4]])1486; CHECK-NEXT:    [[TMP8:%.*]] = zext i8 [[TMP7]] to i321487; CHECK-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]1488; CHECK:       [[__CRIT_EDGE:.*:]]1489; CHECK-NEXT:    [[SUM_0_LCSSA:%.*]] = trunc i32 [[TMP8]] to i81490; CHECK-NEXT:    ret i8 [[SUM_0_LCSSA]]1491;1492; CHECK-INTERLEAVED-LABEL: define i8 @reduction_and_trunc(1493; CHECK-INTERLEAVED-SAME: ptr noalias captures(none) [[A:%.*]]) {1494; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]1495; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]1496; CHECK-INTERLEAVED:       [[VECTOR_PH]]:1497; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]1498; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:1499; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1500; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi <4 x i32> [ <i32 255, i32 -1, i32 -1, i32 -1>, %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ]1501; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi <4 x i32> [ splat (i32 -1), %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]1502; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = and <4 x i32> [[VEC_PHI]], splat (i32 255)1503; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = and <4 x i32> [[VEC_PHI1]], splat (i32 255)1504; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[INDEX]]1505; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 41506; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 41507; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i8>, ptr [[TMP2]], align 41508; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = zext <4 x i8> [[WIDE_LOAD]] to <4 x i32>1509; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = zext <4 x i8> [[WIDE_LOAD2]] to <4 x i32>1510; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = and <4 x i32> [[TMP0]], [[TMP4]]1511; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = and <4 x i32> [[TMP3]], [[TMP12]]1512; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = trunc <4 x i32> [[TMP6]] to <4 x i8>1513; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = trunc <4 x i32> [[TMP7]] to <4 x i8>1514; CHECK-INTERLEAVED-NEXT:    [[TMP10]] = zext <4 x i8> [[TMP8]] to <4 x i32>1515; CHECK-INTERLEAVED-NEXT:    [[TMP11]] = zext <4 x i8> [[TMP9]] to <4 x i32>1516; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 81517; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], 2561518; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]1519; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:1520; CHECK-INTERLEAVED-NEXT:    [[BIN_RDX:%.*]] = and <4 x i8> [[TMP9]], [[TMP8]]1521; CHECK-INTERLEAVED-NEXT:    [[TMP13:%.*]] = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> [[BIN_RDX]])1522; CHECK-INTERLEAVED-NEXT:    [[TMP14:%.*]] = zext i8 [[TMP13]] to i321523; CHECK-INTERLEAVED-NEXT:    br [[DOT_CRIT_EDGE:label %.*]]1524; CHECK-INTERLEAVED:       [[__CRIT_EDGE:.*:]]1525; CHECK-INTERLEAVED-NEXT:    [[SUM_0_LCSSA:%.*]] = trunc i32 [[TMP14]] to i81526; CHECK-INTERLEAVED-NEXT:    ret i8 [[SUM_0_LCSSA]]1527;1528entry:1529  br label %.lr.ph1530 1531.lr.ph:                                           ; preds = %entry, %.lr.ph1532  %indvars.iv = phi i32 [ %indvars.iv.next, %.lr.ph ], [ 0, %entry ]1533  %sum.02p = phi i32 [ %l9, %.lr.ph ], [ 255, %entry ]1534  %sum.02 = and i32 %sum.02p, 2551535  %l2 = getelementptr inbounds i8, ptr %A, i32 %indvars.iv1536  %l3 = load i8, ptr %l2, align 41537  %l3e = zext i8 %l3 to i321538  %l9 = and i32 %sum.02, %l3e1539  %indvars.iv.next = add i32 %indvars.iv, 11540  %exitcond = icmp eq i32 %indvars.iv.next, 2561541  br i1 %exitcond, label %._crit_edge, label %.lr.ph1542 1543._crit_edge:                                      ; preds = %.lr.ph1544  %sum.0.lcssa = phi i32 [ %l9, %.lr.ph ]1545  %ret = trunc i32 %sum.0.lcssa to i81546  ret i8 %ret1547}1548 1549; Test case when loop has a call to the llvm.fmuladd intrinsic.1550define float @reduction_fmuladd(ptr %a, ptr %b, i64 %n) {1551; CHECK-LABEL: define float @reduction_fmuladd(1552; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) {1553; CHECK-NEXT:  [[ENTRY:.*]]:1554; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 41555; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]1556; CHECK:       [[VECTOR_PH]]:1557; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N]], 41558; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]1559; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]1560; CHECK:       [[VECTOR_BODY]]:1561; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1562; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]1563; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]]1564; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 41565; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDEX]]1566; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP1]], align 41567; CHECK-NEXT:    [[TMP2:%.*]] = fmul <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD1]]1568; CHECK-NEXT:    [[TMP3:%.*]] = call float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP2]])1569; CHECK-NEXT:    [[TMP4]] = fadd float [[VEC_PHI]], [[TMP3]]1570; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 41571; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]1572; CHECK-NEXT:    br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]1573; CHECK:       [[MIDDLE_BLOCK]]:1574; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]1575; CHECK-NEXT:    br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]]1576; CHECK:       [[SCALAR_PH]]:1577; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]1578; CHECK-NEXT:    [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]1579; CHECK-NEXT:    br label %[[FOR_BODY:.*]]1580; CHECK:       [[FOR_BODY]]:1581; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]1582; CHECK-NEXT:    [[SUM_07:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[MULADD:%.*]], %[[FOR_BODY]] ]1583; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]]1584; CHECK-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 41585; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]1586; CHECK-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX2]], align 41587; CHECK-NEXT:    [[MULADD]] = tail call float @llvm.fmuladd.f32(float [[TMP6]], float [[TMP7]], float [[SUM_07]])1588; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11589; CHECK-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]1590; CHECK-NEXT:    br i1 [[EXITCOND_NOT]], label %[[FOR_END]], label %[[FOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]1591; CHECK:       [[FOR_END]]:1592; CHECK-NEXT:    [[MULADD_LCSSA:%.*]] = phi float [ [[MULADD]], %[[FOR_BODY]] ], [ [[TMP4]], %[[MIDDLE_BLOCK]] ]1593; CHECK-NEXT:    ret float [[MULADD_LCSSA]]1594;1595; CHECK-INTERLEAVED-LABEL: define float @reduction_fmuladd(1596; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) {1597; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*]]:1598; CHECK-INTERLEAVED-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 81599; CHECK-INTERLEAVED-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]1600; CHECK-INTERLEAVED:       [[VECTOR_PH]]:1601; CHECK-INTERLEAVED-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N]], 81602; CHECK-INTERLEAVED-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]1603; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]1604; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:1605; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1606; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]1607; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi float [ -0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]1608; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]]1609; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds float, ptr [[TMP0]], i64 41610; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 41611; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x float>, ptr [[TMP1]], align 41612; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDEX]]1613; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 41614; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x float>, ptr [[TMP2]], align 41615; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP3]], align 41616; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = fmul <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD3]]1617; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = fmul <4 x float> [[WIDE_LOAD2]], [[WIDE_LOAD4]]1618; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = call float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP4]])1619; CHECK-INTERLEAVED-NEXT:    [[TMP7]] = fadd float [[VEC_PHI]], [[TMP6]]1620; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = call float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP5]])1621; CHECK-INTERLEAVED-NEXT:    [[TMP9]] = fadd float [[VEC_PHI1]], [[TMP8]]1622; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 81623; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]1624; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]1625; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:1626; CHECK-INTERLEAVED-NEXT:    [[BIN_RDX:%.*]] = fadd float [[TMP9]], [[TMP7]]1627; CHECK-INTERLEAVED-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]1628; CHECK-INTERLEAVED-NEXT:    br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]]1629; CHECK-INTERLEAVED:       [[SCALAR_PH]]:1630; CHECK-INTERLEAVED-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]1631; CHECK-INTERLEAVED-NEXT:    [[BC_MERGE_RDX:%.*]] = phi float [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]1632; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_BODY:.*]]1633; CHECK-INTERLEAVED:       [[FOR_BODY]]:1634; CHECK-INTERLEAVED-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]1635; CHECK-INTERLEAVED-NEXT:    [[SUM_07:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[MULADD:%.*]], %[[FOR_BODY]] ]1636; CHECK-INTERLEAVED-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]]1637; CHECK-INTERLEAVED-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX]], align 41638; CHECK-INTERLEAVED-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]1639; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX2]], align 41640; CHECK-INTERLEAVED-NEXT:    [[MULADD]] = tail call float @llvm.fmuladd.f32(float [[TMP11]], float [[TMP12]], float [[SUM_07]])1641; CHECK-INTERLEAVED-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11642; CHECK-INTERLEAVED-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]1643; CHECK-INTERLEAVED-NEXT:    br i1 [[EXITCOND_NOT]], label %[[FOR_END]], label %[[FOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]1644; CHECK-INTERLEAVED:       [[FOR_END]]:1645; CHECK-INTERLEAVED-NEXT:    [[MULADD_LCSSA:%.*]] = phi float [ [[MULADD]], %[[FOR_BODY]] ], [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ]1646; CHECK-INTERLEAVED-NEXT:    ret float [[MULADD_LCSSA]]1647;1648 1649entry:1650  br label %for.body1651 1652for.body:1653  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]1654  %sum.07 = phi float [ 0.000000e+00, %entry ], [ %muladd, %for.body ]1655  %arrayidx = getelementptr inbounds float, ptr %a, i64 %iv1656  %0 = load float, ptr %arrayidx, align 41657  %arrayidx2 = getelementptr inbounds float, ptr %b, i64 %iv1658  %1 = load float, ptr %arrayidx2, align 41659  %muladd = tail call float @llvm.fmuladd.f32(float %0, float %1, float %sum.07)1660  %iv.next = add nuw nsw i64 %iv, 11661  %exitcond.not = icmp eq i64 %iv.next, %n1662  br i1 %exitcond.not, label %for.end, label %for.body1663 1664for.end:1665  ret float %muladd1666}1667 1668define float @reduction_fmuladd_recurrence_first_arg(ptr %a, ptr %b, i64 %n) {1669; CHECK-LABEL: define float @reduction_fmuladd_recurrence_first_arg(1670; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) {1671; CHECK-NEXT:  [[ENTRY:.*]]:1672; CHECK-NEXT:    br label %[[FOR_BODY:.*]]1673; CHECK:       [[FOR_BODY]]:1674; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]1675; CHECK-NEXT:    [[SUM_07:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[MULADD:%.*]], %[[FOR_BODY]] ]1676; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]]1677; CHECK-NEXT:    [[TMP0:%.*]] = load float, ptr [[ARRAYIDX]], align 41678; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]1679; CHECK-NEXT:    [[TMP1:%.*]] = load float, ptr [[ARRAYIDX2]], align 41680; CHECK-NEXT:    [[MULADD]] = tail call float @llvm.fmuladd.f32(float [[SUM_07]], float [[TMP0]], float [[TMP1]])1681; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11682; CHECK-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]1683; CHECK-NEXT:    br i1 [[EXITCOND_NOT]], label %[[FOR_END:.*]], label %[[FOR_BODY]]1684; CHECK:       [[FOR_END]]:1685; CHECK-NEXT:    [[MULADD_LCSSA:%.*]] = phi float [ [[MULADD]], %[[FOR_BODY]] ]1686; CHECK-NEXT:    ret float [[MULADD_LCSSA]]1687;1688; CHECK-INTERLEAVED-LABEL: define float @reduction_fmuladd_recurrence_first_arg(1689; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) {1690; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*]]:1691; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_BODY:.*]]1692; CHECK-INTERLEAVED:       [[FOR_BODY]]:1693; CHECK-INTERLEAVED-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]1694; CHECK-INTERLEAVED-NEXT:    [[SUM_07:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[MULADD:%.*]], %[[FOR_BODY]] ]1695; CHECK-INTERLEAVED-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]]1696; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = load float, ptr [[ARRAYIDX]], align 41697; CHECK-INTERLEAVED-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]1698; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = load float, ptr [[ARRAYIDX2]], align 41699; CHECK-INTERLEAVED-NEXT:    [[MULADD]] = tail call float @llvm.fmuladd.f32(float [[SUM_07]], float [[TMP0]], float [[TMP1]])1700; CHECK-INTERLEAVED-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11701; CHECK-INTERLEAVED-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]1702; CHECK-INTERLEAVED-NEXT:    br i1 [[EXITCOND_NOT]], label %[[FOR_END:.*]], label %[[FOR_BODY]]1703; CHECK-INTERLEAVED:       [[FOR_END]]:1704; CHECK-INTERLEAVED-NEXT:    [[MULADD_LCSSA:%.*]] = phi float [ [[MULADD]], %[[FOR_BODY]] ]1705; CHECK-INTERLEAVED-NEXT:    ret float [[MULADD_LCSSA]]1706;1707 1708entry:1709  br label %for.body1710 1711for.body:1712  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]1713  %sum.07 = phi float [ 0.000000e+00, %entry ], [ %muladd, %for.body ]1714  %arrayidx = getelementptr inbounds float, ptr %a, i64 %iv1715  %0 = load float, ptr %arrayidx, align 41716  %arrayidx2 = getelementptr inbounds float, ptr %b, i64 %iv1717  %1 = load float, ptr %arrayidx2, align 41718  %muladd = tail call float @llvm.fmuladd.f32(float %sum.07, float %0, float %1)1719  %iv.next = add nuw nsw i64 %iv, 11720  %exitcond.not = icmp eq i64 %iv.next, %n1721  br i1 %exitcond.not, label %for.end, label %for.body1722 1723for.end:1724  ret float %muladd1725}1726 1727define float @reduction_fmuladd_recurrence_second_arg(ptr %a, ptr %b, i64 %n) {1728; CHECK-LABEL: define float @reduction_fmuladd_recurrence_second_arg(1729; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) {1730; CHECK-NEXT:  [[ENTRY:.*]]:1731; CHECK-NEXT:    br label %[[FOR_BODY:.*]]1732; CHECK:       [[FOR_BODY]]:1733; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]1734; CHECK-NEXT:    [[SUM_07:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[MULADD:%.*]], %[[FOR_BODY]] ]1735; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]]1736; CHECK-NEXT:    [[TMP0:%.*]] = load float, ptr [[ARRAYIDX]], align 41737; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]1738; CHECK-NEXT:    [[TMP1:%.*]] = load float, ptr [[ARRAYIDX2]], align 41739; CHECK-NEXT:    [[MULADD]] = tail call float @llvm.fmuladd.f32(float [[TMP0]], float [[SUM_07]], float [[TMP1]])1740; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11741; CHECK-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]1742; CHECK-NEXT:    br i1 [[EXITCOND_NOT]], label %[[FOR_END:.*]], label %[[FOR_BODY]]1743; CHECK:       [[FOR_END]]:1744; CHECK-NEXT:    [[MULADD_LCSSA:%.*]] = phi float [ [[MULADD]], %[[FOR_BODY]] ]1745; CHECK-NEXT:    ret float [[MULADD_LCSSA]]1746;1747; CHECK-INTERLEAVED-LABEL: define float @reduction_fmuladd_recurrence_second_arg(1748; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) {1749; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*]]:1750; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_BODY:.*]]1751; CHECK-INTERLEAVED:       [[FOR_BODY]]:1752; CHECK-INTERLEAVED-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]1753; CHECK-INTERLEAVED-NEXT:    [[SUM_07:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[MULADD:%.*]], %[[FOR_BODY]] ]1754; CHECK-INTERLEAVED-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]]1755; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = load float, ptr [[ARRAYIDX]], align 41756; CHECK-INTERLEAVED-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]1757; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = load float, ptr [[ARRAYIDX2]], align 41758; CHECK-INTERLEAVED-NEXT:    [[MULADD]] = tail call float @llvm.fmuladd.f32(float [[TMP0]], float [[SUM_07]], float [[TMP1]])1759; CHECK-INTERLEAVED-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11760; CHECK-INTERLEAVED-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]1761; CHECK-INTERLEAVED-NEXT:    br i1 [[EXITCOND_NOT]], label %[[FOR_END:.*]], label %[[FOR_BODY]]1762; CHECK-INTERLEAVED:       [[FOR_END]]:1763; CHECK-INTERLEAVED-NEXT:    [[MULADD_LCSSA:%.*]] = phi float [ [[MULADD]], %[[FOR_BODY]] ]1764; CHECK-INTERLEAVED-NEXT:    ret float [[MULADD_LCSSA]]1765;1766 1767entry:1768  br label %for.body1769 1770for.body:1771  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]1772  %sum.07 = phi float [ 0.000000e+00, %entry ], [ %muladd, %for.body ]1773  %arrayidx = getelementptr inbounds float, ptr %a, i64 %iv1774  %0 = load float, ptr %arrayidx, align 41775  %arrayidx2 = getelementptr inbounds float, ptr %b, i64 %iv1776  %1 = load float, ptr %arrayidx2, align 41777  %muladd = tail call float @llvm.fmuladd.f32(float %0, float %sum.07, float %1)1778  %iv.next = add nuw nsw i64 %iv, 11779  %exitcond.not = icmp eq i64 %iv.next, %n1780  br i1 %exitcond.not, label %for.end, label %for.body1781 1782for.end:1783  ret float %muladd1784}1785 1786define float @reduction_fmuladd_blend(ptr %a, ptr %b, i64 %n, i1 %c) {1787; CHECK-LABEL: define float @reduction_fmuladd_blend(1788; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]], i1 [[C:%.*]]) {1789; CHECK-NEXT:  [[ENTRY:.*]]:1790; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 41791; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]1792; CHECK:       [[VECTOR_PH]]:1793; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N]], 41794; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]1795; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[C]], i64 01796; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer1797; CHECK-NEXT:    [[TMP1:%.*]] = xor <4 x i1> [[BROADCAST_SPLAT]], splat (i1 true)1798; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]1799; CHECK:       [[VECTOR_BODY]]:1800; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1801; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]1802; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]]1803; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP2]], align 41804; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDEX]]1805; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP3]], align 41806; CHECK-NEXT:    [[TMP4:%.*]] = fmul <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD1]]1807; CHECK-NEXT:    [[TMP5:%.*]] = select <4 x i1> [[TMP1]], <4 x float> [[TMP4]], <4 x float> splat (float -0.000000e+00)1808; CHECK-NEXT:    [[TMP6:%.*]] = call float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP5]])1809; CHECK-NEXT:    [[TMP7]] = fadd float [[VEC_PHI]], [[TMP6]]1810; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 41811; CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]1812; CHECK-NEXT:    br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]1813; CHECK:       [[MIDDLE_BLOCK]]:1814; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]1815; CHECK-NEXT:    br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]1816; CHECK:       [[SCALAR_PH]]:1817; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]1818; CHECK-NEXT:    [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]1819; CHECK-NEXT:    br label %[[LOOP_HEADER:.*]]1820; CHECK:       [[LOOP_HEADER]]:1821; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]1822; CHECK-NEXT:    [[SUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LATCH]] ]1823; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]]1824; CHECK-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX2]], align 41825; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]1826; CHECK-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX]], align 41827; CHECK-NEXT:    br i1 [[C]], label %[[IF:.*]], label %[[ELSE:.*]]1828; CHECK:       [[IF]]:1829; CHECK-NEXT:    br label %[[LATCH]]1830; CHECK:       [[ELSE]]:1831; CHECK-NEXT:    [[MULADD:%.*]] = tail call float @llvm.fmuladd.f32(float [[TMP9]], float [[TMP10]], float [[SUM]])1832; CHECK-NEXT:    br label %[[LATCH]]1833; CHECK:       [[LATCH]]:1834; CHECK-NEXT:    [[SUM_NEXT]] = phi float [ [[SUM]], %[[IF]] ], [ [[MULADD]], %[[ELSE]] ]1835; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11836; CHECK-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]1837; CHECK-NEXT:    br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP22:![0-9]+]]1838; CHECK:       [[EXIT]]:1839; CHECK-NEXT:    [[SUM_NEXT_LCSSA:%.*]] = phi float [ [[SUM_NEXT]], %[[LATCH]] ], [ [[TMP7]], %[[MIDDLE_BLOCK]] ]1840; CHECK-NEXT:    ret float [[SUM_NEXT_LCSSA]]1841;1842; CHECK-INTERLEAVED-LABEL: define float @reduction_fmuladd_blend(1843; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]], i1 [[C:%.*]]) {1844; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*]]:1845; CHECK-INTERLEAVED-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 81846; CHECK-INTERLEAVED-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]1847; CHECK-INTERLEAVED:       [[VECTOR_PH]]:1848; CHECK-INTERLEAVED-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N]], 81849; CHECK-INTERLEAVED-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]1850; CHECK-INTERLEAVED-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[C]], i64 01851; CHECK-INTERLEAVED-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer1852; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = xor <4 x i1> [[BROADCAST_SPLAT]], splat (i1 true)1853; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]1854; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:1855; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1856; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ]1857; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi float [ -0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]1858; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]]1859; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 41860; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP2]], align 41861; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x float>, ptr [[TMP3]], align 41862; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDEX]]1863; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 41864; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x float>, ptr [[TMP4]], align 41865; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP5]], align 41866; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = fmul <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD3]]1867; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = fmul <4 x float> [[WIDE_LOAD2]], [[WIDE_LOAD4]]1868; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = select <4 x i1> [[TMP1]], <4 x float> [[TMP6]], <4 x float> splat (float -0.000000e+00)1869; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = call float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP8]])1870; CHECK-INTERLEAVED-NEXT:    [[TMP10]] = fadd float [[VEC_PHI]], [[TMP9]]1871; CHECK-INTERLEAVED-NEXT:    [[TMP11:%.*]] = select <4 x i1> [[TMP1]], <4 x float> [[TMP7]], <4 x float> splat (float -0.000000e+00)1872; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = call float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP11]])1873; CHECK-INTERLEAVED-NEXT:    [[TMP13]] = fadd float [[VEC_PHI1]], [[TMP12]]1874; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 81875; CHECK-INTERLEAVED-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]1876; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]1877; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:1878; CHECK-INTERLEAVED-NEXT:    [[BIN_RDX:%.*]] = fadd float [[TMP13]], [[TMP10]]1879; CHECK-INTERLEAVED-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]1880; CHECK-INTERLEAVED-NEXT:    br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]1881; CHECK-INTERLEAVED:       [[SCALAR_PH]]:1882; CHECK-INTERLEAVED-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]1883; CHECK-INTERLEAVED-NEXT:    [[BC_MERGE_RDX:%.*]] = phi float [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]1884; CHECK-INTERLEAVED-NEXT:    br label %[[LOOP_HEADER:.*]]1885; CHECK-INTERLEAVED:       [[LOOP_HEADER]]:1886; CHECK-INTERLEAVED-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]1887; CHECK-INTERLEAVED-NEXT:    [[SUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LATCH]] ]1888; CHECK-INTERLEAVED-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]]1889; CHECK-INTERLEAVED-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX2]], align 41890; CHECK-INTERLEAVED-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]]1891; CHECK-INTERLEAVED-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 41892; CHECK-INTERLEAVED-NEXT:    br i1 [[C]], label %[[IF:.*]], label %[[ELSE:.*]]1893; CHECK-INTERLEAVED:       [[IF]]:1894; CHECK-INTERLEAVED-NEXT:    br label %[[LATCH]]1895; CHECK-INTERLEAVED:       [[ELSE]]:1896; CHECK-INTERLEAVED-NEXT:    [[MULADD:%.*]] = tail call float @llvm.fmuladd.f32(float [[TMP15]], float [[TMP16]], float [[SUM]])1897; CHECK-INTERLEAVED-NEXT:    br label %[[LATCH]]1898; CHECK-INTERLEAVED:       [[LATCH]]:1899; CHECK-INTERLEAVED-NEXT:    [[SUM_NEXT]] = phi float [ [[SUM]], %[[IF]] ], [ [[MULADD]], %[[ELSE]] ]1900; CHECK-INTERLEAVED-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11901; CHECK-INTERLEAVED-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]1902; CHECK-INTERLEAVED-NEXT:    br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP22:![0-9]+]]1903; CHECK-INTERLEAVED:       [[EXIT]]:1904; CHECK-INTERLEAVED-NEXT:    [[SUM_NEXT_LCSSA:%.*]] = phi float [ [[SUM_NEXT]], %[[LATCH]] ], [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ]1905; CHECK-INTERLEAVED-NEXT:    ret float [[SUM_NEXT_LCSSA]]1906;1907entry:1908  br label %loop.header1909 1910loop.header:1911  %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ]1912  %sum = phi float [ 0.000000e+00, %entry ], [ %sum.next, %latch ]1913  %arrayidx = getelementptr inbounds float, ptr %a, i64 %iv1914  %0 = load float, ptr %arrayidx, align 41915  %arrayidx2 = getelementptr inbounds float, ptr %b, i64 %iv1916  %1 = load float, ptr %arrayidx2, align 41917  br i1 %c, label %if, label %else1918 1919if:1920  br label %latch1921 1922else:1923  %muladd = tail call float @llvm.fmuladd.f32(float %0, float %1, float %sum)1924  br label %latch1925 1926latch:1927  %sum.next = phi float [ %sum, %if ], [ %muladd, %else ]1928  %iv.next = add nuw nsw i64 %iv, 11929  %exitcond.not = icmp eq i64 %iv.next, %n1930  br i1 %exitcond.not, label %exit, label %loop.header1931 1932exit:1933  ret float %sum.next1934}1935 1936; This case was previously failing verification due to the mask for the1937; reduction being created after the reduction.1938define i32 @predicated_not_dominates_reduction(ptr nocapture noundef readonly %h, i32 noundef %i) {1939; CHECK-LABEL: define i32 @predicated_not_dominates_reduction(1940; CHECK-SAME: ptr noundef readonly captures(none) [[H:%.*]], i32 noundef [[I:%.*]]) {1941; CHECK-NEXT:  [[ENTRY:.*]]:1942; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[I]], 41943; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]1944; CHECK:       [[VECTOR_PH]]:1945; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i32 [[I]], 41946; CHECK-NEXT:    [[N_VEC:%.*]] = sub i32 [[I]], [[N_MOD_VF]]1947; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]1948; CHECK:       [[VECTOR_BODY]]:1949; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]1950; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]1951; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[H]], i32 [[INDEX]]1952; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 11953; CHECK-NEXT:    [[TMP9:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD]], zeroinitializer1954; CHECK-NEXT:    [[TMP2:%.*]] = udiv <4 x i8> [[WIDE_LOAD]], splat (i8 31)1955; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw nsw <4 x i8> [[TMP2]], splat (i8 3)1956; CHECK-NEXT:    [[TMP4:%.*]] = udiv <4 x i8> [[TMP3]], splat (i8 31)1957; CHECK-NEXT:    [[TMP14:%.*]] = zext <4 x i8> [[TMP4]] to <4 x i32>1958; CHECK-NEXT:    [[TMP5:%.*]] = select <4 x i1> [[TMP9]], <4 x i32> [[TMP14]], <4 x i32> zeroinitializer1959; CHECK-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP5]])1960; CHECK-NEXT:    [[TMP7]] = add i32 [[VEC_PHI]], [[TMP6]]1961; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 41962; CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]1963; CHECK-NEXT:    br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]]1964; CHECK:       [[MIDDLE_BLOCK]]:1965; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[I]], [[N_VEC]]1966; CHECK-NEXT:    br i1 [[CMP_N]], label %[[FOR_END7:.*]], label %[[SCALAR_PH]]1967; CHECK:       [[SCALAR_PH]]:1968; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]1969; CHECK-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]1970; CHECK-NEXT:    br label %[[FOR_BODY2:.*]]1971; CHECK:       [[FOR_BODY2]]:1972; CHECK-NEXT:    [[A_117:%.*]] = phi i32 [ [[INC6:%.*]], %[[FOR_INC5:.*]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]1973; CHECK-NEXT:    [[G_016:%.*]] = phi i32 [ [[G_1:%.*]], %[[FOR_INC5]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]1974; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[H]], i32 [[A_117]]1975; CHECK-NEXT:    [[TMP10:%.*]] = load i8, ptr [[ARRAYIDX]], align 11976; CHECK-NEXT:    [[TOBOOL3_NOT:%.*]] = icmp eq i8 [[TMP10]], 01977; CHECK-NEXT:    br i1 [[TOBOOL3_NOT]], label %[[FOR_INC5]], label %[[IF_THEN:.*]]1978; CHECK:       [[IF_THEN]]:1979; CHECK-NEXT:    [[TMP11:%.*]] = udiv i8 [[TMP10]], 311980; CHECK-NEXT:    [[TMP12:%.*]] = shl nuw nsw i8 [[TMP11]], 31981; CHECK-NEXT:    [[TMP13:%.*]] = udiv i8 [[TMP12]], 311982; CHECK-NEXT:    [[DIV4:%.*]] = zext i8 [[TMP13]] to i321983; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[G_016]], [[DIV4]]1984; CHECK-NEXT:    br label %[[FOR_INC5]]1985; CHECK:       [[FOR_INC5]]:1986; CHECK-NEXT:    [[G_1]] = phi i32 [ [[ADD]], %[[IF_THEN]] ], [ [[G_016]], %[[FOR_BODY2]] ]1987; CHECK-NEXT:    [[INC6]] = add nuw nsw i32 [[A_117]], 11988; CHECK-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC6]], [[I]]1989; CHECK-NEXT:    br i1 [[EXITCOND_NOT]], label %[[FOR_END7]], label %[[FOR_BODY2]], !llvm.loop [[LOOP24:![0-9]+]]1990; CHECK:       [[FOR_END7]]:1991; CHECK-NEXT:    [[G_1_LCSSA:%.*]] = phi i32 [ [[G_1]], %[[FOR_INC5]] ], [ [[TMP7]], %[[MIDDLE_BLOCK]] ]1992; CHECK-NEXT:    ret i32 [[G_1_LCSSA]]1993;1994; CHECK-INTERLEAVED-LABEL: define i32 @predicated_not_dominates_reduction(1995; CHECK-INTERLEAVED-SAME: ptr noundef readonly captures(none) [[H:%.*]], i32 noundef [[I:%.*]]) {1996; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*]]:1997; CHECK-INTERLEAVED-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[I]], 81998; CHECK-INTERLEAVED-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]1999; CHECK-INTERLEAVED:       [[VECTOR_PH]]:2000; CHECK-INTERLEAVED-NEXT:    [[N_MOD_VF:%.*]] = urem i32 [[I]], 82001; CHECK-INTERLEAVED-NEXT:    [[N_VEC:%.*]] = sub i32 [[I]], [[N_MOD_VF]]2002; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]2003; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:2004; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]2005; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]2006; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ]2007; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[H]], i32 [[INDEX]]2008; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 42009; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 12010; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i8>, ptr [[TMP2]], align 12011; CHECK-INTERLEAVED-NEXT:    [[TMP16:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD]], zeroinitializer2012; CHECK-INTERLEAVED-NEXT:    [[TMP21:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD2]], zeroinitializer2013; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = udiv <4 x i8> [[WIDE_LOAD]], splat (i8 31)2014; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = udiv <4 x i8> [[WIDE_LOAD2]], splat (i8 31)2015; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = shl nuw nsw <4 x i8> [[TMP3]], splat (i8 3)2016; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = shl nuw nsw <4 x i8> [[TMP4]], splat (i8 3)2017; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = udiv <4 x i8> [[TMP5]], splat (i8 31)2018; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = udiv <4 x i8> [[TMP6]], splat (i8 31)2019; CHECK-INTERLEAVED-NEXT:    [[TMP22:%.*]] = zext <4 x i8> [[TMP7]] to <4 x i32>2020; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = select <4 x i1> [[TMP16]], <4 x i32> [[TMP22]], <4 x i32> zeroinitializer2021; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP9]])2022; CHECK-INTERLEAVED-NEXT:    [[TMP11]] = add i32 [[VEC_PHI]], [[TMP10]]2023; CHECK-INTERLEAVED-NEXT:    [[TMP23:%.*]] = zext <4 x i8> [[TMP8]] to <4 x i32>2024; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = select <4 x i1> [[TMP21]], <4 x i32> [[TMP23]], <4 x i32> zeroinitializer2025; CHECK-INTERLEAVED-NEXT:    [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP12]])2026; CHECK-INTERLEAVED-NEXT:    [[TMP14]] = add i32 [[VEC_PHI1]], [[TMP13]]2027; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 82028; CHECK-INTERLEAVED-NEXT:    [[TMP15:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]2029; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]]2030; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:2031; CHECK-INTERLEAVED-NEXT:    [[BIN_RDX:%.*]] = add i32 [[TMP14]], [[TMP11]]2032; CHECK-INTERLEAVED-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[I]], [[N_VEC]]2033; CHECK-INTERLEAVED-NEXT:    br i1 [[CMP_N]], label %[[FOR_END7:.*]], label %[[SCALAR_PH]]2034; CHECK-INTERLEAVED:       [[SCALAR_PH]]:2035; CHECK-INTERLEAVED-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]2036; CHECK-INTERLEAVED-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i32 [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]2037; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_BODY2:.*]]2038; CHECK-INTERLEAVED:       [[FOR_BODY2]]:2039; CHECK-INTERLEAVED-NEXT:    [[A_117:%.*]] = phi i32 [ [[INC6:%.*]], %[[FOR_INC5:.*]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]2040; CHECK-INTERLEAVED-NEXT:    [[G_016:%.*]] = phi i32 [ [[G_1:%.*]], %[[FOR_INC5]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]2041; CHECK-INTERLEAVED-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[H]], i32 [[A_117]]2042; CHECK-INTERLEAVED-NEXT:    [[TMP17:%.*]] = load i8, ptr [[ARRAYIDX]], align 12043; CHECK-INTERLEAVED-NEXT:    [[TOBOOL3_NOT:%.*]] = icmp eq i8 [[TMP17]], 02044; CHECK-INTERLEAVED-NEXT:    br i1 [[TOBOOL3_NOT]], label %[[FOR_INC5]], label %[[IF_THEN:.*]]2045; CHECK-INTERLEAVED:       [[IF_THEN]]:2046; CHECK-INTERLEAVED-NEXT:    [[TMP18:%.*]] = udiv i8 [[TMP17]], 312047; CHECK-INTERLEAVED-NEXT:    [[TMP19:%.*]] = shl nuw nsw i8 [[TMP18]], 32048; CHECK-INTERLEAVED-NEXT:    [[TMP20:%.*]] = udiv i8 [[TMP19]], 312049; CHECK-INTERLEAVED-NEXT:    [[DIV4:%.*]] = zext i8 [[TMP20]] to i322050; CHECK-INTERLEAVED-NEXT:    [[ADD:%.*]] = add nsw i32 [[G_016]], [[DIV4]]2051; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_INC5]]2052; CHECK-INTERLEAVED:       [[FOR_INC5]]:2053; CHECK-INTERLEAVED-NEXT:    [[G_1]] = phi i32 [ [[ADD]], %[[IF_THEN]] ], [ [[G_016]], %[[FOR_BODY2]] ]2054; CHECK-INTERLEAVED-NEXT:    [[INC6]] = add nuw nsw i32 [[A_117]], 12055; CHECK-INTERLEAVED-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC6]], [[I]]2056; CHECK-INTERLEAVED-NEXT:    br i1 [[EXITCOND_NOT]], label %[[FOR_END7]], label %[[FOR_BODY2]], !llvm.loop [[LOOP24:![0-9]+]]2057; CHECK-INTERLEAVED:       [[FOR_END7]]:2058; CHECK-INTERLEAVED-NEXT:    [[G_1_LCSSA:%.*]] = phi i32 [ [[G_1]], %[[FOR_INC5]] ], [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ]2059; CHECK-INTERLEAVED-NEXT:    ret i32 [[G_1_LCSSA]]2060;2061entry:2062  br label %for.body22063 2064for.body2:                                        ; preds = %entry, %for.inc52065  %a.117 = phi i32 [ %inc6, %for.inc5 ], [ 0, %entry ]2066  %g.016 = phi i32 [ %g.1, %for.inc5 ], [ 0, %entry ]2067  %arrayidx = getelementptr inbounds i8, ptr %h, i32 %a.1172068  %0 = load i8, ptr %arrayidx, align 12069  %tobool3.not = icmp eq i8 %0, 02070  br i1 %tobool3.not, label %for.inc5, label %if.then2071 2072if.then:                                          ; preds = %for.body22073  %1 = udiv i8 %0, 312074  %2 = shl nuw nsw i8 %1, 32075  %3 = udiv i8 %2, 312076  %div4 = zext i8 %3 to i322077  %add = add nsw i32 %g.016, %div42078  br label %for.inc52079 2080for.inc5:                                         ; preds = %for.body2, %if.then2081  %g.1 = phi i32 [ %add, %if.then ], [ %g.016, %for.body2 ]2082  %inc6 = add nuw nsw i32 %a.117, 12083  %exitcond.not = icmp eq i32 %inc6, %i2084  br i1 %exitcond.not, label %for.end7, label %for.body22085 2086for.end7:                                         ; preds = %for.inc52087  %g.1.lcssa = phi i32 [ %g.1, %for.inc5 ]2088  ret i32 %g.1.lcssa2089}2090 2091define i32 @predicated_not_dominates_reduction_twoadd(ptr nocapture noundef readonly %h, i32 noundef %i) {2092; CHECK-LABEL: define i32 @predicated_not_dominates_reduction_twoadd(2093; CHECK-SAME: ptr noundef readonly captures(none) [[H:%.*]], i32 noundef [[I:%.*]]) {2094; CHECK-NEXT:  [[ENTRY:.*]]:2095; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[I]], 42096; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]2097; CHECK:       [[VECTOR_PH]]:2098; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i32 [[I]], 42099; CHECK-NEXT:    [[N_VEC:%.*]] = sub i32 [[I]], [[N_MOD_VF]]2100; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]2101; CHECK:       [[VECTOR_BODY]]:2102; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]2103; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]2104; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[H]], i32 [[INDEX]]2105; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 12106; CHECK-NEXT:    [[TMP6:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD]], zeroinitializer2107; CHECK-NEXT:    [[TMP2:%.*]] = udiv <4 x i8> [[WIDE_LOAD]], splat (i8 31)2108; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw nsw <4 x i8> [[TMP2]], splat (i8 3)2109; CHECK-NEXT:    [[TMP4:%.*]] = udiv <4 x i8> [[TMP3]], splat (i8 31)2110; CHECK-NEXT:    [[TMP13:%.*]] = zext <4 x i8> [[TMP4]] to <4 x i32>2111; CHECK-NEXT:    [[TMP5:%.*]] = select <4 x i1> [[TMP6]], <4 x i32> [[TMP13]], <4 x i32> zeroinitializer2112; CHECK-NEXT:    [[TMP7:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP5]])2113; CHECK-NEXT:    [[TMP8:%.*]] = add i32 [[VEC_PHI]], [[TMP7]]2114; CHECK-NEXT:    [[TMP9:%.*]] = select <4 x i1> [[TMP6]], <4 x i32> [[TMP13]], <4 x i32> zeroinitializer2115; CHECK-NEXT:    [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP9]])2116; CHECK-NEXT:    [[TMP11]] = add i32 [[TMP8]], [[TMP10]]2117; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 42118; CHECK-NEXT:    [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]2119; CHECK-NEXT:    br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP25:![0-9]+]]2120; CHECK:       [[MIDDLE_BLOCK]]:2121; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[I]], [[N_VEC]]2122; CHECK-NEXT:    br i1 [[CMP_N]], label %[[FOR_END7:.*]], label %[[SCALAR_PH]]2123; CHECK:       [[SCALAR_PH]]:2124; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]2125; CHECK-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]2126; CHECK-NEXT:    br label %[[FOR_BODY2:.*]]2127; CHECK:       [[FOR_BODY2]]:2128; CHECK-NEXT:    [[A_117:%.*]] = phi i32 [ [[INC6:%.*]], %[[FOR_INC5:.*]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]2129; CHECK-NEXT:    [[G_016:%.*]] = phi i32 [ [[G_1:%.*]], %[[FOR_INC5]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]2130; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[H]], i32 [[A_117]]2131; CHECK-NEXT:    [[TMP14:%.*]] = load i8, ptr [[ARRAYIDX]], align 12132; CHECK-NEXT:    [[TOBOOL3_NOT:%.*]] = icmp eq i8 [[TMP14]], 02133; CHECK-NEXT:    br i1 [[TOBOOL3_NOT]], label %[[FOR_INC5]], label %[[IF_THEN:.*]]2134; CHECK:       [[IF_THEN]]:2135; CHECK-NEXT:    [[TMP15:%.*]] = udiv i8 [[TMP14]], 312136; CHECK-NEXT:    [[TMP16:%.*]] = shl nuw nsw i8 [[TMP15]], 32137; CHECK-NEXT:    [[TMP17:%.*]] = udiv i8 [[TMP16]], 312138; CHECK-NEXT:    [[DIV4:%.*]] = zext i8 [[TMP17]] to i322139; CHECK-NEXT:    [[ADD1:%.*]] = add nsw i32 [[G_016]], [[DIV4]]2140; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[ADD1]], [[DIV4]]2141; CHECK-NEXT:    br label %[[FOR_INC5]]2142; CHECK:       [[FOR_INC5]]:2143; CHECK-NEXT:    [[G_1]] = phi i32 [ [[ADD]], %[[IF_THEN]] ], [ [[G_016]], %[[FOR_BODY2]] ]2144; CHECK-NEXT:    [[INC6]] = add nuw nsw i32 [[A_117]], 12145; CHECK-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC6]], [[I]]2146; CHECK-NEXT:    br i1 [[EXITCOND_NOT]], label %[[FOR_END7]], label %[[FOR_BODY2]], !llvm.loop [[LOOP26:![0-9]+]]2147; CHECK:       [[FOR_END7]]:2148; CHECK-NEXT:    [[G_1_LCSSA:%.*]] = phi i32 [ [[G_1]], %[[FOR_INC5]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]2149; CHECK-NEXT:    ret i32 [[G_1_LCSSA]]2150;2151; CHECK-INTERLEAVED-LABEL: define i32 @predicated_not_dominates_reduction_twoadd(2152; CHECK-INTERLEAVED-SAME: ptr noundef readonly captures(none) [[H:%.*]], i32 noundef [[I:%.*]]) {2153; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*]]:2154; CHECK-INTERLEAVED-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[I]], 82155; CHECK-INTERLEAVED-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]2156; CHECK-INTERLEAVED:       [[VECTOR_PH]]:2157; CHECK-INTERLEAVED-NEXT:    [[N_MOD_VF:%.*]] = urem i32 [[I]], 82158; CHECK-INTERLEAVED-NEXT:    [[N_VEC:%.*]] = sub i32 [[I]], [[N_MOD_VF]]2159; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]2160; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:2161; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]2162; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ]2163; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ]2164; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[H]], i32 [[INDEX]]2165; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 42166; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 12167; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i8>, ptr [[TMP2]], align 12168; CHECK-INTERLEAVED-NEXT:    [[TMP27:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD]], zeroinitializer2169; CHECK-INTERLEAVED-NEXT:    [[TMP28:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD2]], zeroinitializer2170; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = udiv <4 x i8> [[WIDE_LOAD]], splat (i8 31)2171; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = udiv <4 x i8> [[WIDE_LOAD2]], splat (i8 31)2172; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = shl nuw nsw <4 x i8> [[TMP3]], splat (i8 3)2173; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = shl nuw nsw <4 x i8> [[TMP4]], splat (i8 3)2174; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = udiv <4 x i8> [[TMP5]], splat (i8 31)2175; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = udiv <4 x i8> [[TMP6]], splat (i8 31)2176; CHECK-INTERLEAVED-NEXT:    [[TMP29:%.*]] = zext <4 x i8> [[TMP7]] to <4 x i32>2177; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = select <4 x i1> [[TMP27]], <4 x i32> [[TMP29]], <4 x i32> zeroinitializer2178; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP9]])2179; CHECK-INTERLEAVED-NEXT:    [[TMP11:%.*]] = add i32 [[VEC_PHI]], [[TMP10]]2180; CHECK-INTERLEAVED-NEXT:    [[TMP30:%.*]] = zext <4 x i8> [[TMP8]] to <4 x i32>2181; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = select <4 x i1> [[TMP28]], <4 x i32> [[TMP30]], <4 x i32> zeroinitializer2182; CHECK-INTERLEAVED-NEXT:    [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP12]])2183; CHECK-INTERLEAVED-NEXT:    [[TMP14:%.*]] = add i32 [[VEC_PHI1]], [[TMP13]]2184; CHECK-INTERLEAVED-NEXT:    [[TMP15:%.*]] = select <4 x i1> [[TMP27]], <4 x i32> [[TMP29]], <4 x i32> zeroinitializer2185; CHECK-INTERLEAVED-NEXT:    [[TMP16:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP15]])2186; CHECK-INTERLEAVED-NEXT:    [[TMP17]] = add i32 [[TMP11]], [[TMP16]]2187; CHECK-INTERLEAVED-NEXT:    [[TMP18:%.*]] = select <4 x i1> [[TMP28]], <4 x i32> [[TMP30]], <4 x i32> zeroinitializer2188; CHECK-INTERLEAVED-NEXT:    [[TMP19:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP18]])2189; CHECK-INTERLEAVED-NEXT:    [[TMP20]] = add i32 [[TMP14]], [[TMP19]]2190; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 82191; CHECK-INTERLEAVED-NEXT:    [[TMP21:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]2192; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP25:![0-9]+]]2193; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:2194; CHECK-INTERLEAVED-NEXT:    [[BIN_RDX:%.*]] = add i32 [[TMP20]], [[TMP17]]2195; CHECK-INTERLEAVED-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[I]], [[N_VEC]]2196; CHECK-INTERLEAVED-NEXT:    br i1 [[CMP_N]], label %[[FOR_END7:.*]], label %[[SCALAR_PH]]2197; CHECK-INTERLEAVED:       [[SCALAR_PH]]:2198; CHECK-INTERLEAVED-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]2199; CHECK-INTERLEAVED-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i32 [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]2200; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_BODY2:.*]]2201; CHECK-INTERLEAVED:       [[FOR_BODY2]]:2202; CHECK-INTERLEAVED-NEXT:    [[A_117:%.*]] = phi i32 [ [[INC6:%.*]], %[[FOR_INC5:.*]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]2203; CHECK-INTERLEAVED-NEXT:    [[G_016:%.*]] = phi i32 [ [[G_1:%.*]], %[[FOR_INC5]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]2204; CHECK-INTERLEAVED-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[H]], i32 [[A_117]]2205; CHECK-INTERLEAVED-NEXT:    [[TMP23:%.*]] = load i8, ptr [[ARRAYIDX]], align 12206; CHECK-INTERLEAVED-NEXT:    [[TOBOOL3_NOT:%.*]] = icmp eq i8 [[TMP23]], 02207; CHECK-INTERLEAVED-NEXT:    br i1 [[TOBOOL3_NOT]], label %[[FOR_INC5]], label %[[IF_THEN:.*]]2208; CHECK-INTERLEAVED:       [[IF_THEN]]:2209; CHECK-INTERLEAVED-NEXT:    [[TMP24:%.*]] = udiv i8 [[TMP23]], 312210; CHECK-INTERLEAVED-NEXT:    [[TMP25:%.*]] = shl nuw nsw i8 [[TMP24]], 32211; CHECK-INTERLEAVED-NEXT:    [[TMP26:%.*]] = udiv i8 [[TMP25]], 312212; CHECK-INTERLEAVED-NEXT:    [[DIV4:%.*]] = zext i8 [[TMP26]] to i322213; CHECK-INTERLEAVED-NEXT:    [[ADD1:%.*]] = add nsw i32 [[G_016]], [[DIV4]]2214; CHECK-INTERLEAVED-NEXT:    [[ADD:%.*]] = add nsw i32 [[ADD1]], [[DIV4]]2215; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_INC5]]2216; CHECK-INTERLEAVED:       [[FOR_INC5]]:2217; CHECK-INTERLEAVED-NEXT:    [[G_1]] = phi i32 [ [[ADD]], %[[IF_THEN]] ], [ [[G_016]], %[[FOR_BODY2]] ]2218; CHECK-INTERLEAVED-NEXT:    [[INC6]] = add nuw nsw i32 [[A_117]], 12219; CHECK-INTERLEAVED-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC6]], [[I]]2220; CHECK-INTERLEAVED-NEXT:    br i1 [[EXITCOND_NOT]], label %[[FOR_END7]], label %[[FOR_BODY2]], !llvm.loop [[LOOP26:![0-9]+]]2221; CHECK-INTERLEAVED:       [[FOR_END7]]:2222; CHECK-INTERLEAVED-NEXT:    [[G_1_LCSSA:%.*]] = phi i32 [ [[G_1]], %[[FOR_INC5]] ], [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ]2223; CHECK-INTERLEAVED-NEXT:    ret i32 [[G_1_LCSSA]]2224;2225entry:2226  br label %for.body22227 2228for.body2:                                        ; preds = %entry, %for.inc52229  %a.117 = phi i32 [ %inc6, %for.inc5 ], [ 0, %entry ]2230  %g.016 = phi i32 [ %g.1, %for.inc5 ], [ 0, %entry ]2231  %arrayidx = getelementptr inbounds i8, ptr %h, i32 %a.1172232  %0 = load i8, ptr %arrayidx, align 12233  %tobool3.not = icmp eq i8 %0, 02234  br i1 %tobool3.not, label %for.inc5, label %if.then2235 2236if.then:                                          ; preds = %for.body22237  %1 = udiv i8 %0, 312238  %2 = shl nuw nsw i8 %1, 32239  %3 = udiv i8 %2, 312240  %div4 = zext i8 %3 to i322241  %add1 = add nsw i32 %g.016, %div42242  %add = add nsw i32 %add1, %div42243  br label %for.inc52244 2245for.inc5:                                         ; preds = %for.body2, %if.then2246  %g.1 = phi i32 [ %add, %if.then ], [ %g.016, %for.body2 ]2247  %inc6 = add nuw nsw i32 %a.117, 12248  %exitcond.not = icmp eq i32 %inc6, %i2249  br i1 %exitcond.not, label %for.end7, label %for.body22250 2251for.end7:                                         ; preds = %for.inc52252  %g.1.lcssa = phi i32 [ %g.1, %for.inc5 ]2253  ret i32 %g.1.lcssa2254}2255 2256%struct.e = type { i32, i32 }2257define i32 @predicated_or_dominates_reduction(ptr %b) {2258; CHECK-LABEL: define i32 @predicated_or_dominates_reduction(2259; CHECK-SAME: ptr [[B:%.*]]) {2260; CHECK-NEXT:  [[ENTRY:.*:]]2261; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]2262; CHECK:       [[VECTOR_PH]]:2263; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]2264; CHECK:       [[VECTOR_BODY]]:2265; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6:.*]] ]2266; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP48:%.*]], %[[PRED_LOAD_CONTINUE6]] ]2267; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[INDEX]], 02268; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[INDEX]], 12269; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[INDEX]], 22270; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[INDEX]], 32271; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [0 x [[STRUCT_E:%.*]]], ptr [[B]], i32 0, i32 [[TMP0]], i32 12272; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP1]], i32 12273; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP2]], i32 12274; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP3]], i32 12275; CHECK-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP4]], align 42276; CHECK-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP6]], align 42277; CHECK-NEXT:    [[TMP13:%.*]] = load i32, ptr [[TMP8]], align 42278; CHECK-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP10]], align 42279; CHECK-NEXT:    [[TMP15:%.*]] = insertelement <4 x i32> poison, i32 [[TMP11]], i32 02280; CHECK-NEXT:    [[TMP16:%.*]] = insertelement <4 x i32> [[TMP15]], i32 [[TMP12]], i32 12281; CHECK-NEXT:    [[TMP17:%.*]] = insertelement <4 x i32> [[TMP16]], i32 [[TMP13]], i32 22282; CHECK-NEXT:    [[TMP18:%.*]] = insertelement <4 x i32> [[TMP17]], i32 [[TMP14]], i32 32283; CHECK-NEXT:    [[TMP19:%.*]] = icmp eq <4 x i32> [[TMP18]], zeroinitializer2284; CHECK-NEXT:    [[TMP20:%.*]] = extractelement <4 x i1> [[TMP19]], i32 02285; CHECK-NEXT:    br i1 [[TMP20]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]2286; CHECK:       [[PRED_LOAD_IF]]:2287; CHECK-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP0]]2288; CHECK-NEXT:    [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 42289; CHECK-NEXT:    [[TMP24:%.*]] = insertelement <4 x i32> poison, i32 [[TMP23]], i32 02290; CHECK-NEXT:    br label %[[PRED_LOAD_CONTINUE]]2291; CHECK:       [[PRED_LOAD_CONTINUE]]:2292; CHECK-NEXT:    [[TMP25:%.*]] = phi <4 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP24]], %[[PRED_LOAD_IF]] ]2293; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <4 x i1> [[TMP19]], i32 12294; CHECK-NEXT:    br i1 [[TMP26]], label %[[PRED_LOAD_IF1:.*]], label %[[PRED_LOAD_CONTINUE2:.*]]2295; CHECK:       [[PRED_LOAD_IF1]]:2296; CHECK-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP1]]2297; CHECK-NEXT:    [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 42298; CHECK-NEXT:    [[TMP30:%.*]] = insertelement <4 x i32> [[TMP25]], i32 [[TMP29]], i32 12299; CHECK-NEXT:    br label %[[PRED_LOAD_CONTINUE2]]2300; CHECK:       [[PRED_LOAD_CONTINUE2]]:2301; CHECK-NEXT:    [[TMP31:%.*]] = phi <4 x i32> [ [[TMP25]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP30]], %[[PRED_LOAD_IF1]] ]2302; CHECK-NEXT:    [[TMP32:%.*]] = extractelement <4 x i1> [[TMP19]], i32 22303; CHECK-NEXT:    br i1 [[TMP32]], label %[[PRED_LOAD_IF3:.*]], label %[[PRED_LOAD_CONTINUE4:.*]]2304; CHECK:       [[PRED_LOAD_IF3]]:2305; CHECK-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP2]]2306; CHECK-NEXT:    [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 42307; CHECK-NEXT:    [[TMP36:%.*]] = insertelement <4 x i32> [[TMP31]], i32 [[TMP35]], i32 22308; CHECK-NEXT:    br label %[[PRED_LOAD_CONTINUE4]]2309; CHECK:       [[PRED_LOAD_CONTINUE4]]:2310; CHECK-NEXT:    [[TMP37:%.*]] = phi <4 x i32> [ [[TMP31]], %[[PRED_LOAD_CONTINUE2]] ], [ [[TMP36]], %[[PRED_LOAD_IF3]] ]2311; CHECK-NEXT:    [[TMP38:%.*]] = extractelement <4 x i1> [[TMP19]], i32 32312; CHECK-NEXT:    br i1 [[TMP38]], label %[[PRED_LOAD_IF5:.*]], label %[[PRED_LOAD_CONTINUE6]]2313; CHECK:       [[PRED_LOAD_IF5]]:2314; CHECK-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP3]]2315; CHECK-NEXT:    [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 42316; CHECK-NEXT:    [[TMP42:%.*]] = insertelement <4 x i32> [[TMP37]], i32 [[TMP41]], i32 32317; CHECK-NEXT:    br label %[[PRED_LOAD_CONTINUE6]]2318; CHECK:       [[PRED_LOAD_CONTINUE6]]:2319; CHECK-NEXT:    [[TMP43:%.*]] = phi <4 x i32> [ [[TMP37]], %[[PRED_LOAD_CONTINUE4]] ], [ [[TMP42]], %[[PRED_LOAD_IF5]] ]2320; CHECK-NEXT:    [[TMP44:%.*]] = icmp ne <4 x i32> [[TMP43]], zeroinitializer2321; CHECK-NEXT:    [[TMP39:%.*]] = select <4 x i1> [[TMP19]], <4 x i1> [[TMP44]], <4 x i1> zeroinitializer2322; CHECK-NEXT:    [[NOT_:%.*]] = xor <4 x i1> [[TMP19]], splat (i1 true)2323; CHECK-NEXT:    [[TMP50:%.*]] = or <4 x i1> [[TMP39]], [[NOT_]]2324; CHECK-NEXT:    [[TMP51:%.*]] = select <4 x i1> [[TMP50]], <4 x i32> splat (i32 1), <4 x i32> zeroinitializer2325; CHECK-NEXT:    [[TMP47:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP51]])2326; CHECK-NEXT:    [[TMP48]] = add i32 [[VEC_PHI]], [[TMP47]]2327; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 42328; CHECK-NEXT:    [[TMP49:%.*]] = icmp eq i32 [[INDEX_NEXT]], 10002329; CHECK-NEXT:    br i1 [[TMP49]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP27:![0-9]+]]2330; CHECK:       [[MIDDLE_BLOCK]]:2331; CHECK-NEXT:    br label %[[FOR_COND_CLEANUP:.*]]2332; CHECK:       [[FOR_COND_CLEANUP]]:2333; CHECK-NEXT:    ret i32 [[TMP48]]2334;2335; CHECK-INTERLEAVED-LABEL: define i32 @predicated_or_dominates_reduction(2336; CHECK-INTERLEAVED-SAME: ptr [[B:%.*]]) {2337; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]2338; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]2339; CHECK-INTERLEAVED:       [[VECTOR_PH]]:2340; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]2341; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:2342; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE15:.*]] ]2343; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP94:%.*]], %[[PRED_LOAD_CONTINUE15]] ]2344; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP98:%.*]], %[[PRED_LOAD_CONTINUE15]] ]2345; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = add i32 [[INDEX]], 02346; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = add i32 [[INDEX]], 12347; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = add i32 [[INDEX]], 22348; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = add i32 [[INDEX]], 32349; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = add i32 [[INDEX]], 42350; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = add i32 [[INDEX]], 52351; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = add i32 [[INDEX]], 62352; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = add i32 [[INDEX]], 72353; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [0 x [[STRUCT_E:%.*]]], ptr [[B]], i32 0, i32 [[TMP0]], i32 12354; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP1]], i32 12355; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP2]], i32 12356; CHECK-INTERLEAVED-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP3]], i32 12357; CHECK-INTERLEAVED-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP4]], i32 12358; CHECK-INTERLEAVED-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP5]], i32 12359; CHECK-INTERLEAVED-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP6]], i32 12360; CHECK-INTERLEAVED-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP7]], i32 12361; CHECK-INTERLEAVED-NEXT:    [[TMP23:%.*]] = load i32, ptr [[TMP8]], align 42362; CHECK-INTERLEAVED-NEXT:    [[TMP24:%.*]] = load i32, ptr [[TMP10]], align 42363; CHECK-INTERLEAVED-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP12]], align 42364; CHECK-INTERLEAVED-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP14]], align 42365; CHECK-INTERLEAVED-NEXT:    [[TMP27:%.*]] = insertelement <4 x i32> poison, i32 [[TMP23]], i32 02366; CHECK-INTERLEAVED-NEXT:    [[TMP21:%.*]] = insertelement <4 x i32> [[TMP27]], i32 [[TMP24]], i32 12367; CHECK-INTERLEAVED-NEXT:    [[TMP35:%.*]] = insertelement <4 x i32> [[TMP21]], i32 [[TMP25]], i32 22368; CHECK-INTERLEAVED-NEXT:    [[TMP30:%.*]] = insertelement <4 x i32> [[TMP35]], i32 [[TMP26]], i32 32369; CHECK-INTERLEAVED-NEXT:    [[TMP31:%.*]] = load i32, ptr [[TMP16]], align 42370; CHECK-INTERLEAVED-NEXT:    [[TMP32:%.*]] = load i32, ptr [[TMP18]], align 42371; CHECK-INTERLEAVED-NEXT:    [[TMP33:%.*]] = load i32, ptr [[TMP20]], align 42372; CHECK-INTERLEAVED-NEXT:    [[TMP34:%.*]] = load i32, ptr [[TMP22]], align 42373; CHECK-INTERLEAVED-NEXT:    [[TMP28:%.*]] = insertelement <4 x i32> poison, i32 [[TMP31]], i32 02374; CHECK-INTERLEAVED-NEXT:    [[TMP29:%.*]] = insertelement <4 x i32> [[TMP28]], i32 [[TMP32]], i32 12375; CHECK-INTERLEAVED-NEXT:    [[TMP36:%.*]] = insertelement <4 x i32> [[TMP29]], i32 [[TMP33]], i32 22376; CHECK-INTERLEAVED-NEXT:    [[TMP38:%.*]] = insertelement <4 x i32> [[TMP36]], i32 [[TMP34]], i32 32377; CHECK-INTERLEAVED-NEXT:    [[TMP39:%.*]] = icmp eq <4 x i32> [[TMP30]], zeroinitializer2378; CHECK-INTERLEAVED-NEXT:    [[TMP40:%.*]] = icmp eq <4 x i32> [[TMP38]], zeroinitializer2379; CHECK-INTERLEAVED-NEXT:    [[TMP41:%.*]] = extractelement <4 x i1> [[TMP39]], i32 02380; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP41]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]2381; CHECK-INTERLEAVED:       [[PRED_LOAD_IF]]:2382; CHECK-INTERLEAVED-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP0]]2383; CHECK-INTERLEAVED-NEXT:    [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 42384; CHECK-INTERLEAVED-NEXT:    [[TMP45:%.*]] = insertelement <4 x i32> poison, i32 [[TMP44]], i32 02385; CHECK-INTERLEAVED-NEXT:    br label %[[PRED_LOAD_CONTINUE]]2386; CHECK-INTERLEAVED:       [[PRED_LOAD_CONTINUE]]:2387; CHECK-INTERLEAVED-NEXT:    [[TMP46:%.*]] = phi <4 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP45]], %[[PRED_LOAD_IF]] ]2388; CHECK-INTERLEAVED-NEXT:    [[TMP47:%.*]] = extractelement <4 x i1> [[TMP39]], i32 12389; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP47]], label %[[PRED_LOAD_IF2:.*]], label %[[PRED_LOAD_CONTINUE3:.*]]2390; CHECK-INTERLEAVED:       [[PRED_LOAD_IF2]]:2391; CHECK-INTERLEAVED-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP1]]2392; CHECK-INTERLEAVED-NEXT:    [[TMP50:%.*]] = load i32, ptr [[TMP49]], align 42393; CHECK-INTERLEAVED-NEXT:    [[TMP51:%.*]] = insertelement <4 x i32> [[TMP46]], i32 [[TMP50]], i32 12394; CHECK-INTERLEAVED-NEXT:    br label %[[PRED_LOAD_CONTINUE3]]2395; CHECK-INTERLEAVED:       [[PRED_LOAD_CONTINUE3]]:2396; CHECK-INTERLEAVED-NEXT:    [[TMP52:%.*]] = phi <4 x i32> [ [[TMP46]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP51]], %[[PRED_LOAD_IF2]] ]2397; CHECK-INTERLEAVED-NEXT:    [[TMP53:%.*]] = extractelement <4 x i1> [[TMP39]], i32 22398; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP53]], label %[[PRED_LOAD_IF4:.*]], label %[[PRED_LOAD_CONTINUE5:.*]]2399; CHECK-INTERLEAVED:       [[PRED_LOAD_IF4]]:2400; CHECK-INTERLEAVED-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP2]]2401; CHECK-INTERLEAVED-NEXT:    [[TMP56:%.*]] = load i32, ptr [[TMP55]], align 42402; CHECK-INTERLEAVED-NEXT:    [[TMP57:%.*]] = insertelement <4 x i32> [[TMP52]], i32 [[TMP56]], i32 22403; CHECK-INTERLEAVED-NEXT:    br label %[[PRED_LOAD_CONTINUE5]]2404; CHECK-INTERLEAVED:       [[PRED_LOAD_CONTINUE5]]:2405; CHECK-INTERLEAVED-NEXT:    [[TMP58:%.*]] = phi <4 x i32> [ [[TMP52]], %[[PRED_LOAD_CONTINUE3]] ], [ [[TMP57]], %[[PRED_LOAD_IF4]] ]2406; CHECK-INTERLEAVED-NEXT:    [[TMP59:%.*]] = extractelement <4 x i1> [[TMP39]], i32 32407; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP59]], label %[[PRED_LOAD_IF6:.*]], label %[[PRED_LOAD_CONTINUE7:.*]]2408; CHECK-INTERLEAVED:       [[PRED_LOAD_IF6]]:2409; CHECK-INTERLEAVED-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP3]]2410; CHECK-INTERLEAVED-NEXT:    [[TMP62:%.*]] = load i32, ptr [[TMP61]], align 42411; CHECK-INTERLEAVED-NEXT:    [[TMP63:%.*]] = insertelement <4 x i32> [[TMP58]], i32 [[TMP62]], i32 32412; CHECK-INTERLEAVED-NEXT:    br label %[[PRED_LOAD_CONTINUE7]]2413; CHECK-INTERLEAVED:       [[PRED_LOAD_CONTINUE7]]:2414; CHECK-INTERLEAVED-NEXT:    [[TMP64:%.*]] = phi <4 x i32> [ [[TMP58]], %[[PRED_LOAD_CONTINUE5]] ], [ [[TMP63]], %[[PRED_LOAD_IF6]] ]2415; CHECK-INTERLEAVED-NEXT:    [[TMP65:%.*]] = extractelement <4 x i1> [[TMP40]], i32 02416; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP65]], label %[[PRED_LOAD_IF8:.*]], label %[[PRED_LOAD_CONTINUE9:.*]]2417; CHECK-INTERLEAVED:       [[PRED_LOAD_IF8]]:2418; CHECK-INTERLEAVED-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP4]]2419; CHECK-INTERLEAVED-NEXT:    [[TMP68:%.*]] = load i32, ptr [[TMP67]], align 42420; CHECK-INTERLEAVED-NEXT:    [[TMP69:%.*]] = insertelement <4 x i32> poison, i32 [[TMP68]], i32 02421; CHECK-INTERLEAVED-NEXT:    br label %[[PRED_LOAD_CONTINUE9]]2422; CHECK-INTERLEAVED:       [[PRED_LOAD_CONTINUE9]]:2423; CHECK-INTERLEAVED-NEXT:    [[TMP70:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE7]] ], [ [[TMP69]], %[[PRED_LOAD_IF8]] ]2424; CHECK-INTERLEAVED-NEXT:    [[TMP71:%.*]] = extractelement <4 x i1> [[TMP40]], i32 12425; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP71]], label %[[PRED_LOAD_IF10:.*]], label %[[PRED_LOAD_CONTINUE11:.*]]2426; CHECK-INTERLEAVED:       [[PRED_LOAD_IF10]]:2427; CHECK-INTERLEAVED-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP5]]2428; CHECK-INTERLEAVED-NEXT:    [[TMP74:%.*]] = load i32, ptr [[TMP73]], align 42429; CHECK-INTERLEAVED-NEXT:    [[TMP75:%.*]] = insertelement <4 x i32> [[TMP70]], i32 [[TMP74]], i32 12430; CHECK-INTERLEAVED-NEXT:    br label %[[PRED_LOAD_CONTINUE11]]2431; CHECK-INTERLEAVED:       [[PRED_LOAD_CONTINUE11]]:2432; CHECK-INTERLEAVED-NEXT:    [[TMP76:%.*]] = phi <4 x i32> [ [[TMP70]], %[[PRED_LOAD_CONTINUE9]] ], [ [[TMP75]], %[[PRED_LOAD_IF10]] ]2433; CHECK-INTERLEAVED-NEXT:    [[TMP77:%.*]] = extractelement <4 x i1> [[TMP40]], i32 22434; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP77]], label %[[PRED_LOAD_IF12:.*]], label %[[PRED_LOAD_CONTINUE13:.*]]2435; CHECK-INTERLEAVED:       [[PRED_LOAD_IF12]]:2436; CHECK-INTERLEAVED-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP6]]2437; CHECK-INTERLEAVED-NEXT:    [[TMP80:%.*]] = load i32, ptr [[TMP79]], align 42438; CHECK-INTERLEAVED-NEXT:    [[TMP81:%.*]] = insertelement <4 x i32> [[TMP76]], i32 [[TMP80]], i32 22439; CHECK-INTERLEAVED-NEXT:    br label %[[PRED_LOAD_CONTINUE13]]2440; CHECK-INTERLEAVED:       [[PRED_LOAD_CONTINUE13]]:2441; CHECK-INTERLEAVED-NEXT:    [[TMP82:%.*]] = phi <4 x i32> [ [[TMP76]], %[[PRED_LOAD_CONTINUE11]] ], [ [[TMP81]], %[[PRED_LOAD_IF12]] ]2442; CHECK-INTERLEAVED-NEXT:    [[TMP83:%.*]] = extractelement <4 x i1> [[TMP40]], i32 32443; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP83]], label %[[PRED_LOAD_IF14:.*]], label %[[PRED_LOAD_CONTINUE15]]2444; CHECK-INTERLEAVED:       [[PRED_LOAD_IF14]]:2445; CHECK-INTERLEAVED-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [0 x [[STRUCT_E]]], ptr [[B]], i32 0, i32 [[TMP7]]2446; CHECK-INTERLEAVED-NEXT:    [[TMP86:%.*]] = load i32, ptr [[TMP85]], align 42447; CHECK-INTERLEAVED-NEXT:    [[TMP87:%.*]] = insertelement <4 x i32> [[TMP82]], i32 [[TMP86]], i32 32448; CHECK-INTERLEAVED-NEXT:    br label %[[PRED_LOAD_CONTINUE15]]2449; CHECK-INTERLEAVED:       [[PRED_LOAD_CONTINUE15]]:2450; CHECK-INTERLEAVED-NEXT:    [[TMP88:%.*]] = phi <4 x i32> [ [[TMP82]], %[[PRED_LOAD_CONTINUE13]] ], [ [[TMP87]], %[[PRED_LOAD_IF14]] ]2451; CHECK-INTERLEAVED-NEXT:    [[TMP89:%.*]] = icmp ne <4 x i32> [[TMP64]], zeroinitializer2452; CHECK-INTERLEAVED-NEXT:    [[TMP90:%.*]] = icmp ne <4 x i32> [[TMP88]], zeroinitializer2453; CHECK-INTERLEAVED-NEXT:    [[TMP78:%.*]] = select <4 x i1> [[TMP39]], <4 x i1> [[TMP89]], <4 x i1> zeroinitializer2454; CHECK-INTERLEAVED-NEXT:    [[TMP84:%.*]] = select <4 x i1> [[TMP40]], <4 x i1> [[TMP90]], <4 x i1> zeroinitializer2455; CHECK-INTERLEAVED-NEXT:    [[NOT_:%.*]] = xor <4 x i1> [[TMP39]], splat (i1 true)2456; CHECK-INTERLEAVED-NEXT:    [[NOT_18:%.*]] = xor <4 x i1> [[TMP40]], splat (i1 true)2457; CHECK-INTERLEAVED-NEXT:    [[TMP91:%.*]] = or <4 x i1> [[TMP78]], [[NOT_]]2458; CHECK-INTERLEAVED-NEXT:    [[TMP92:%.*]] = or <4 x i1> [[TMP84]], [[NOT_18]]2459; CHECK-INTERLEAVED-NEXT:    [[TMP95:%.*]] = select <4 x i1> [[TMP91]], <4 x i32> splat (i32 1), <4 x i32> zeroinitializer2460; CHECK-INTERLEAVED-NEXT:    [[TMP93:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP95]])2461; CHECK-INTERLEAVED-NEXT:    [[TMP94]] = add i32 [[VEC_PHI]], [[TMP93]]2462; CHECK-INTERLEAVED-NEXT:    [[TMP96:%.*]] = select <4 x i1> [[TMP92]], <4 x i32> splat (i32 1), <4 x i32> zeroinitializer2463; CHECK-INTERLEAVED-NEXT:    [[TMP97:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP96]])2464; CHECK-INTERLEAVED-NEXT:    [[TMP98]] = add i32 [[VEC_PHI1]], [[TMP97]]2465; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 82466; CHECK-INTERLEAVED-NEXT:    [[TMP99:%.*]] = icmp eq i32 [[INDEX_NEXT]], 10002467; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP99]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP27:![0-9]+]]2468; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:2469; CHECK-INTERLEAVED-NEXT:    [[BIN_RDX:%.*]] = add i32 [[TMP98]], [[TMP94]]2470; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_COND_CLEANUP:.*]]2471; CHECK-INTERLEAVED:       [[FOR_COND_CLEANUP]]:2472; CHECK-INTERLEAVED-NEXT:    ret i32 [[BIN_RDX]]2473;2474entry:2475  br label %for.body2476 2477for.cond.cleanup:                                 ; preds = %for.inc2478  %a.1.lcssa = phi i32 [ %a.1, %for.inc ]2479  ret i32 %a.1.lcssa2480 2481for.body:                                         ; preds = %entry, %for.inc2482  %g.09 = phi i32 [ 0, %entry ], [ %inc3, %for.inc ]2483  %a.08 = phi i32 [ 0, %entry ], [ %a.1, %for.inc ]2484  %d = getelementptr inbounds [0 x %struct.e], ptr %b, i32 0, i32 %g.09, i32 12485  %0 = load i32, ptr %d, align 42486  %tobool.not = icmp eq i32 %0, 02487  br i1 %tobool.not, label %lor.lhs.false, label %if.then2488 2489lor.lhs.false:                                    ; preds = %for.body2490  %arrayidx = getelementptr inbounds [0 x %struct.e], ptr %b, i32 0, i32 %g.092491  %1 = load i32, ptr %arrayidx, align 42492  %tobool2.not = icmp eq i32 %1, 02493  br i1 %tobool2.not, label %for.inc, label %if.then2494 2495if.then:                                          ; preds = %lor.lhs.false, %for.body2496  %inc = add nsw i32 %a.08, 12497  br label %for.inc2498 2499for.inc:                                          ; preds = %lor.lhs.false, %if.then2500  %a.1 = phi i32 [ %inc, %if.then ], [ %a.08, %lor.lhs.false ]2501  %inc3 = add nuw nsw i32 %g.09, 12502  %exitcond.not = icmp eq i32 %inc3, 10002503  br i1 %exitcond.not, label %for.cond.cleanup, label %for.body2504}2505 2506; An in-loop add reduction followed by an in-loop sub reduction becomes an add reduction followed by an add reduction with its input negated2507define i32 @reduction_add_sub(ptr noalias nocapture %A, ptr noalias nocapture %B) {2508; CHECK-LABEL: define i32 @reduction_add_sub(2509; CHECK-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {2510; CHECK-NEXT:  [[ENTRY:.*:]]2511; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]2512; CHECK:       [[VECTOR_PH]]:2513; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]2514; CHECK:       [[VECTOR_BODY]]:2515; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]2516; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]2517; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]2518; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]2519; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 42520; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 42521; CHECK-NEXT:    [[TMP2:%.*]] = sub <4 x i32> zeroinitializer, [[WIDE_LOAD1]]2522; CHECK-NEXT:    [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD]])2523; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[VEC_PHI]], [[TMP3]]2524; CHECK-NEXT:    [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])2525; CHECK-NEXT:    [[TMP6]] = add i32 [[TMP4]], [[TMP5]]2526; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 42527; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2562528; CHECK-NEXT:    br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP28:![0-9]+]]2529; CHECK:       [[MIDDLE_BLOCK]]:2530; CHECK-NEXT:    br label %[[FOR_END:.*]]2531; CHECK:       [[FOR_END]]:2532; CHECK-NEXT:    ret i32 [[TMP6]]2533;2534; CHECK-INTERLEAVED-LABEL: define i32 @reduction_add_sub(2535; CHECK-INTERLEAVED-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {2536; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]2537; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]2538; CHECK-INTERLEAVED:       [[VECTOR_PH]]:2539; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]2540; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:2541; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]2542; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]2543; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]2544; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]2545; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]2546; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 42547; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 42548; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP2]], align 42549; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 42550; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP1]], align 42551; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP3]], align 42552; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = sub <4 x i32> zeroinitializer, [[WIDE_LOAD3]]2553; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = sub <4 x i32> zeroinitializer, [[WIDE_LOAD4]]2554; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD]])2555; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = add i32 [[VEC_PHI]], [[TMP6]]2556; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD2]])2557; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = add i32 [[VEC_PHI1]], [[TMP8]]2558; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP4]])2559; CHECK-INTERLEAVED-NEXT:    [[TMP11]] = add i32 [[TMP7]], [[TMP10]]2560; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP5]])2561; CHECK-INTERLEAVED-NEXT:    [[TMP13]] = add i32 [[TMP9]], [[TMP12]]2562; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 82563; CHECK-INTERLEAVED-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2562564; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP28:![0-9]+]]2565; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:2566; CHECK-INTERLEAVED-NEXT:    [[BIN_RDX:%.*]] = add i32 [[TMP13]], [[TMP11]]2567; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_END:.*]]2568; CHECK-INTERLEAVED:       [[FOR_END]]:2569; CHECK-INTERLEAVED-NEXT:    ret i32 [[BIN_RDX]]2570;2571entry:2572  br label %for.body2573 2574for.body:                                         ; preds = %entry, %for.body2575  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]2576  %x.05 = phi i32 [ %sub, %for.body ], [ 0, %entry ]2577  %arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv2578  %arrayidx.b = getelementptr inbounds i32, ptr %B, i64 %indvars.iv2579  %l0 = load i32, ptr %arrayidx, align 42580  %l0.b = load i32, ptr %arrayidx.b, align 42581  %add = add nsw i32 %x.05, %l02582  %sub = sub nsw i32 %add, %l0.b2583  %indvars.iv.next = add i64 %indvars.iv, 12584  %lftr.wideiv = trunc i64 %indvars.iv.next to i322585  %exitcond = icmp eq i32 %lftr.wideiv, 2562586  br i1 %exitcond, label %for.end, label %for.body2587 2588for.end:                                          ; preds = %for.body, %entry2589  %x.0.lcssa = phi i32 [ %sub, %for.body ]2590  ret i32 %x.0.lcssa2591}2592 2593; An in-loop sub reduction followed by an in-loop add reduction becomes an add reduction with its input negated2594define i32 @reduction_sub_add(ptr noalias nocapture %A, ptr noalias nocapture %B) {2595; CHECK-LABEL: define i32 @reduction_sub_add(2596; CHECK-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {2597; CHECK-NEXT:  [[ENTRY:.*:]]2598; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]2599; CHECK:       [[VECTOR_PH]]:2600; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]2601; CHECK:       [[VECTOR_BODY]]:2602; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]2603; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]2604; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]2605; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]2606; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 42607; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 42608; CHECK-NEXT:    [[TMP2:%.*]] = sub <4 x i32> zeroinitializer, [[WIDE_LOAD]]2609; CHECK-NEXT:    [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])2610; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[VEC_PHI]], [[TMP3]]2611; CHECK-NEXT:    [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD1]])2612; CHECK-NEXT:    [[TMP6]] = add i32 [[TMP4]], [[TMP5]]2613; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 42614; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2562615; CHECK-NEXT:    br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP29:![0-9]+]]2616; CHECK:       [[MIDDLE_BLOCK]]:2617; CHECK-NEXT:    br label %[[FOR_END:.*]]2618; CHECK:       [[FOR_END]]:2619; CHECK-NEXT:    ret i32 [[TMP6]]2620;2621; CHECK-INTERLEAVED-LABEL: define i32 @reduction_sub_add(2622; CHECK-INTERLEAVED-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) {2623; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]2624; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]2625; CHECK-INTERLEAVED:       [[VECTOR_PH]]:2626; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]2627; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:2628; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]2629; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]2630; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]2631; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]2632; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]2633; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 42634; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 42635; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP2]], align 42636; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 42637; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP1]], align 42638; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP3]], align 42639; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = sub <4 x i32> zeroinitializer, [[WIDE_LOAD]]2640; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = sub <4 x i32> zeroinitializer, [[WIDE_LOAD2]]2641; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP4]])2642; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = add i32 [[VEC_PHI]], [[TMP6]]2643; CHECK-INTERLEAVED-NEXT:    [[TMP8:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP5]])2644; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = add i32 [[VEC_PHI1]], [[TMP8]]2645; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD3]])2646; CHECK-INTERLEAVED-NEXT:    [[TMP11]] = add i32 [[TMP7]], [[TMP10]]2647; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[WIDE_LOAD4]])2648; CHECK-INTERLEAVED-NEXT:    [[TMP13]] = add i32 [[TMP9]], [[TMP12]]2649; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 82650; CHECK-INTERLEAVED-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2562651; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP29:![0-9]+]]2652; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:2653; CHECK-INTERLEAVED-NEXT:    [[BIN_RDX:%.*]] = add i32 [[TMP13]], [[TMP11]]2654; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_END:.*]]2655; CHECK-INTERLEAVED:       [[FOR_END]]:2656; CHECK-INTERLEAVED-NEXT:    ret i32 [[BIN_RDX]]2657;2658entry:2659  br label %for.body2660 2661for.body:                                         ; preds = %entry, %for.body2662  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]2663  %x.05 = phi i32 [ %add, %for.body ], [ 0, %entry ]2664  %arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv2665  %arrayidx.b = getelementptr inbounds i32, ptr %B, i64 %indvars.iv2666  %l0 = load i32, ptr %arrayidx, align 42667  %l0.b = load i32, ptr %arrayidx.b, align 42668  %sub = sub nsw i32 %x.05, %l02669  %add = add nsw i32 %sub, %l0.b2670  %indvars.iv.next = add i64 %indvars.iv, 12671  %lftr.wideiv = trunc i64 %indvars.iv.next to i322672  %exitcond = icmp eq i32 %lftr.wideiv, 2562673  br i1 %exitcond, label %for.end, label %for.body2674 2675for.end:                                          ; preds = %for.body, %entry2676  %x.0.lcssa = phi i32 [ %add, %for.body ]2677  ret i32 %x.0.lcssa2678}2679 2680; Test that bundling recipes that share an operand into an expression works.2681; In this case the two extends are the recipes that share an operand.2682define i64 @reduction_expression_same_operands(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {2683; CHECK-LABEL: define i64 @reduction_expression_same_operands(2684; CHECK-SAME: ptr readonly captures(none) [[X:%.*]], ptr readonly captures(none) [[Y:%.*]], i32 [[N:%.*]]) {2685; CHECK-NEXT:  [[ENTRY:.*]]:2686; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 42687; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]2688; CHECK:       [[VECTOR_PH]]:2689; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i32 [[N]], 42690; CHECK-NEXT:    [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]2691; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]2692; CHECK:       [[VECTOR_BODY]]:2693; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]2694; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]2695; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i16, ptr [[X]], i32 [[INDEX]]2696; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i16>, ptr [[TMP1]], align 42697; CHECK-NEXT:    [[TMP3:%.*]] = sext <4 x i16> [[WIDE_LOAD]] to <4 x i64>2698; CHECK-NEXT:    [[TMP4:%.*]] = mul nsw <4 x i64> [[TMP3]], [[TMP3]]2699; CHECK-NEXT:    [[TMP5:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP4]])2700; CHECK-NEXT:    [[TMP6]] = add i64 [[VEC_PHI]], [[TMP5]]2701; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 42702; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]2703; CHECK-NEXT:    br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP30:![0-9]+]]2704; CHECK:       [[MIDDLE_BLOCK]]:2705; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]2706; CHECK-NEXT:    br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]2707; CHECK:       [[SCALAR_PH]]:2708; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]2709; CHECK-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]2710; CHECK-NEXT:    br label %[[LOOP:.*]]2711; CHECK:       [[LOOP]]:2712; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]2713; CHECK-NEXT:    [[RDX:%.*]] = phi i64 [ [[RDX_NEXT:%.*]], %[[LOOP]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]2714; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[X]], i32 [[IV]]2715; CHECK-NEXT:    [[LOAD0:%.*]] = load i16, ptr [[ARRAYIDX]], align 42716; CHECK-NEXT:    [[CONV0:%.*]] = sext i16 [[LOAD0]] to i322717; CHECK-NEXT:    [[CONV1:%.*]] = sext i16 [[LOAD0]] to i322718; CHECK-NEXT:    [[MUL1:%.*]] = mul nsw i32 [[CONV0]], [[CONV1]]2719; CHECK-NEXT:    [[MUL:%.*]] = sext i32 [[MUL1]] to i642720; CHECK-NEXT:    [[RDX_NEXT]] = add nsw i64 [[RDX]], [[MUL]]2721; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i32 [[IV]], 12722; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]2723; CHECK-NEXT:    br i1 [[EXITCOND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP31:![0-9]+]]2724; CHECK:       [[EXIT]]:2725; CHECK-NEXT:    [[R_0_LCSSA:%.*]] = phi i64 [ [[RDX_NEXT]], %[[LOOP]] ], [ [[TMP6]], %[[MIDDLE_BLOCK]] ]2726; CHECK-NEXT:    ret i64 [[R_0_LCSSA]]2727;2728; CHECK-INTERLEAVED-LABEL: define i64 @reduction_expression_same_operands(2729; CHECK-INTERLEAVED-SAME: ptr readonly captures(none) [[X:%.*]], ptr readonly captures(none) [[Y:%.*]], i32 [[N:%.*]]) {2730; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*]]:2731; CHECK-INTERLEAVED-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 82732; CHECK-INTERLEAVED-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]2733; CHECK-INTERLEAVED:       [[VECTOR_PH]]:2734; CHECK-INTERLEAVED-NEXT:    [[N_MOD_VF:%.*]] = urem i32 [[N]], 82735; CHECK-INTERLEAVED-NEXT:    [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]2736; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]2737; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:2738; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]2739; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]2740; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ]2741; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i16, ptr [[X]], i32 [[INDEX]]2742; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i16, ptr [[TMP1]], i64 42743; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i16>, ptr [[TMP1]], align 42744; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i16>, ptr [[TMP2]], align 42745; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = sext <4 x i16> [[WIDE_LOAD]] to <4 x i64>2746; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = mul nsw <4 x i64> [[TMP4]], [[TMP4]]2747; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP5]])2748; CHECK-INTERLEAVED-NEXT:    [[TMP7]] = add i64 [[VEC_PHI]], [[TMP6]]2749; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = sext <4 x i16> [[WIDE_LOAD2]] to <4 x i64>2750; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = mul nsw <4 x i64> [[TMP9]], [[TMP9]]2751; CHECK-INTERLEAVED-NEXT:    [[TMP11:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP10]])2752; CHECK-INTERLEAVED-NEXT:    [[TMP12]] = add i64 [[VEC_PHI1]], [[TMP11]]2753; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 82754; CHECK-INTERLEAVED-NEXT:    [[TMP13:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]2755; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP30:![0-9]+]]2756; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:2757; CHECK-INTERLEAVED-NEXT:    [[BIN_RDX:%.*]] = add i64 [[TMP12]], [[TMP7]]2758; CHECK-INTERLEAVED-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]2759; CHECK-INTERLEAVED-NEXT:    br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]2760; CHECK-INTERLEAVED:       [[SCALAR_PH]]:2761; CHECK-INTERLEAVED-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]2762; CHECK-INTERLEAVED-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i64 [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]2763; CHECK-INTERLEAVED-NEXT:    br label %[[LOOP:.*]]2764; CHECK-INTERLEAVED:       [[LOOP]]:2765; CHECK-INTERLEAVED-NEXT:    [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]2766; CHECK-INTERLEAVED-NEXT:    [[RDX:%.*]] = phi i64 [ [[RDX_NEXT:%.*]], %[[LOOP]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]2767; CHECK-INTERLEAVED-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[X]], i32 [[IV]]2768; CHECK-INTERLEAVED-NEXT:    [[LOAD0:%.*]] = load i16, ptr [[ARRAYIDX]], align 42769; CHECK-INTERLEAVED-NEXT:    [[CONV0:%.*]] = sext i16 [[LOAD0]] to i322770; CHECK-INTERLEAVED-NEXT:    [[CONV1:%.*]] = sext i16 [[LOAD0]] to i322771; CHECK-INTERLEAVED-NEXT:    [[MUL1:%.*]] = mul nsw i32 [[CONV0]], [[CONV1]]2772; CHECK-INTERLEAVED-NEXT:    [[MUL:%.*]] = sext i32 [[MUL1]] to i642773; CHECK-INTERLEAVED-NEXT:    [[RDX_NEXT]] = add nsw i64 [[RDX]], [[MUL]]2774; CHECK-INTERLEAVED-NEXT:    [[IV_NEXT]] = add nuw nsw i32 [[IV]], 12775; CHECK-INTERLEAVED-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]2776; CHECK-INTERLEAVED-NEXT:    br i1 [[EXITCOND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP31:![0-9]+]]2777; CHECK-INTERLEAVED:       [[EXIT]]:2778; CHECK-INTERLEAVED-NEXT:    [[R_0_LCSSA:%.*]] = phi i64 [ [[RDX_NEXT]], %[[LOOP]] ], [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ]2779; CHECK-INTERLEAVED-NEXT:    ret i64 [[R_0_LCSSA]]2780;2781entry:2782  br label %loop2783 2784loop:2785  %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ]2786  %rdx = phi i64 [ %rdx.next, %loop ], [ 0, %entry ]2787  %arrayidx = getelementptr inbounds i16, ptr %x, i32 %iv2788  %load0 = load i16, ptr %arrayidx, align 42789  %conv0 = sext i16 %load0 to i322790  %conv1 = sext i16 %load0 to i322791  %mul = mul nsw i32 %conv0, %conv12792  %conv = sext i32 %mul to i642793  %rdx.next = add nsw i64 %rdx, %conv2794  %iv.next = add nuw nsw i32 %iv, 12795  %exitcond = icmp eq i32 %iv.next, %n2796  br i1 %exitcond, label %exit, label %loop2797 2798exit:2799  %r.0.lcssa = phi i64 [ %rdx.next, %loop ]2800  ret i64 %r.0.lcssa2801}2802 2803define i32 @reduction_expression_ext_mulacc_livein(ptr %a, i16 %c) {2804; CHECK-LABEL: define i32 @reduction_expression_ext_mulacc_livein(2805; CHECK-SAME: ptr [[A:%.*]], i16 [[C:%.*]]) {2806; CHECK-NEXT:  [[ENTRY:.*:]]2807; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]2808; CHECK:       [[VECTOR_PH]]:2809; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i16> poison, i16 [[C]], i64 02810; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i16> [[BROADCAST_SPLATINSERT]], <4 x i16> poison, <4 x i32> zeroinitializer2811; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]2812; CHECK:       [[VECTOR_BODY]]:2813; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]2814; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]2815; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]2816; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP0]], align 12817; CHECK-NEXT:    [[TMP1:%.*]] = zext <4 x i8> [[WIDE_LOAD]] to <4 x i16>2818; CHECK-NEXT:    [[TMP2:%.*]] = mul <4 x i16> [[BROADCAST_SPLAT]], [[TMP1]]2819; CHECK-NEXT:    [[TMP3:%.*]] = zext <4 x i16> [[TMP2]] to <4 x i32>2820; CHECK-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3]])2821; CHECK-NEXT:    [[TMP5]] = add i32 [[VEC_PHI]], [[TMP4]]2822; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 42823; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10242824; CHECK-NEXT:    br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP32:![0-9]+]]2825; CHECK:       [[MIDDLE_BLOCK]]:2826; CHECK-NEXT:    br label %[[FOR_EXIT:.*]]2827; CHECK:       [[FOR_EXIT]]:2828; CHECK-NEXT:    ret i32 [[TMP5]]2829;2830; CHECK-INTERLEAVED-LABEL: define i32 @reduction_expression_ext_mulacc_livein(2831; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], i16 [[C:%.*]]) {2832; CHECK-INTERLEAVED-NEXT:  [[ENTRY:.*:]]2833; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_PH:.*]]2834; CHECK-INTERLEAVED:       [[VECTOR_PH]]:2835; CHECK-INTERLEAVED-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i16> poison, i16 [[C]], i64 02836; CHECK-INTERLEAVED-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i16> [[BROADCAST_SPLATINSERT]], <4 x i16> poison, <4 x i32> zeroinitializer2837; CHECK-INTERLEAVED-NEXT:    br label %[[VECTOR_BODY:.*]]2838; CHECK-INTERLEAVED:       [[VECTOR_BODY]]:2839; CHECK-INTERLEAVED-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]2840; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ]2841; CHECK-INTERLEAVED-NEXT:    [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]2842; CHECK-INTERLEAVED-NEXT:    [[TMP0:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]2843; CHECK-INTERLEAVED-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i64 42844; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP0]], align 12845; CHECK-INTERLEAVED-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i8>, ptr [[TMP1]], align 12846; CHECK-INTERLEAVED-NEXT:    [[TMP2:%.*]] = zext <4 x i8> [[WIDE_LOAD]] to <4 x i16>2847; CHECK-INTERLEAVED-NEXT:    [[TMP3:%.*]] = zext <4 x i8> [[WIDE_LOAD2]] to <4 x i16>2848; CHECK-INTERLEAVED-NEXT:    [[TMP4:%.*]] = mul <4 x i16> [[BROADCAST_SPLAT]], [[TMP2]]2849; CHECK-INTERLEAVED-NEXT:    [[TMP5:%.*]] = mul <4 x i16> [[BROADCAST_SPLAT]], [[TMP3]]2850; CHECK-INTERLEAVED-NEXT:    [[TMP6:%.*]] = zext <4 x i16> [[TMP4]] to <4 x i32>2851; CHECK-INTERLEAVED-NEXT:    [[TMP7:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP6]])2852; CHECK-INTERLEAVED-NEXT:    [[TMP8]] = add i32 [[VEC_PHI]], [[TMP7]]2853; CHECK-INTERLEAVED-NEXT:    [[TMP9:%.*]] = zext <4 x i16> [[TMP5]] to <4 x i32>2854; CHECK-INTERLEAVED-NEXT:    [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP9]])2855; CHECK-INTERLEAVED-NEXT:    [[TMP11]] = add i32 [[VEC_PHI1]], [[TMP10]]2856; CHECK-INTERLEAVED-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 82857; CHECK-INTERLEAVED-NEXT:    [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10242858; CHECK-INTERLEAVED-NEXT:    br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP32:![0-9]+]]2859; CHECK-INTERLEAVED:       [[MIDDLE_BLOCK]]:2860; CHECK-INTERLEAVED-NEXT:    [[BIN_RDX:%.*]] = add i32 [[TMP11]], [[TMP8]]2861; CHECK-INTERLEAVED-NEXT:    br label %[[FOR_EXIT:.*]]2862; CHECK-INTERLEAVED:       [[FOR_EXIT]]:2863; CHECK-INTERLEAVED-NEXT:    ret i32 [[BIN_RDX]]2864;2865entry:2866  br label %for.body2867 2868for.body:                                         ; preds = %for.body, %entry2869  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]2870  %accum = phi i32 [ 0, %entry ], [ %add, %for.body ]2871  %gep.a = getelementptr i8, ptr %a, i64 %iv2872  %load.a = load i8, ptr %gep.a, align 12873  %ext.a = zext i8 %load.a to i162874  %mul = mul i16 %c, %ext.a2875  %mul.ext = zext i16 %mul to i322876  %add = add i32 %mul.ext, %accum2877  %iv.next = add i64 %iv, 12878  %exitcond.not = icmp eq i64 %iv.next, 10242879  br i1 %exitcond.not, label %for.exit, label %for.body2880 2881for.exit:                        ; preds = %for.body2882  ret i32 %add2883}2884 2885declare float @llvm.fmuladd.f32(float, float, float)2886 2887!6 = distinct !{!6, !7, !8}2888!7 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}2889!8 = !{!"llvm.loop.vectorize.enable", i1 true}2890