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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 62; RUN: opt -p loop-vectorize -force-vector-width=4 -S %s | FileCheck %s3 4define i32 @umax_phi_used_outside(ptr %src, i32 %n) {5; CHECK-LABEL: define i32 @umax_phi_used_outside(6; CHECK-SAME: ptr [[SRC:%.*]], i32 [[N:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*]]:8; CHECK-NEXT: br label %[[LOOP:.*]]9; CHECK: [[LOOP]]:10; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]11; CHECK-NEXT: [[MAX:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SPEC_SELECT:%.*]], %[[LOOP]] ]12; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i32 [[IV]]13; CHECK-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 114; CHECK-NEXT: [[L_EXT:%.*]] = zext i8 [[L]] to i3215; CHECK-NEXT: [[SPEC_SELECT]] = tail call i32 @llvm.umax.i32(i32 [[MAX]], i32 [[L_EXT]])16; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 117; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV]], [[N]]18; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]19; CHECK: [[EXIT]]:20; CHECK-NEXT: [[MAX_LCSSA:%.*]] = phi i32 [ [[MAX]], %[[LOOP]] ]21; CHECK-NEXT: ret i32 [[MAX_LCSSA]]22;23entry:24 br label %loop25 26loop:27 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]28 %max = phi i32 [ 0, %entry ], [ %spec.select, %loop ]29 %gep.src = getelementptr inbounds i8, ptr %src, i32 %iv30 %l = load i8, ptr %gep.src31 %l.ext = zext i8 %l to i3232 %spec.select = tail call i32 @llvm.umax.i32(i32 %max, i32 %l.ext)33 %iv.next = add i32 %iv, 134 %ec = icmp eq i32 %iv, %n35 br i1 %ec, label %exit, label %loop36 37exit:38 ret i32 %max39}40 41define i32 @chained_smax(i32 %x, ptr %src) {42; CHECK-LABEL: define i32 @chained_smax(43; CHECK-SAME: i32 [[X:%.*]], ptr [[SRC:%.*]]) {44; CHECK-NEXT: [[ENTRY:.*:]]45; CHECK-NEXT: br label %[[VECTOR_PH:.*]]46; CHECK: [[VECTOR_PH]]:47; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 048; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer49; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]50; CHECK: [[VECTOR_BODY]]:51; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6:.*]] ]52; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6]] ]53; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP26:%.*]], %[[PRED_LOAD_CONTINUE6]] ]54; CHECK-NEXT: [[TMP0:%.*]] = icmp ule <4 x i8> [[VEC_IND]], splat (i8 1)55; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[BROADCAST_SPLAT]], <4 x i32> [[VEC_PHI]])56; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i1> [[TMP0]], i32 057; CHECK-NEXT: br i1 [[TMP2]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]58; CHECK: [[PRED_LOAD_IF]]:59; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 060; CHECK-NEXT: [[TMP4:%.*]] = getelementptr [3 x i32], ptr [[SRC]], i64 [[TMP3]]61; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 462; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> poison, i32 [[TMP5]], i32 063; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE]]64; CHECK: [[PRED_LOAD_CONTINUE]]:65; CHECK-NEXT: [[TMP7:%.*]] = phi <4 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP6]], %[[PRED_LOAD_IF]] ]66; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP0]], i32 167; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_LOAD_IF1:.*]], label %[[PRED_LOAD_CONTINUE2:.*]]68; CHECK: [[PRED_LOAD_IF1]]:69; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 170; CHECK-NEXT: [[TMP10:%.*]] = getelementptr [3 x i32], ptr [[SRC]], i64 [[TMP9]]71; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 472; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[TMP11]], i32 173; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE2]]74; CHECK: [[PRED_LOAD_CONTINUE2]]:75; CHECK-NEXT: [[TMP13:%.*]] = phi <4 x i32> [ [[TMP7]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP12]], %[[PRED_LOAD_IF1]] ]76; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i1> [[TMP0]], i32 277; CHECK-NEXT: br i1 [[TMP14]], label %[[PRED_LOAD_IF3:.*]], label %[[PRED_LOAD_CONTINUE4:.*]]78; CHECK: [[PRED_LOAD_IF3]]:79; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 280; CHECK-NEXT: [[TMP16:%.*]] = getelementptr [3 x i32], ptr [[SRC]], i64 [[TMP15]]81; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 482; CHECK-NEXT: [[TMP18:%.*]] = insertelement <4 x i32> [[TMP13]], i32 [[TMP17]], i32 283; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE4]]84; CHECK: [[PRED_LOAD_CONTINUE4]]:85; CHECK-NEXT: [[TMP19:%.*]] = phi <4 x i32> [ [[TMP13]], %[[PRED_LOAD_CONTINUE2]] ], [ [[TMP18]], %[[PRED_LOAD_IF3]] ]86; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i1> [[TMP0]], i32 387; CHECK-NEXT: br i1 [[TMP20]], label %[[PRED_LOAD_IF5:.*]], label %[[PRED_LOAD_CONTINUE6]]88; CHECK: [[PRED_LOAD_IF5]]:89; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[INDEX]], 390; CHECK-NEXT: [[TMP22:%.*]] = getelementptr [3 x i32], ptr [[SRC]], i64 [[TMP21]]91; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 492; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> [[TMP19]], i32 [[TMP23]], i32 393; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE6]]94; CHECK: [[PRED_LOAD_CONTINUE6]]:95; CHECK-NEXT: [[TMP25:%.*]] = phi <4 x i32> [ [[TMP19]], %[[PRED_LOAD_CONTINUE4]] ], [ [[TMP24]], %[[PRED_LOAD_IF5]] ]96; CHECK-NEXT: [[TMP26]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP25]], <4 x i32> [[TMP1]])97; CHECK-NEXT: [[TMP27:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> [[TMP26]], <4 x i32> [[VEC_PHI]]98; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 499; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 4)100; CHECK-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]101; CHECK: [[MIDDLE_BLOCK]]:102; CHECK-NEXT: [[TMP28:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP27]])103; CHECK-NEXT: br label %[[EXIT:.*]]104; CHECK: [[EXIT]]:105; CHECK-NEXT: ret i32 [[TMP28]]106;107entry:108 br label %loop109 110loop: ; preds = %loop, %entry111 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]112 %max = phi i32 [ 0, %entry ], [ %max.next, %loop ]113 %gep.src = getelementptr [3 x i32], ptr %src, i64 %iv114 %max.1 = tail call i32 @llvm.smax.i32(i32 %x, i32 %max)115 %l = load i32, ptr %gep.src, align 4116 %max.next = tail call i32 @llvm.smax.i32(i32 %l, i32 %max.1)117 %iv.next = add i64 %iv, 1118 %ec = icmp eq i64 %iv, 1119 br i1 %ec, label %exit, label %loop120 121exit:122 ret i32 %max.next123}124 125define void @smax_with_invariant_store_user(ptr noalias %src, ptr %dst, i64 %n) {126; CHECK-LABEL: define void @smax_with_invariant_store_user(127; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) {128; CHECK-NEXT: [[ENTRY:.*]]:129; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1130; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4131; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]132; CHECK: [[VECTOR_PH]]:133; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 4134; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]135; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]136; CHECK: [[VECTOR_BODY]]:137; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]138; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]139; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]140; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4141; CHECK-NEXT: [[TMP2]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])142; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4143; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]144; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]145; CHECK: [[MIDDLE_BLOCK]]:146; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP2]])147; CHECK-NEXT: store i32 [[TMP4]], ptr [[DST]], align 4148; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]149; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]150; CHECK: [[SCALAR_PH]]:151; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]152; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]153; CHECK-NEXT: br label %[[LOOP:.*]]154; CHECK: [[LOOP]]:155; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]156; CHECK-NEXT: [[MAX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]157; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]]158; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4159; CHECK-NEXT: [[MAX_NEXT]] = tail call i32 @llvm.smax.i32(i32 [[MAX]], i32 [[L]])160; CHECK-NEXT: store i32 [[MAX_NEXT]], ptr [[DST]], align 4161; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1162; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]163; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]164; CHECK: [[EXIT]]:165; CHECK-NEXT: ret void166;167entry:168 br label %loop169 170loop:171 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]172 %max = phi i32 [ 0, %entry ], [ %max.next, %loop ]173 %gep.src = getelementptr inbounds i32, ptr %src, i64 %iv174 %l = load i32, ptr %gep.src, align 4175 %max.next = tail call i32 @llvm.smax.i32(i32 %max, i32 %l)176 store i32 %max.next, ptr %dst, align 4177 %iv.next = add i64 %iv, 1178 %ec = icmp eq i64 %iv, %n179 br i1 %ec, label %exit, label %loop180 181exit:182 ret void183}184 185define void @smax_with_multiple_invariant_store_user_same_addr(ptr noalias %src, ptr %dst, i64 %n) {186; CHECK-LABEL: define void @smax_with_multiple_invariant_store_user_same_addr(187; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) {188; CHECK-NEXT: [[ENTRY:.*]]:189; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1190; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4191; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]192; CHECK: [[VECTOR_PH]]:193; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 4194; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]195; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]196; CHECK: [[VECTOR_BODY]]:197; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]198; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]199; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]200; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4201; CHECK-NEXT: [[TMP2]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])202; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4203; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]204; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]205; CHECK: [[MIDDLE_BLOCK]]:206; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP2]])207; CHECK-NEXT: store i32 [[TMP4]], ptr [[DST]], align 4208; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]209; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]210; CHECK: [[SCALAR_PH]]:211; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]212; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]213; CHECK-NEXT: br label %[[LOOP:.*]]214; CHECK: [[LOOP]]:215; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]216; CHECK-NEXT: [[MAX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]217; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]]218; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4219; CHECK-NEXT: [[MAX_NEXT]] = tail call i32 @llvm.smax.i32(i32 [[MAX]], i32 [[L]])220; CHECK-NEXT: store i32 [[MAX_NEXT]], ptr [[DST]], align 4221; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1222; CHECK-NEXT: store i32 [[MAX_NEXT]], ptr [[DST]], align 4223; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]224; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]225; CHECK: [[EXIT]]:226; CHECK-NEXT: ret void227;228entry:229 br label %loop230 231loop:232 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]233 %max = phi i32 [ 0, %entry ], [ %max.next, %loop ]234 %gep.src = getelementptr inbounds i32, ptr %src, i64 %iv235 %l = load i32, ptr %gep.src, align 4236 %max.next = tail call i32 @llvm.smax.i32(i32 %max, i32 %l)237 store i32 %max.next, ptr %dst, align 4238 %iv.next = add i64 %iv, 1239 store i32 %max.next, ptr %dst, align 4240 %ec = icmp eq i64 %iv, %n241 br i1 %ec, label %exit, label %loop242 243exit:244 ret void245}246 247define void @smax_with_multiple_invariant_store_user_same_addr2(ptr noalias %src, ptr %dst, i64 %n) {248; CHECK-LABEL: define void @smax_with_multiple_invariant_store_user_same_addr2(249; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) {250; CHECK-NEXT: [[ENTRY:.*]]:251; CHECK-NEXT: br label %[[LOOP:.*]]252; CHECK: [[LOOP]]:253; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]254; CHECK-NEXT: [[MAX:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]255; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]]256; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4257; CHECK-NEXT: [[MAX_NEXT]] = tail call i32 @llvm.smax.i32(i32 [[MAX]], i32 [[L]])258; CHECK-NEXT: store i32 [[MAX_NEXT]], ptr [[DST]], align 4259; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1260; CHECK-NEXT: store i32 0, ptr [[DST]], align 4261; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]262; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]263; CHECK: [[EXIT]]:264; CHECK-NEXT: ret void265;266entry:267 br label %loop268 269loop:270 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]271 %max = phi i32 [ 0, %entry ], [ %max.next, %loop ]272 %gep.src = getelementptr inbounds i32, ptr %src, i64 %iv273 %l = load i32, ptr %gep.src, align 4274 %max.next = tail call i32 @llvm.smax.i32(i32 %max, i32 %l)275 store i32 %max.next, ptr %dst, align 4276 %iv.next = add i64 %iv, 1277 store i32 0, ptr %dst, align 4278 %ec = icmp eq i64 %iv, %n279 br i1 %ec, label %exit, label %loop280 281exit:282 ret void283}284 285define void @smax_with_multiple_invariant_store_user_same_addr3(ptr noalias %src, ptr %dst, i64 %n) {286; CHECK-LABEL: define void @smax_with_multiple_invariant_store_user_same_addr3(287; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) {288; CHECK-NEXT: [[ENTRY:.*]]:289; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1290; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4291; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]292; CHECK: [[VECTOR_PH]]:293; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 4294; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]295; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]296; CHECK: [[VECTOR_BODY]]:297; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]298; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]299; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]300; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4301; CHECK-NEXT: [[TMP2]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])302; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4303; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]304; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]305; CHECK: [[MIDDLE_BLOCK]]:306; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP2]])307; CHECK-NEXT: store i32 [[TMP4]], ptr [[DST]], align 4308; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]309; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]310; CHECK: [[SCALAR_PH]]:311; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]312; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]313; CHECK-NEXT: br label %[[LOOP:.*]]314; CHECK: [[LOOP]]:315; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]316; CHECK-NEXT: [[MAX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]317; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]]318; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4319; CHECK-NEXT: [[MAX_NEXT]] = tail call i32 @llvm.smax.i32(i32 [[MAX]], i32 [[L]])320; CHECK-NEXT: store i32 0, ptr [[DST]], align 4321; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1322; CHECK-NEXT: store i32 [[MAX_NEXT]], ptr [[DST]], align 4323; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]324; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]325; CHECK: [[EXIT]]:326; CHECK-NEXT: ret void327;328entry:329 br label %loop330 331loop:332 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]333 %max = phi i32 [ 0, %entry ], [ %max.next, %loop ]334 %gep.src = getelementptr inbounds i32, ptr %src, i64 %iv335 %l = load i32, ptr %gep.src, align 4336 %max.next = tail call i32 @llvm.smax.i32(i32 %max, i32 %l)337 store i32 0, ptr %dst, align 4338 %iv.next = add i64 %iv, 1339 store i32 %max.next, ptr %dst, align 4340 %ec = icmp eq i64 %iv, %n341 br i1 %ec, label %exit, label %loop342 343exit:344 ret void345}346 347define void @smax_with_multiple_invariant_store_user_different_addr(ptr noalias %src, ptr noalias %dst, ptr noalias %dst.2, i64 %n) {348; CHECK-LABEL: define void @smax_with_multiple_invariant_store_user_different_addr(349; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], ptr noalias [[DST_2:%.*]], i64 [[N:%.*]]) {350; CHECK-NEXT: [[ENTRY:.*]]:351; CHECK-NEXT: br label %[[LOOP:.*]]352; CHECK: [[LOOP]]:353; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]354; CHECK-NEXT: [[MAX:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]355; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]]356; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4357; CHECK-NEXT: [[MAX_NEXT]] = tail call i32 @llvm.smax.i32(i32 [[MAX]], i32 [[L]])358; CHECK-NEXT: store i32 [[MAX_NEXT]], ptr [[DST]], align 4359; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1360; CHECK-NEXT: store i32 [[MAX_NEXT]], ptr [[DST_2]], align 4361; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]362; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]363; CHECK: [[EXIT]]:364; CHECK-NEXT: ret void365;366entry:367 br label %loop368 369loop:370 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]371 %max = phi i32 [ 0, %entry ], [ %max.next, %loop ]372 %gep.src = getelementptr inbounds i32, ptr %src, i64 %iv373 %l = load i32, ptr %gep.src, align 4374 %max.next = tail call i32 @llvm.smax.i32(i32 %max, i32 %l)375 store i32 %max.next, ptr %dst, align 4376 %iv.next = add i64 %iv, 1377 store i32 %max.next, ptr %dst.2, align 4378 %ec = icmp eq i64 %iv, %n379 br i1 %ec, label %exit, label %loop380 381exit:382 ret void383}384 385define i32 @chained_instructions_feeding_max1(i32 %x, ptr %src) {386; CHECK-LABEL: define i32 @chained_instructions_feeding_max1(387; CHECK-SAME: i32 [[X:%.*]], ptr [[SRC:%.*]]) {388; CHECK-NEXT: [[ENTRY:.*]]:389; CHECK-NEXT: br label %[[LOOP:.*]]390; CHECK: [[LOOP]]:391; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]392; CHECK-NEXT: [[MAX:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]393; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr [3 x i32], ptr [[SRC]], i64 [[IV]]394; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4395; CHECK-NEXT: [[ADD:%.*]] = add i32 [[MAX]], [[L]]396; CHECK-NEXT: [[MAX_NEXT]] = tail call i32 @llvm.smax.i32(i32 [[ADD]], i32 [[L]])397; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1398; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1399; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]400; CHECK: [[EXIT]]:401; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi i32 [ [[MAX_NEXT]], %[[LOOP]] ]402; CHECK-NEXT: ret i32 [[MAX_NEXT_LCSSA]]403;404entry:405 br label %loop406 407loop: ; preds = %loop, %entry408 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]409 %max = phi i32 [ 0, %entry ], [ %max.next, %loop ]410 %gep.src = getelementptr [3 x i32], ptr %src, i64 %iv411 %l = load i32, ptr %gep.src, align 4412 %add = add i32 %max, %l413 %max.next = tail call i32 @llvm.smax.i32(i32 %add, i32 %l)414 %iv.next = add i64 %iv, 1415 %ec = icmp eq i64 %iv, 1416 br i1 %ec, label %exit, label %loop417 418exit:419 ret i32 %max.next420}421 422define i32 @chained_instructions_feeding_max2(i32 %x, ptr %src) {423; CHECK-LABEL: define i32 @chained_instructions_feeding_max2(424; CHECK-SAME: i32 [[X:%.*]], ptr [[SRC:%.*]]) {425; CHECK-NEXT: [[ENTRY:.*]]:426; CHECK-NEXT: br label %[[LOOP:.*]]427; CHECK: [[LOOP]]:428; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]429; CHECK-NEXT: [[MAX:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]430; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr [3 x i32], ptr [[SRC]], i64 [[IV]]431; CHECK-NEXT: [[MAX_1:%.*]] = tail call i32 @llvm.smax.i32(i32 [[X]], i32 [[MAX]])432; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4433; CHECK-NEXT: [[ADD:%.*]] = add i32 [[L]], [[MAX_1]]434; CHECK-NEXT: [[MAX_NEXT]] = tail call i32 @llvm.smax.i32(i32 [[ADD]], i32 100)435; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1436; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1437; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]438; CHECK: [[EXIT]]:439; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi i32 [ [[MAX_NEXT]], %[[LOOP]] ]440; CHECK-NEXT: ret i32 [[MAX_NEXT_LCSSA]]441;442entry:443 br label %loop444 445loop: ; preds = %loop, %entry446 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]447 %max = phi i32 [ 0, %entry ], [ %max.next, %loop ]448 %gep.src = getelementptr [3 x i32], ptr %src, i64 %iv449 %max.1 = tail call i32 @llvm.smax.i32(i32 %x, i32 %max)450 %l = load i32, ptr %gep.src, align 4451 %add = add i32 %l, %max.1452 %max.next = tail call i32 @llvm.smax.i32(i32 %add, i32 100)453 %iv.next = add i64 %iv, 1454 %ec = icmp eq i64 %iv, 1455 br i1 %ec, label %exit, label %loop456 457exit:458 ret i32 %max.next459}460 461 462define i32 @test_predicated_smin(ptr %src) {463; CHECK-LABEL: define i32 @test_predicated_smin(464; CHECK-SAME: ptr [[SRC:%.*]]) {465; CHECK-NEXT: [[ENTRY:.*:]]466; CHECK-NEXT: br label %[[VECTOR_PH:.*]]467; CHECK: [[VECTOR_PH]]:468; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]469; CHECK: [[VECTOR_BODY]]:470; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]471; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[PREDPHI:%.*]], %[[VECTOR_BODY]] ]472; CHECK-NEXT: [[TMP0:%.*]] = getelementptr float, ptr [[SRC]], i64 [[INDEX]]473; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 4474; CHECK-NEXT: [[TMP1:%.*]] = fcmp une <4 x float> [[WIDE_LOAD]], zeroinitializer475; CHECK-NEXT: [[TMP2:%.*]] = fdiv <4 x float> [[WIDE_LOAD]], splat (float 3.000000e+00)476; CHECK-NEXT: [[TMP3:%.*]] = fptosi <4 x float> [[TMP2]] to <4 x i32>477; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[TMP3]])478; CHECK-NEXT: [[PREDPHI]] = select <4 x i1> [[TMP1]], <4 x i32> [[TMP4]], <4 x i32> [[VEC_PHI]]479; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4480; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 112481; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]482; CHECK: [[MIDDLE_BLOCK]]:483; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[PREDPHI]])484; CHECK-NEXT: br label %[[EXIT:.*]]485; CHECK: [[EXIT]]:486; CHECK-NEXT: ret i32 [[TMP6]]487;488entry:489 br label %loop.header490 491loop.header:492 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]493 %min = phi i32 [ 0, %entry ], [ %min.merge, %loop.latch ]494 %gep.src = getelementptr float, ptr %src, i64 %iv495 %l = load float, ptr %gep.src, align 4496 %c = fcmp une float %l, 0.0497 br i1 %c, label %then, label %loop.latch498 499then:500 %div = fdiv float %l, 3.0501 %div.i32 = fptosi float %div to i32502 %min.next = tail call i32 @llvm.smin.i32(i32 %min, i32 %div.i32)503 br label %loop.latch504 505loop.latch:506 %min.merge = phi i32 [ %min.next, %then ], [ %min, %loop.header ]507 %iv.next = add i64 %iv, 1508 %ec = icmp eq i64 %iv, 111509 br i1 %ec, label %exit, label %loop.header510 511exit:512 ret i32 %min.merge513}514 515define i32 @smax_reduction_multiple_incoming(ptr %src, i32 %n, i1 %cond) {516; CHECK-LABEL: define i32 @smax_reduction_multiple_incoming(517; CHECK-SAME: ptr [[SRC:%.*]], i32 [[N:%.*]], i1 [[COND:%.*]]) {518; CHECK-NEXT: [[ENTRY:.*]]:519; CHECK-NEXT: br i1 [[COND]], label %[[LOOP_HEADER_PREHEADER:.*]], label %[[ELSE:.*]]520; CHECK: [[ELSE]]:521; CHECK-NEXT: br label %[[LOOP_HEADER_PREHEADER]]522; CHECK: [[LOOP_HEADER_PREHEADER]]:523; CHECK-NEXT: [[IV_PH:%.*]] = phi i32 [ 10, %[[ELSE]] ], [ 0, %[[ENTRY]] ]524; CHECK-NEXT: [[MAX_PH:%.*]] = phi i32 [ 5, %[[ELSE]] ], [ 0, %[[ENTRY]] ]525; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], 1526; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[IV_PH]]527; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 4528; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]529; CHECK: [[VECTOR_SCEVCHECK]]:530; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[N]], [[IV_PH]]531; CHECK-NEXT: br i1 [[TMP2]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]532; CHECK: [[VECTOR_PH]]:533; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 4534; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]]535; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[IV_PH]], [[N_VEC]]536; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[MAX_PH]], i64 0537; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer538; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]539; CHECK: [[VECTOR_BODY]]:540; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]541; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]542; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i32 [[IV_PH]], [[INDEX]]543; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i32 [[OFFSET_IDX]]544; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4545; CHECK-NEXT: [[TMP5]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])546; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4547; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]548; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]549; CHECK: [[MIDDLE_BLOCK]]:550; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP5]])551; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]]552; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]553; CHECK: [[SCALAR_PH]]:554; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ [[IV_PH]], %[[LOOP_HEADER_PREHEADER]] ], [ [[IV_PH]], %[[VECTOR_SCEVCHECK]] ]555; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ [[MAX_PH]], %[[LOOP_HEADER_PREHEADER]] ], [ [[MAX_PH]], %[[VECTOR_SCEVCHECK]] ]556; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]557; CHECK: [[LOOP_HEADER]]:558; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[LOOP_HEADER]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]559; CHECK-NEXT: [[MAX:%.*]] = phi i32 [ [[MAX_NEXT:%.*]], %[[LOOP_HEADER]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]560; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i32 [[IV]]561; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4562; CHECK-NEXT: [[MAX_NEXT]] = tail call i32 @llvm.smax.i32(i32 [[MAX]], i32 [[L]])563; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1564; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV]], [[N]]565; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP11:![0-9]+]]566; CHECK: [[EXIT]]:567; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi i32 [ [[MAX_NEXT]], %[[LOOP_HEADER]] ], [ [[TMP7]], %[[MIDDLE_BLOCK]] ]568; CHECK-NEXT: ret i32 [[MAX_NEXT_LCSSA]]569;570entry:571 br i1 %cond, label %loop.header, label %else572 573else:574 br label %loop.header575 576loop.header:577 %iv = phi i32 [ 0, %entry ], [ 10, %else ], [ %iv.next, %loop.header ]578 %max = phi i32 [ 0, %entry ], [ 5, %else ], [ %max.next, %loop.header ]579 %gep.src = getelementptr inbounds i32, ptr %src, i32 %iv580 %l = load i32, ptr %gep.src, align 4581 %max.next = tail call i32 @llvm.smax.i32(i32 %max, i32 %l)582 %iv.next = add i32 %iv, 1583 %ec = icmp eq i32 %iv, %n584 br i1 %ec, label %exit, label %loop.header585 586exit:587 ret i32 %max.next588}589