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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 62; RUN: opt -passes='loop-vectorize' -force-vector-width=4 -force-vector-interleave=1 -S < %s 2>&1 | FileCheck %s3 4target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"5 6; Make sure the selects generated from reduction are always emitted7; in deterministic order.8;9define i32 @foo() !prof !1 {10; CHECK-LABEL: define i32 @foo() {{.*}}{11; CHECK-NEXT: [[T16:.*:]]12; CHECK-NEXT: br label %[[VECTOR_PH:.*]]13; CHECK: [[VECTOR_PH]]:14; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]15; CHECK: [[VECTOR_BODY]]:16; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]17; CHECK-NEXT: [[VEC_PHI_1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[ADD_5:%.*]], %[[VECTOR_BODY]] ]18; CHECK-NEXT: [[VEC_PHI_2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[ADD_3:%.*]], %[[VECTOR_BODY]] ]19; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 020; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer21; CHECK-NEXT: [[VEC_IV:%.*]] = add <4 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1, i64 2, i64 3>22; CHECK-NEXT: [[TMP0:%.*]] = icmp ule <4 x i64> [[VEC_IV]], splat (i64 9)23; CHECK-NEXT: [[ADD_3]] = add <4 x i32> splat (i32 3), [[VEC_PHI_2]]24; CHECK-NEXT: [[ADD_5]] = add <4 x i32> [[VEC_PHI_1]], splat (i32 5)25; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> [[ADD_5]], <4 x i32> [[VEC_PHI_1]]26; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> [[ADD_3]], <4 x i32> [[VEC_PHI_2]]27; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 428; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1229; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !prof [[PROF1:![0-9]+]], !llvm.loop [[LOOP2:![0-9]+]]30; CHECK: [[MIDDLE_BLOCK]]:31; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3]])32; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP4]])33; CHECK-NEXT: br label %[[EXIT:.*]]34; CHECK: [[EXIT]]:35; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP7]], [[TMP6]]36; CHECK-NEXT: ret i32 [[ADD]]37;38entry:39 br label %loop40 41loop:42 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]43 %red.1 = phi i32 [ 0, %entry ], [ %red.1.next, %loop ]44 %red.2 = phi i32 [ 0, %entry ], [ %red.2.next, %loop ]45 %red.2.next = add i32 3, %red.246 %red.1.next = add i32 %red.1, 547 %iv.next = add nuw nsw i64 %iv, 148 %ec = icmp eq i64 %iv.next, 1049 br i1 %ec, label %exit, label %loop, !prof !250 51exit:52 %r.2 = phi i32 [ %red.2.next, %loop ]53 %r.1 = phi i32 [ %red.1.next, %loop ]54 %add = add i32 %r.2, %r.155 ret i32 %add56}57 58; Make sure we do not fail when checking for ordered reduction. This test just59; exercises the path and bails out without performing vectorization.60define double @quux(i1 %arg) {61; CHECK-LABEL: define double @quux(62; CHECK-SAME: i1 [[ARG:%.*]]) {63; CHECK-NEXT: [[ENTRY:.*]]:64; CHECK-NEXT: br label %[[HEADER:.*]]65; CHECK: [[HEADER]]:66; CHECK-NEXT: [[TMP5:%.*]] = phi double [ 1.300000e+01, %[[ENTRY]] ], [ [[TMP:%.*]], %[[LATCH:.*]] ]67; CHECK-NEXT: [[TMP6:%.*]] = fadd double [[TMP5]], 1.000000e+0068; CHECK-NEXT: br label %[[LATCH]]69; CHECK: [[LATCH]]:70; CHECK-NEXT: [[TMP]] = phi double [ [[TMP6]], %[[HEADER]] ]71; CHECK-NEXT: br i1 [[ARG]], label %[[HEADER]], label %[[EXIT:.*]]72; CHECK: [[EXIT]]:73; CHECK-NEXT: [[R:%.*]] = phi double [ [[TMP]], %[[LATCH]] ]74; CHECK-NEXT: ret double [[R]]75;76entry:77 br label %header78 79header:80 %tmp5 = phi double [ 1.300000e+01, %entry ], [ %tmp, %latch ]81 %tmp6 = fadd double %tmp5, 1.000000e+0082 br label %latch83 84latch:85 %tmp = phi double [ %tmp6, %header ]86 br i1 %arg, label %header, label %exit87 88exit:89 %r = phi double [ %tmp, %latch ]90 ret double %r91}92 93!1 = !{!"function_entry_count", i64 801}94!2 = !{!"branch_weights", i32 746, i32 1}95