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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -p loop-vectorize -force-vector-width=2 -S %s | FileCheck %s3 4declare noalias noundef ptr @calloc(i64 noundef, i64 noundef)5 6define void @reuse_lcssa_phi_for_add_rec1(ptr %head) {7; CHECK-LABEL: define void @reuse_lcssa_phi_for_add_rec1(8; CHECK-SAME: ptr [[HEAD:%.*]]) {9; CHECK-NEXT: [[ENTRY:.*]]:10; CHECK-NEXT: br label %[[LOOP_1:.*]]11; CHECK: [[LOOP_1]]:12; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_1]] ]13; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP_1]] ]14; CHECK-NEXT: [[FOR:%.*]] = phi ptr [ [[HEAD]], %[[ENTRY]] ], [ [[L_1:%.*]], %[[LOOP_1]] ]15; CHECK-NEXT: [[L_1]] = load ptr, ptr [[FOR]], align 816; CHECK-NEXT: [[IV_2_NEXT]] = add nuw nsw i32 [[IV_2]], 117; CHECK-NEXT: [[EC_1:%.*]] = icmp eq ptr [[L_1]], null18; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 119; CHECK-NEXT: br i1 [[EC_1]], label %[[PH:.*]], label %[[LOOP_1]]20; CHECK: [[PH]]:21; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i64 [ [[IV]], %[[LOOP_1]] ]22; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[IV_2_NEXT]], %[[LOOP_1]] ]23; CHECK-NEXT: [[SRC_2:%.*]] = tail call noalias noundef dereferenceable_or_null(8) ptr @calloc(i64 1, i64 8)24; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 1)25; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[SMIN]]26; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i6427; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 128; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 229; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]30; CHECK: [[VECTOR_PH]]:31; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 232; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]33; CHECK-NEXT: [[TMP4:%.*]] = sub i64 [[IV_LCSSA]], [[N_VEC]]34; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]35; CHECK: [[VECTOR_BODY]]:36; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]37; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i64 [[IV_LCSSA]], [[INDEX]]38; CHECK-NEXT: [[TMP5:%.*]] = getelementptr ptr, ptr [[SRC_2]], i64 [[OFFSET_IDX]]39; CHECK-NEXT: [[TMP6:%.*]] = getelementptr ptr, ptr [[TMP5]], i64 040; CHECK-NEXT: [[TMP7:%.*]] = getelementptr ptr, ptr [[TMP6]], i64 -141; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x ptr>, ptr [[TMP7]], align 842; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <2 x ptr> [[WIDE_LOAD]], <2 x ptr> poison, <2 x i32> <i32 1, i32 0>43; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x ptr> [[REVERSE]], i32 044; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x ptr> [[REVERSE]], i32 145; CHECK-NEXT: store ptr null, ptr [[TMP8]], align 846; CHECK-NEXT: store ptr null, ptr [[TMP9]], align 847; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 248; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]49; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]50; CHECK: [[MIDDLE_BLOCK]]:51; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]52; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]]53; CHECK: [[SCALAR_PH]]:54; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ [[IV_LCSSA]], %[[PH]] ]55; CHECK-NEXT: br label %[[LOOP_2:.*]]56; CHECK: [[LOOP_2]]:57; CHECK-NEXT: [[IV_3:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT_3:%.*]], %[[LOOP_2]] ]58; CHECK-NEXT: [[IV_NEXT_3]] = add nsw i64 [[IV_3]], -159; CHECK-NEXT: [[GEP_SRC_2:%.*]] = getelementptr ptr, ptr [[SRC_2]], i64 [[IV_3]]60; CHECK-NEXT: [[L:%.*]] = load ptr, ptr [[GEP_SRC_2]], align 861; CHECK-NEXT: store ptr null, ptr [[L]], align 862; CHECK-NEXT: [[T:%.*]] = trunc nuw i64 [[IV_3]] to i3263; CHECK-NEXT: [[EC_2:%.*]] = icmp sgt i32 [[T]], 164; CHECK-NEXT: br i1 [[EC_2]], label %[[LOOP_2]], label %[[FOR_END]], !llvm.loop [[LOOP3:![0-9]+]]65; CHECK: [[FOR_END]]:66; CHECK-NEXT: ret void67;68entry:69 br label %loop.170 71loop.1:72 %iv = phi i64 [ 1, %entry ], [ %iv.next, %loop.1 ]73 %iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop.1 ]74 %for = phi ptr [ %head, %entry ], [ %l.1, %loop.1 ]75 %l.1 = load ptr, ptr %for, align 876 %iv.2.next = add nuw nsw i32 %iv.2, 177 %ec.1 = icmp eq ptr %l.1, null78 %iv.next = add nuw i64 %iv, 179 br i1 %ec.1, label %ph, label %loop.180 81ph:82 %iv.lcssa = phi i64 [ %iv, %loop.1 ]83 %iv.2.next.lcssa = phi i32 [ %iv.2.next, %loop.1 ]84 %src.2 = tail call noalias noundef dereferenceable_or_null(8) ptr @calloc(i64 1, i64 8)85 br label %loop.286 87loop.2:88 %iv.3 = phi i64 [ %iv.lcssa, %ph ], [ %iv.next.3, %loop.2 ]89 %iv.next.3 = add nsw i64 %iv.3, -190 %gep.src.2 = getelementptr ptr, ptr %src.2, i64 %iv.391 %l = load ptr, ptr %gep.src.2, align 892 store ptr null, ptr %l, align 893 %t = trunc nuw i64 %iv.3 to i3294 %ec.2 = icmp sgt i32 %t, 195 br i1 %ec.2, label %loop.2, label %for.end96 97for.end:98 ret void99}100 101declare i32 @val()102 103define void @runtime_checks_ptr_inductions(ptr %dst.1, ptr %dst.2, i1 %c) {104; CHECK-LABEL: define void @runtime_checks_ptr_inductions(105; CHECK-SAME: ptr [[DST_1:%.*]], ptr [[DST_2:%.*]], i1 [[C:%.*]]) {106; CHECK-NEXT: [[ENTRY:.*]]:107; CHECK-NEXT: br label %[[LOOP_1:.*]]108; CHECK: [[LOOP_1]]:109; CHECK-NEXT: [[PTR_IV_1:%.*]] = phi ptr [ [[DST_1]], %[[ENTRY]] ], [ [[PTR_IV_1_NEXT:%.*]], %[[LOOP_1]] ]110; CHECK-NEXT: [[CALL:%.*]] = call i32 @val()111; CHECK-NEXT: [[SEL_DST:%.*]] = select i1 [[C]], ptr [[DST_1]], ptr [[DST_2]]112; CHECK-NEXT: [[SEL_DST_LCSSA12:%.*]] = ptrtoint ptr [[SEL_DST]] to i64113; CHECK-NEXT: [[PTR_IV_1_NEXT]] = getelementptr i8, ptr [[PTR_IV_1]], i64 1114; CHECK-NEXT: [[EC_1:%.*]] = icmp eq i32 [[CALL]], 0115; CHECK-NEXT: br i1 [[EC_1]], label %[[LOOP_2_HEADER_PREHEADER:.*]], label %[[LOOP_1]]116; CHECK: [[LOOP_2_HEADER_PREHEADER]]:117; CHECK-NEXT: [[PTR_IV_1_LCSSA:%.*]] = phi ptr [ [[PTR_IV_1]], %[[LOOP_1]] ]118; CHECK-NEXT: [[SEL_DST_LCSSA:%.*]] = phi ptr [ [[SEL_DST]], %[[LOOP_1]] ]119; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]120; CHECK: [[VECTOR_MEMCHECK]]:121; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[PTR_IV_1_LCSSA]] to i64122; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[SEL_DST_LCSSA12]]123; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP1]], 2124; CHECK-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]125; CHECK: [[VECTOR_PH]]:126; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[PTR_IV_1_LCSSA]], i64 1022127; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[SEL_DST_LCSSA]], i64 1022128; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]129; CHECK: [[VECTOR_BODY]]:130; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]131; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PTR_IV_1_LCSSA]], i64 [[INDEX]]132; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[SEL_DST_LCSSA]], i64 [[INDEX]]133; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[NEXT_GEP4]], align 1134; CHECK-NEXT: store <2 x i8> [[WIDE_LOAD]], ptr [[NEXT_GEP]], align 1135; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2136; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1022137; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]138; CHECK: [[MIDDLE_BLOCK]]:139; CHECK-NEXT: br label %[[SCALAR_PH]]140; CHECK: [[SCALAR_PH]]:141; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 1023, %[[MIDDLE_BLOCK]] ], [ 1, %[[VECTOR_MEMCHECK]] ]142; CHECK-NEXT: [[BC_RESUME_VAL3:%.*]] = phi ptr [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[PTR_IV_1_LCSSA]], %[[VECTOR_MEMCHECK]] ]143; CHECK-NEXT: [[BC_RESUME_VAL4:%.*]] = phi ptr [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ [[SEL_DST_LCSSA]], %[[VECTOR_MEMCHECK]] ]144; CHECK-NEXT: br label %[[LOOP_2_HEADER:.*]]145; CHECK: [[LOOP_2_HEADER]]:146; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[DEC7:%.*]], %[[LOOP_2_LATCH:.*]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]147; CHECK-NEXT: [[PTR_IV_2:%.*]] = phi ptr [ [[PTR_IV_2_NEXT:%.*]], %[[LOOP_2_LATCH]] ], [ [[BC_RESUME_VAL3]], %[[SCALAR_PH]] ]148; CHECK-NEXT: [[PTR_IV_3:%.*]] = phi ptr [ [[PTR_IV_3_NEXT:%.*]], %[[LOOP_2_LATCH]] ], [ [[BC_RESUME_VAL4]], %[[SCALAR_PH]] ]149; CHECK-NEXT: [[EC_2:%.*]] = icmp eq i32 [[IV]], 1024150; CHECK-NEXT: br i1 [[EC_2]], label %[[EXIT:.*]], label %[[LOOP_2_LATCH]]151; CHECK: [[LOOP_2_LATCH]]:152; CHECK-NEXT: [[DEC7]] = add i32 [[IV]], 1153; CHECK-NEXT: [[PTR_IV_3_NEXT]] = getelementptr i8, ptr [[PTR_IV_3]], i64 1154; CHECK-NEXT: [[L:%.*]] = load i8, ptr [[PTR_IV_3]], align 1155; CHECK-NEXT: [[PTR_IV_2_NEXT]] = getelementptr i8, ptr [[PTR_IV_2]], i64 1156; CHECK-NEXT: store i8 [[L]], ptr [[PTR_IV_2]], align 1157; CHECK-NEXT: br label %[[LOOP_2_HEADER]], !llvm.loop [[LOOP5:![0-9]+]]158; CHECK: [[EXIT]]:159; CHECK-NEXT: ret void160;161entry:162 br label %loop.1163 164loop.1:165 %ptr.iv.1 = phi ptr [ %dst.1, %entry ], [ %ptr.iv.1.next, %loop.1 ]166 %call = call i32 @val()167 %sel.dst = select i1 %c, ptr %dst.1, ptr %dst.2168 %ptr.iv.1.next = getelementptr i8, ptr %ptr.iv.1, i64 1169 %ec.1 = icmp eq i32 %call, 0170 br i1 %ec.1, label %loop.2.header, label %loop.1171 172loop.2.header:173 %iv = phi i32 [ 1, %loop.1 ], [ %dec7, %loop.2.latch ]174 %ptr.iv.2 = phi ptr [ %ptr.iv.1, %loop.1 ], [ %ptr.iv.2.next, %loop.2.latch ]175 %ptr.iv.3 = phi ptr [ %sel.dst, %loop.1 ], [ %ptr.iv.3.next, %loop.2.latch ]176 %ec.2 = icmp eq i32 %iv, 1024177 br i1 %ec.2, label %exit, label %loop.2.latch178 179loop.2.latch:180 %dec7 = add i32 %iv, 1181 %ptr.iv.3.next = getelementptr i8, ptr %ptr.iv.3, i64 1182 %l = load i8, ptr %ptr.iv.3, align 1183 %ptr.iv.2.next = getelementptr i8, ptr %ptr.iv.2, i64 1184 store i8 %l, ptr %ptr.iv.2, align 1185 br label %loop.2.header186 187exit:188 ret void189}190 191 192declare void @foo()193declare void @bar()194 195define void @expand_diff_scev_unknown(ptr %dst, i1 %invar.c, i32 %step) mustprogress {196; CHECK-LABEL: define void @expand_diff_scev_unknown(197; CHECK-SAME: ptr [[DST:%.*]], i1 [[INVAR_C:%.*]], i32 [[STEP:%.*]]) #[[ATTR0:[0-9]+]] {198; CHECK-NEXT: [[ENTRY:.*]]:199; CHECK-NEXT: br label %[[LOOP_1:.*]]200; CHECK: [[LOOP_1]]:201; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], %[[LOOP_1]] ], [ 0, %[[ENTRY]] ]202; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ [[STEP]], %[[ENTRY]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP_1]] ]203; CHECK-NEXT: call void @foo()204; CHECK-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1205; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1206; CHECK-NEXT: br i1 [[INVAR_C]], label %[[LOOP_2_PREHEADER:.*]], label %[[LOOP_1]]207; CHECK: [[LOOP_2_PREHEADER]]:208; CHECK-NEXT: [[IV_1_LCSSA:%.*]] = phi i32 [ [[IV_1]], %[[LOOP_1]] ]209; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[IV_1_LCSSA]], [[STEP]]210; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP1]], i32 0)211; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[STEP]], -2212; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[INDVAR]], -1213; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], [[TMP2]]214; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[SMAX]], [[TMP4]]215; CHECK-NEXT: [[UMIN:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP5]], i32 1)216; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[UMIN]], 1217; CHECK-NEXT: [[TMP7:%.*]] = sub i32 [[TMP5]], [[UMIN]]218; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[STEP]], i32 1)219; CHECK-NEXT: [[TMP8:%.*]] = udiv i32 [[TMP7]], [[UMAX]]220; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[TMP6]], [[TMP8]]221; CHECK-NEXT: [[TMP16:%.*]] = sub i32 2, [[STEP]]222; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[IV_1_LCSSA]], [[TMP16]]223; CHECK-NEXT: [[SMAX1:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP12]], i32 0)224; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP3]], -1225; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[SMAX1]], [[TMP14]]226; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP15]], 2227; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]228; CHECK: [[VECTOR_SCEVCHECK]]:229; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STEP]], 1230; CHECK-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]231; CHECK: [[VECTOR_PH]]:232; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP15]], 2233; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP15]], [[N_MOD_VF]]234; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[IV_1_LCSSA]], [[N_VEC]]235; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]236; CHECK: [[VECTOR_BODY]]:237; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]238; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i32 [[IV_1_LCSSA]], [[INDEX]]239; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[OFFSET_IDX]]240; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[TMP11]], align 4241; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2242; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]243; CHECK-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]244; CHECK: [[MIDDLE_BLOCK]]:245; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP15]], [[N_VEC]]246; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]247; CHECK: [[SCALAR_PH]]:248; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ [[IV_1_LCSSA]], %[[LOOP_2_PREHEADER]] ], [ [[IV_1_LCSSA]], %[[VECTOR_SCEVCHECK]] ]249; CHECK-NEXT: br label %[[LOOP_2:.*]]250; CHECK: [[LOOP_2]]:251; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[IV_2_NEXT:%.*]], %[[LOOP_2]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]252; CHECK-NEXT: [[IV_2_NEXT]] = add nsw i32 [[IV_2]], [[STEP]]253; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[IV_2]]254; CHECK-NEXT: store i32 0, ptr [[GEP_DST]], align 4255; CHECK-NEXT: [[EC_2:%.*]] = icmp slt i32 [[IV_2_NEXT]], 0256; CHECK-NEXT: br i1 [[EC_2]], label %[[LOOP_2]], label %[[EXIT]], !llvm.loop [[LOOP7:![0-9]+]]257; CHECK: [[EXIT]]:258; CHECK-NEXT: ret void259;260entry:261 br label %loop.1262 263loop.1:264 %iv.1 = phi i32 [ %step, %entry ], [ %iv.1.next, %loop.1 ]265 call void @foo()266 %iv.1.next = add i32 %iv.1, 1267 br i1 %invar.c, label %loop.2, label %loop.1268 269loop.2:270 %iv.2 = phi i32 [ %iv.1, %loop.1 ], [ %iv.2.next, %loop.2 ]271 %iv.2.next = add nsw i32 %iv.2, %step272 %gep.dst = getelementptr inbounds i32, ptr %dst, i32 %iv.2273 store i32 0, ptr %gep.dst274 %ec.2 = icmp slt i32 %iv.2.next, 0275 br i1 %ec.2, label %loop.2, label %exit276 277exit:278 ret void279}280 281define void @expand_diff_neg_ptrtoint_expr(ptr %src, ptr %start) {282; CHECK-LABEL: define void @expand_diff_neg_ptrtoint_expr(283; CHECK-SAME: ptr [[SRC:%.*]], ptr [[START:%.*]]) {284; CHECK-NEXT: [[ENTRY:.*]]:285; CHECK-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64286; CHECK-NEXT: br label %[[LOOP_1:.*]]287; CHECK: [[LOOP_1]]:288; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_1]] ]289; CHECK-NEXT: [[PTR_IV_1:%.*]] = phi ptr [ [[START]], %[[ENTRY]] ], [ [[PTR_IV_1_NEXT:%.*]], %[[LOOP_1]] ]290; CHECK-NEXT: [[PTR_IV_1_NEXT]] = getelementptr i8, ptr [[PTR_IV_1]], i64 8291; CHECK-NEXT: call void @foo()292; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1293; CHECK-NEXT: [[EC_1:%.*]] = icmp eq i64 [[IV_NEXT]], 32294; CHECK-NEXT: br i1 [[EC_1]], label %[[LOOP_2_PREHEADER:.*]], label %[[LOOP_1]]295; CHECK: [[LOOP_2_PREHEADER]]:296; CHECK-NEXT: [[PTR_IV_1_NEXT_LCSSA:%.*]] = phi ptr [ [[PTR_IV_1_NEXT]], %[[LOOP_1]] ]297; CHECK-NEXT: br label %[[LOOP_2:.*]]298; CHECK: [[LOOP_2]]:299; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ [[IV_NEXT_1:%.*]], %[[LOOP_2]] ], [ 1, %[[LOOP_2_PREHEADER]] ]300; CHECK-NEXT: [[PTR_IV_2:%.*]] = phi ptr [ [[PTR_IV_2_NEXT:%.*]], %[[LOOP_2]] ], [ [[PTR_IV_1_NEXT_LCSSA]], %[[LOOP_2_PREHEADER]] ]301; CHECK-NEXT: call void @bar()302; CHECK-NEXT: [[PTR_IV_2_NEXT]] = getelementptr i8, ptr [[PTR_IV_2]], i64 8303; CHECK-NEXT: [[IV_NEXT_1]] = add i64 [[IV_1]], 1304; CHECK-NEXT: [[EC_2:%.*]] = icmp eq i64 [[IV_NEXT_1]], 32305; CHECK-NEXT: br i1 [[EC_2]], label %[[LOOP_3_PREHEADER:.*]], label %[[LOOP_2]]306; CHECK: [[LOOP_3_PREHEADER]]:307; CHECK-NEXT: [[TMP1:%.*]] = phi ptr [ [[PTR_IV_2_NEXT]], %[[LOOP_2]] ]308; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]309; CHECK: [[VECTOR_MEMCHECK]]:310; CHECK-NEXT: [[TMP0:%.*]] = sub i64 0, [[SRC2]]311; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[TMP1]] to i64312; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP5]], [[TMP0]]313; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP2]], 16314; CHECK-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]315; CHECK: [[VECTOR_PH]]:316; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP1]], i64 -16317; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]318; CHECK: [[VECTOR_BODY]]:319; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]320; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]]321; CHECK-NEXT: [[OFFSET_IDX5:%.*]] = mul i64 [[INDEX]], 8322; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[TMP1]], i64 [[OFFSET_IDX5]]323; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], -1324; CHECK-NEXT: [[TMP8:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP7]]325; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP8]], align 8326; CHECK-NEXT: store <2 x i64> [[WIDE_LOAD]], ptr [[NEXT_GEP]], align 8327; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2328; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], -2329; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]330; CHECK: [[MIDDLE_BLOCK]]:331; CHECK-NEXT: br label %[[SCALAR_PH]]332; CHECK: [[SCALAR_PH]]:333; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ -1, %[[MIDDLE_BLOCK]] ], [ 1, %[[VECTOR_MEMCHECK]] ]334; CHECK-NEXT: [[BC_RESUME_VAL3:%.*]] = phi ptr [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ [[TMP1]], %[[VECTOR_MEMCHECK]] ]335; CHECK-NEXT: br label %[[LOOP_3:.*]]336; CHECK: [[LOOP_3]]:337; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[IV_NEXT_2:%.*]], %[[LOOP_3]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]338; CHECK-NEXT: [[PTR_IV_3:%.*]] = phi ptr [ [[PTR_IV_3_NEXT:%.*]], %[[LOOP_3]] ], [ [[BC_RESUME_VAL3]], %[[SCALAR_PH]] ]339; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[IV_2]], -1340; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP12]]341; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP_SRC]], align 8342; CHECK-NEXT: [[PTR_IV_3_NEXT]] = getelementptr i8, ptr [[PTR_IV_3]], i64 8343; CHECK-NEXT: store i64 [[L]], ptr [[PTR_IV_3]], align 8344; CHECK-NEXT: [[IV_NEXT_2]] = add i64 [[IV_2]], 1345; CHECK-NEXT: [[EC_3:%.*]] = icmp eq i64 [[IV_NEXT_2]], 0346; CHECK-NEXT: br i1 [[EC_3]], label %[[EXIT:.*]], label %[[LOOP_3]], !llvm.loop [[LOOP9:![0-9]+]]347; CHECK: [[EXIT]]:348; CHECK-NEXT: ret void349;350entry:351 br label %loop.1352 353loop.1:354 %iv = phi i64 [ 1, %entry ], [ %iv.next, %loop.1 ]355 %ptr.iv.1 = phi ptr [ %start, %entry ], [ %ptr.iv.1.next, %loop.1 ]356 %ptr.iv.1.next = getelementptr i8, ptr %ptr.iv.1, i64 8357 call void @foo()358 %iv.next = add i64 %iv, 1359 %ec.1 = icmp eq i64 %iv.next, 32360 br i1 %ec.1, label %loop.2, label %loop.1361 362loop.2:363 %iv.1 = phi i64 [ 1, %loop.1 ], [ %iv.next.1, %loop.2 ]364 %ptr.iv.2 = phi ptr [ %ptr.iv.1.next, %loop.1 ], [ %ptr.iv.2.next, %loop.2 ]365 call void @bar()366 %ptr.iv.2.next = getelementptr i8, ptr %ptr.iv.2, i64 8367 %iv.next.1 = add i64 %iv.1, 1368 %ec.2 = icmp eq i64 %iv.next.1, 32369 br i1 %ec.2, label %loop.3, label %loop.2370 371loop.3:372 %iv.2 = phi i64 [ 1, %loop.2 ], [ %iv.next.2, %loop.3 ]373 %ptr.iv.3 = phi ptr [ %ptr.iv.2.next, %loop.2 ], [ %ptr.iv.3.next, %loop.3 ]374 %6 = add i64 %iv.2, -1375 %gep.src = getelementptr double, ptr %src, i64 %6376 %l = load i64, ptr %gep.src, align 8377 %ptr.iv.3.next = getelementptr i8, ptr %ptr.iv.3, i64 8378 store i64 %l, ptr %ptr.iv.3, align 8379 %iv.next.2 = add i64 %iv.2, 1380 %ec.3 = icmp eq i64 %iv.next.2, 0381 br i1 %ec.3, label %exit, label %loop.3382 383exit:384 ret void385}386 387 388declare i1 @cond()389 390define void @scev_exp_reuse_const_add(ptr %dst, ptr %src) {391; CHECK-LABEL: define void @scev_exp_reuse_const_add(392; CHECK-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]]) {393; CHECK-NEXT: [[ENTRY:.*]]:394; CHECK-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64395; CHECK-NEXT: br label %[[LOOP_1:.*]]396; CHECK: [[LOOP_1]]:397; CHECK-NEXT: [[PTR_IV_1:%.*]] = phi ptr [ [[DST]], %[[ENTRY]] ], [ [[PTR_IV_1_NEXT:%.*]], %[[LOOP_1]] ]398; CHECK-NEXT: [[PTR_IV_1_NEXT]] = getelementptr i8, ptr [[PTR_IV_1]], i64 2399; CHECK-NEXT: [[C:%.*]] = call i1 @cond()400; CHECK-NEXT: br i1 [[C]], label %[[LOOP_2_PH:.*]], label %[[LOOP_1]]401; CHECK: [[LOOP_2_PH]]:402; CHECK-NEXT: [[PTR_IV_1_NEXT_LCSSA:%.*]] = phi ptr [ [[PTR_IV_1_NEXT]], %[[LOOP_1]] ]403; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]404; CHECK: [[VECTOR_MEMCHECK]]:405; CHECK-NEXT: [[TMP0:%.*]] = sub i64 -2, [[SRC2]]406; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR_IV_1_NEXT_LCSSA]] to i64407; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], [[TMP0]]408; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP2]], 4409; CHECK-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]410; CHECK: [[VECTOR_PH]]:411; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[PTR_IV_1_NEXT_LCSSA]], i64 80412; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]413; CHECK: [[VECTOR_BODY]]:414; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]415; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 2416; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PTR_IV_1_NEXT_LCSSA]], i64 [[OFFSET_IDX]]417; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 1418; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i16, ptr [[SRC]], i64 [[TMP4]]419; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i16>, ptr [[TMP5]], align 2420; CHECK-NEXT: store <2 x i16> [[WIDE_LOAD]], ptr [[NEXT_GEP]], align 2421; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2422; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 40423; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]424; CHECK: [[MIDDLE_BLOCK]]:425; CHECK-NEXT: br label %[[SCALAR_PH]]426; CHECK: [[SCALAR_PH]]:427; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 40, %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_MEMCHECK]] ]428; CHECK-NEXT: [[BC_RESUME_VAL2:%.*]] = phi ptr [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ [[PTR_IV_1_NEXT_LCSSA]], %[[VECTOR_MEMCHECK]] ]429; CHECK-NEXT: br label %[[LOOP_2:.*]]430; CHECK: [[LOOP_2]]:431; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP_2]] ]432; CHECK-NEXT: [[PTR_IV_2:%.*]] = phi ptr [ [[BC_RESUME_VAL2]], %[[SCALAR_PH]] ], [ [[PTR_IV_2_NEXT:%.*]], %[[LOOP_2]] ]433; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_1]], 1434; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr i16, ptr [[SRC]], i64 [[IV_2_NEXT]]435; CHECK-NEXT: [[L:%.*]] = load i16, ptr [[GEP_SRC_1]], align 2436; CHECK-NEXT: [[PTR_IV_2_NEXT]] = getelementptr i8, ptr [[PTR_IV_2]], i64 2437; CHECK-NEXT: store i16 [[L]], ptr [[PTR_IV_2]], align 2438; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_1]], 40439; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_2]], !llvm.loop [[LOOP11:![0-9]+]]440; CHECK: [[EXIT]]:441; CHECK-NEXT: ret void442;443entry:444 br label %loop.1445 446loop.1:447 %ptr.iv.1 = phi ptr [ %dst, %entry ], [ %ptr.iv.1.next, %loop.1 ]448 %ptr.iv.1.next = getelementptr i8, ptr %ptr.iv.1, i64 2449 %c = call i1 @cond()450 br i1 %c, label %loop.2.ph, label %loop.1451 452loop.2.ph:453 br label %loop.2454 455loop.2:456 %iv.1 = phi i64 [ 0, %loop.2.ph ], [ %iv.2.next, %loop.2 ]457 %ptr.iv.2 = phi ptr [ %ptr.iv.1.next, %loop.2.ph ], [ %ptr.iv.2.next, %loop.2 ]458 %iv.2.next = add i64 %iv.1, 1459 %gep.src.1 = getelementptr i16, ptr %src, i64 %iv.2.next460 %l = load i16, ptr %gep.src.1, align 2461 %ptr.iv.2.next = getelementptr i8, ptr %ptr.iv.2, i64 2462 store i16 %l, ptr %ptr.iv.2, align 2463 %ec = icmp eq i64 %iv.1, 40464 br i1 %ec, label %exit, label %loop.2465 466exit:467 ret void468}469 470; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)471declare double @llvm.cos.f64(double) #0472 473attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }474