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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -o - -S %s | FileCheck %s3 4; Test case with a large number of pointer groups to check for memory5; conflicts, but with many redundant checks that can be simplified.6define void @test_large_number_of_group(ptr %dst, i64 %off, i64 %N) {7; CHECK-LABEL: @test_large_number_of_group(8; CHECK-NEXT: entry:9; CHECK-NEXT: [[OFF_MUL_2:%.*]] = shl i64 [[OFF:%.*]], 110; CHECK-NEXT: [[OFF_MUL_3:%.*]] = mul i64 [[OFF]], 311; CHECK-NEXT: [[OFF_MUL_4:%.*]] = shl i64 [[OFF]], 212; CHECK-NEXT: [[OFF_MUL_5:%.*]] = mul i64 [[OFF]], 513; CHECK-NEXT: [[OFF_MUL_6:%.*]] = mul i64 [[OFF]], 614; CHECK-NEXT: [[OFF_MUL_7:%.*]] = mul i64 [[OFF]], 715; CHECK-NEXT: [[OFF_MUL_8:%.*]] = shl i64 [[OFF]], 316; CHECK-NEXT: [[OFF_MUL_9:%.*]] = mul i64 [[OFF]], 917; CHECK-NEXT: [[OFF_MUL_10:%.*]] = mul i64 [[OFF]], 1018; CHECK-NEXT: [[OFF_MUL_11:%.*]] = mul i64 [[OFF]], 1119; CHECK-NEXT: [[OFF_MUL_12:%.*]] = mul i64 [[OFF]], 1220; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N:%.*]], 421; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]]22; CHECK: vector.memcheck:23; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[OFF_MUL_8]], 3224; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[OFF]], 425; CHECK-NEXT: [[DIFF_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 3226; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK1]]27; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[OFF]], 2428; CHECK-NEXT: [[DIFF_CHECK2:%.*]] = icmp ult i64 [[TMP1]], 3229; CHECK-NEXT: [[CONFLICT_RDX3:%.*]] = or i1 [[CONFLICT_RDX]], [[DIFF_CHECK2]]30; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[OFF]], 531; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP2]], 3232; CHECK-NEXT: [[CONFLICT_RDX5:%.*]] = or i1 [[CONFLICT_RDX3]], [[DIFF_CHECK4]]33; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[OFF]], 4034; CHECK-NEXT: [[DIFF_CHECK6:%.*]] = icmp ult i64 [[TMP3]], 3235; CHECK-NEXT: [[CONFLICT_RDX7:%.*]] = or i1 [[CONFLICT_RDX5]], [[DIFF_CHECK6]]36; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[OFF]], 4837; CHECK-NEXT: [[DIFF_CHECK8:%.*]] = icmp ult i64 [[TMP4]], 3238; CHECK-NEXT: [[CONFLICT_RDX9:%.*]] = or i1 [[CONFLICT_RDX7]], [[DIFF_CHECK8]]39; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[OFF]], 5640; CHECK-NEXT: [[DIFF_CHECK10:%.*]] = icmp ult i64 [[TMP5]], 3241; CHECK-NEXT: [[CONFLICT_RDX11:%.*]] = or i1 [[CONFLICT_RDX9]], [[DIFF_CHECK10]]42; CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[OFF]], 643; CHECK-NEXT: [[DIFF_CHECK12:%.*]] = icmp ult i64 [[TMP6]], 3244; CHECK-NEXT: [[CONFLICT_RDX13:%.*]] = or i1 [[CONFLICT_RDX11]], [[DIFF_CHECK12]]45; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[OFF]], 7246; CHECK-NEXT: [[DIFF_CHECK14:%.*]] = icmp ult i64 [[TMP7]], 3247; CHECK-NEXT: [[CONFLICT_RDX15:%.*]] = or i1 [[CONFLICT_RDX13]], [[DIFF_CHECK14]]48; CHECK-NEXT: [[TMP8:%.*]] = mul i64 [[OFF]], 8049; CHECK-NEXT: [[DIFF_CHECK16:%.*]] = icmp ult i64 [[TMP8]], 3250; CHECK-NEXT: [[CONFLICT_RDX17:%.*]] = or i1 [[CONFLICT_RDX15]], [[DIFF_CHECK16]]51; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[OFF]], 8852; CHECK-NEXT: [[DIFF_CHECK18:%.*]] = icmp ult i64 [[TMP9]], 3253; CHECK-NEXT: [[CONFLICT_RDX19:%.*]] = or i1 [[CONFLICT_RDX17]], [[DIFF_CHECK18]]54; CHECK-NEXT: br i1 [[CONFLICT_RDX19]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]55; CHECK: vector.ph:56; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 457; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]58; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]59; CHECK: vector.body:60; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]61; CHECK-NEXT: [[TMP11:%.*]] = add nsw i64 [[INDEX]], -562; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP11]], [[OFF]]63; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i64, ptr [[DST:%.*]], i64 [[TMP12]]64; CHECK-NEXT: store <4 x double> zeroinitializer, ptr [[TMP14]], align 865; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP11]], [[OFF_MUL_2]]66; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP15]]67; CHECK-NEXT: store <4 x double> zeroinitializer, ptr [[TMP17]], align 868; CHECK-NEXT: [[TMP18:%.*]] = add i64 [[TMP11]], [[OFF_MUL_3]]69; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP18]]70; CHECK-NEXT: store <4 x double> zeroinitializer, ptr [[TMP20]], align 871; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[TMP11]], [[OFF_MUL_4]]72; CHECK-NEXT: [[TMP23:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP21]]73; CHECK-NEXT: store <4 x double> zeroinitializer, ptr [[TMP23]], align 874; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[TMP11]], [[OFF_MUL_5]]75; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP24]]76; CHECK-NEXT: store <4 x double> zeroinitializer, ptr [[TMP26]], align 877; CHECK-NEXT: [[TMP27:%.*]] = add i64 [[TMP11]], [[OFF_MUL_6]]78; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP27]]79; CHECK-NEXT: store <4 x double> zeroinitializer, ptr [[TMP29]], align 880; CHECK-NEXT: [[TMP30:%.*]] = add i64 [[TMP11]], [[OFF_MUL_7]]81; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP30]]82; CHECK-NEXT: store <4 x double> zeroinitializer, ptr [[TMP32]], align 883; CHECK-NEXT: [[TMP33:%.*]] = add i64 [[TMP11]], [[OFF_MUL_8]]84; CHECK-NEXT: [[TMP35:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP33]]85; CHECK-NEXT: store <4 x double> zeroinitializer, ptr [[TMP35]], align 886; CHECK-NEXT: [[TMP36:%.*]] = add i64 [[TMP11]], [[OFF_MUL_9]]87; CHECK-NEXT: [[TMP38:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP36]]88; CHECK-NEXT: store <4 x double> zeroinitializer, ptr [[TMP38]], align 889; CHECK-NEXT: [[TMP39:%.*]] = add i64 [[TMP11]], [[OFF_MUL_10]]90; CHECK-NEXT: [[TMP41:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP39]]91; CHECK-NEXT: store <4 x double> zeroinitializer, ptr [[TMP41]], align 892; CHECK-NEXT: [[TMP42:%.*]] = add i64 [[TMP11]], [[OFF_MUL_11]]93; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP42]]94; CHECK-NEXT: store <4 x double> zeroinitializer, ptr [[TMP44]], align 895; CHECK-NEXT: [[TMP45:%.*]] = add i64 [[TMP11]], [[OFF_MUL_12]]96; CHECK-NEXT: [[TMP47:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP45]]97; CHECK-NEXT: store <4 x double> zeroinitializer, ptr [[TMP47]], align 898; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 499; CHECK-NEXT: [[TMP48:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]100; CHECK-NEXT: br i1 [[TMP48]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]101; CHECK: middle.block:102; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]103; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]104; CHECK: scalar.ph:105; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_MEMCHECK]] ]106; CHECK-NEXT: br label [[LOOP:%.*]]107; CHECK: loop:108; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]109; CHECK-NEXT: [[IV_SUB_5:%.*]] = add nsw i64 [[IV]], -5110; CHECK-NEXT: [[IDX_1:%.*]] = add i64 [[IV_SUB_5]], [[OFF]]111; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IDX_1]]112; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_1]], align 8113; CHECK-NEXT: [[IDX_2:%.*]] = add i64 [[IV_SUB_5]], [[OFF_MUL_2]]114; CHECK-NEXT: [[GEP_2:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IDX_2]]115; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_2]], align 8116; CHECK-NEXT: [[IDX_3:%.*]] = add i64 [[IV_SUB_5]], [[OFF_MUL_3]]117; CHECK-NEXT: [[GEP_3:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IDX_3]]118; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_3]], align 8119; CHECK-NEXT: [[IDX_4:%.*]] = add i64 [[IV_SUB_5]], [[OFF_MUL_4]]120; CHECK-NEXT: [[GEP_4:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IDX_4]]121; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_4]], align 8122; CHECK-NEXT: [[IDX_5:%.*]] = add i64 [[IV_SUB_5]], [[OFF_MUL_5]]123; CHECK-NEXT: [[GEP_5:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IDX_5]]124; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_5]], align 8125; CHECK-NEXT: [[IDX_6:%.*]] = add i64 [[IV_SUB_5]], [[OFF_MUL_6]]126; CHECK-NEXT: [[GEP_6:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IDX_6]]127; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_6]], align 8128; CHECK-NEXT: [[IDX_7:%.*]] = add i64 [[IV_SUB_5]], [[OFF_MUL_7]]129; CHECK-NEXT: [[GEP_7:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IDX_7]]130; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_7]], align 8131; CHECK-NEXT: [[IDX_8:%.*]] = add i64 [[IV_SUB_5]], [[OFF_MUL_8]]132; CHECK-NEXT: [[GEP_8:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IDX_8]]133; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_8]], align 8134; CHECK-NEXT: [[IDX_9:%.*]] = add i64 [[IV_SUB_5]], [[OFF_MUL_9]]135; CHECK-NEXT: [[GEP_9:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IDX_9]]136; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_9]], align 8137; CHECK-NEXT: [[IDX_10:%.*]] = add i64 [[IV_SUB_5]], [[OFF_MUL_10]]138; CHECK-NEXT: [[GEP_10:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IDX_10]]139; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_10]], align 8140; CHECK-NEXT: [[IDX_11:%.*]] = add i64 [[IV_SUB_5]], [[OFF_MUL_11]]141; CHECK-NEXT: [[GEP_11:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IDX_11]]142; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_11]], align 8143; CHECK-NEXT: [[IDX_12:%.*]] = add i64 [[IV_SUB_5]], [[OFF_MUL_12]]144; CHECK-NEXT: [[GEP_12:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IDX_12]]145; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_12]], align 8146; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1147; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]148; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]149; CHECK: exit:150; CHECK-NEXT: ret void151;152entry:153 %off.mul.2 = shl i64 %off, 1154 %off.mul.3 = mul i64 %off, 3155 %off.mul.4 = shl i64 %off, 2156 %off.mul.5 = mul i64 %off, 5157 %off.mul.6 = mul i64 %off, 6158 %off.mul.7 = mul i64 %off, 7159 %off.mul.8 = shl i64 %off, 3160 %off.mul.9 = mul i64 %off, 9161 %off.mul.10 = mul i64 %off, 10162 %off.mul.11 = mul i64 %off, 11163 %off.mul.12 = mul i64 %off, 12164 br label %loop165 166loop:167 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]168 %iv.sub.5 = add nsw i64 %iv, -5169 %idx.1 = add i64 %iv.sub.5, %off170 %gep.1 = getelementptr i64, ptr %dst, i64 %idx.1171 store double 0.000000e+00, ptr %gep.1, align 8172 %idx.2 = add i64 %iv.sub.5, %off.mul.2173 %gep.2 = getelementptr i64, ptr %dst, i64 %idx.2174 store double 0.000000e+00, ptr %gep.2, align 8175 %idx.3 = add i64 %iv.sub.5, %off.mul.3176 %gep.3 = getelementptr i64, ptr %dst, i64 %idx.3177 store double 0.000000e+00, ptr %gep.3, align 8178 %idx.4 = add i64 %iv.sub.5, %off.mul.4179 %gep.4 = getelementptr i64, ptr %dst, i64 %idx.4180 store double 0.000000e+00, ptr %gep.4, align 8181 %idx.5 = add i64 %iv.sub.5, %off.mul.5182 %gep.5 = getelementptr i64, ptr %dst, i64 %idx.5183 store double 0.000000e+00, ptr %gep.5, align 8184 %idx.6 = add i64 %iv.sub.5, %off.mul.6185 %gep.6 = getelementptr i64, ptr %dst, i64 %idx.6186 store double 0.000000e+00, ptr %gep.6, align 8187 %idx.7 = add i64 %iv.sub.5, %off.mul.7188 %gep.7 = getelementptr i64, ptr %dst, i64 %idx.7189 store double 0.000000e+00, ptr %gep.7, align 8190 %idx.8 = add i64 %iv.sub.5, %off.mul.8191 %gep.8 = getelementptr i64, ptr %dst, i64 %idx.8192 store double 0.000000e+00, ptr %gep.8, align 8193 %idx.9 = add i64 %iv.sub.5, %off.mul.9194 %gep.9 = getelementptr i64, ptr %dst, i64 %idx.9195 store double 0.000000e+00, ptr %gep.9, align 8196 %idx.10 = add i64 %iv.sub.5, %off.mul.10197 %gep.10 = getelementptr i64, ptr %dst, i64 %idx.10198 store double 0.000000e+00, ptr %gep.10, align 8199 %idx.11 = add i64 %iv.sub.5, %off.mul.11200 %gep.11 = getelementptr i64, ptr %dst, i64 %idx.11201 store double 0.000000e+00, ptr %gep.11, align 8202 %idx.12 = add i64 %iv.sub.5, %off.mul.12203 %gep.12 = getelementptr i64, ptr %dst, i64 %idx.12204 store double 0.000000e+00, ptr %gep.12, align 8205 %iv.next = add nuw nsw i64 %iv, 1206 %ec = icmp eq i64 %iv.next, %N207 br i1 %ec, label %exit, label %loop208 209exit:210 ret void211}212 213define void @check_creation_order(ptr %a, ptr %b, i32 %m) {214; CHECK-LABEL: @check_creation_order(215; CHECK-NEXT: entry:216; CHECK-NEXT: [[B2:%.*]] = ptrtoint ptr [[B:%.*]] to i64217; CHECK-NEXT: [[A1:%.*]] = ptrtoint ptr [[A:%.*]] to i64218; CHECK-NEXT: [[M_EXT:%.*]] = sext i32 [[M:%.*]] to i64219; CHECK-NEXT: [[INVARIANT_GEP:%.*]] = getelementptr double, ptr [[A]], i64 [[M_EXT]]220; CHECK-NEXT: br label [[VECTOR_MEMCHECK:%.*]]221; CHECK: vector.memcheck:222; CHECK-NEXT: [[TMP0:%.*]] = mul nsw i64 [[M_EXT]], -8223; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32224; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[A1]], [[B2]]225; CHECK-NEXT: [[DIFF_CHECK3:%.*]] = icmp ult i64 [[TMP1]], 32226; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK3]]227; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]228; CHECK: vector.ph:229; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]230; CHECK: vector.body:231; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]232; CHECK-NEXT: [[TMP3:%.*]] = getelementptr double, ptr [[INVARIANT_GEP]], i64 [[INDEX]]233; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x double>, ptr [[TMP3]], align 8234; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds double, ptr [[B]], i64 [[INDEX]]235; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x double>, ptr [[TMP5]], align 8236; CHECK-NEXT: [[TMP7:%.*]] = fadd <4 x double> [[WIDE_LOAD]], [[WIDE_LOAD4]]237; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds double, ptr [[A]], i64 [[INDEX]]238; CHECK-NEXT: store <4 x double> [[TMP7]], ptr [[TMP8]], align 8239; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4240; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 31996241; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]242; CHECK: middle.block:243; CHECK-NEXT: br label [[SCALAR_PH]]244; CHECK: scalar.ph:245; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 31996, [[MIDDLE_BLOCK]] ], [ 0, [[VECTOR_MEMCHECK]] ]246; CHECK-NEXT: br label [[LOOP:%.*]]247; CHECK: loop:248; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]249; CHECK-NEXT: [[GEP:%.*]] = getelementptr double, ptr [[INVARIANT_GEP]], i64 [[IV]]250; CHECK-NEXT: [[L_0:%.*]] = load double, ptr [[GEP]], align 8251; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds double, ptr [[B]], i64 [[IV]]252; CHECK-NEXT: [[L_1:%.*]] = load double, ptr [[GEP_B]], align 8253; CHECK-NEXT: [[ADD3:%.*]] = fadd double [[L_0]], [[L_1]]254; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds double, ptr [[A]], i64 [[IV]]255; CHECK-NEXT: store double [[ADD3]], ptr [[GEP_A]], align 8256; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1257; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 31999258; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]259; CHECK: exit:260; CHECK-NEXT: ret void261;262entry:263 %m.ext = sext i32 %m to i64264 %invariant.gep = getelementptr double, ptr %a, i64 %m.ext265 br label %loop266 267loop:268 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]269 %gep = getelementptr double, ptr %invariant.gep, i64 %iv270 %l.0 = load double, ptr %gep, align 8271 %gep.b = getelementptr inbounds double, ptr %b, i64 %iv272 %l.1 = load double, ptr %gep.b, align 8273 %add3 = fadd double %l.0, %l.1274 %gep.a = getelementptr inbounds double, ptr %a, i64 %iv275 store double %add3, ptr %gep.a, align 8276 %iv.next = add nuw nsw i64 %iv, 1277 %exitcond.not = icmp eq i64 %iv.next, 31999278 br i1 %exitcond.not, label %exit, label %loop279 280exit:281 ret void282}283